JPS6064382A - Character image display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a character image display control device, and more particularly to a device that enables external synchronization with a simple configuration.

Background of the Technology Currently, a character image display control device, that is, a CRT controller, built into a CRT display device used in a microcomputer system or a personal computer system, etc., usually displays images at a scanning cycle specific to each device. is performing an action. Therefore, when displaying an image signal from a television receiver, an image signal from a video device, and an image signal from a microcombination system or tri personal computer system on the same screen, It is necessary to perform so-called external synchronization to synchronize the image signal input from the outside with the display scanning cycle on the CRT controller side. In order to achieve such external synchronization, conventionally, a phase synchronization circuit (P
A method has been used in which the phase of the synchronous signal inside the CR1' controller is locked to an external signal or synchronous signal using a LL circuit. However, this method has the disadvantage that the circuit scale is large and the device configuration is sloppy. The present invention is based on the idea that even if an error in the minimum display unit occurs due to external synchronization, there is no need for phase locking as long as the error does not cause a visual problem. This makes it possible to achieve downsizing and cost reduction.

Prior Art and Problems FIG. 1 shows the configuration of a video system including a conventional character image display device (hereinafter referred to as a CRT controller). The system shown in the figure includes a television device 1, a CRT controller 2, an oscillation circuit 3, and a phase synchronization circuit (hereinafter referred to as PT).
(referred to as an L circuit) 4, a video memory 5, and a parallel-to-serial conversion circuit 6-. The television viewing device l may be, for example, a television receiver, or a device combining a video tape recorder and a monitor television, but it may be a device that transmits a horizontal synchronizing signal H (TV) and a vertical synchronizing signal V (TV). It must be possible to output the video signal, and it must be configured so that the internal video signal and the video signal input from the outside can be superimposed and displayed directly on the television screen.

In the system shown in FIG. 1, so-called superimposition (3) is possible, in which images such as characters read out from the video memory 5 are superimposed and displayed on the display screen of the television device 1 under the control of the CRT controller 2. be. The video memory 5 can be accessed from a personal computer, as shown in the figure, and text information is written therein. The read data from the video memory 5 is converted into a serial video output signal by a parallel-serial conversion circuit 6 and supplied to the television device 1, where it is mixed with the video signal inside the television learning device and displayed.

By the way, in the system shown in FIG. 1, in order to superimpose the internal video signal of the television device 1 and the video signal output from the video memory 5, a CRT is required.
It is necessary that the synchronization signal inside the controller 2 and the synchronization signals H (TV) and V (TV) from the television set 1 are synchronized. Therefore, in the system shown in the figure, the PLL circuit 4 generates a clock pulse CLK synchronized with the horizontal synchronizing signal 1 ((TV)) from the television computer 1 and supplies it to the CRT controller.
A horizontal (4) synchronization signal synchronized with the horizontal synchronization signal H (TV) from the television device I is created within the T controller. In addition, CRT controller 2
The horizontal synchronizing signal H (CRTC) created within is supplied to the PLL circuit 4 and compared with the horizontal synchronizing signal H (TV) from the television device 1. Also, television equipment
A vertical synchronizing signal V (TV) is supplied to the CRT controller 2 from the CRT controller 2. For example, when the system is powered on, the vertical counter inside the jDcRT controller 2 is initialized by the vertical synchronizing signal V (TV), and the vertical synchronizing signal V (TV) is supplied to the CRT controller 2. synchronization is performed. In this way, a horizontal synchronization signal and a vertical synchronization signal synchronized with each synchronization signal from the television device 1 are created. Furthermore, memory addresses synchronized with each of these synchronization signals are created and supplied to the video memory 5 to read out the image information, which is converted into a serial signal by the parallel-to-serial conversion circuit 6 and input to the television device 1. Ru.

In this way, the image signal inside the television device 1 and the text information from the video memory 5 are superimposed and displayed on the same screen. Note that the contents of the video memory 5 can be rewritten as appropriate by the computer system shown in the figure.

FIGS. 2(a) and 2(b) show the relationship between each synchronization signal on the television device side and the synchronization signal on the CRT controller side. Figure (a) shows the vertical synchronization signal v ('rv) and horizontal synchronization signal H (TV
) and the vertical synchronizing signal V (CR
TC) and the horizontal synchronization signal H (CRTC) are in an asynchronous state, that is, the CRT controller 2 is free-running.
Indicates the state in which On the other hand, Φ) in the figure shows each synchronization signal V (TV) and H (T
V) and the synchronization signal V(CRTC
) and H (CRTC) are synchronized.

FIG. 3 shows the internal configuration of a conventional CRT controller used in the system of FIG.

The CRT controller in the figure includes a horizontal counter 7, a horizontal period setting circuit 8, a comparator 9, a horizontal synchronization generating circuit lO1, a vertical counter 11. It is composed of a vertical synchronization setting circuit 12, a comparator 13, a vertical synchronization generation circuit 14, a memory address counter 15, a memory address counter control section 16, and the like.

In the CRT controller in Figure 3) 0-RA, ! Clock pulses CLK input from the PLLn path shown in FIG. 1 are counted by a horizontal counter 7 and a memory address counter 15, respectively. The clock pulse CLK is a so-called character clock, and one pulse corresponds to each character displayed on the screen.

The horizontal cycle setting circuit 8 stores in advance the number of character clocks in one horizontal cycle as a horizontal cycle set value, and the comparator 9 compares the set values of and with the output of the horizontal counter 7. When the two match, the comparator 9 outputs one pulse, and the horizontal counter 7 is reset by the pulse. This pulse is then input to a vertical counter 11 and counted. The count value of the vertical counter 11 is also compared in the comparator 13 with the value stored as the vertical cycle setting value in the vertical cycle setting circuit 12. When the two match, the vertical counter 11 is reset.

The outputs of the horizontal counter 7 and the vertical counter (7) 11 are supplied to the horizontal synchronization generation circuit 10 and the vertical synchronization generation circuit 14, respectively, to generate the vertical synchronization signal V (CRTC) and horizontal synchronization signal H (
CRTC) is created. Furthermore, when both the comparator 13 and the comparator 9 output a match signal, the memory address counter 15 is reset by the memory address counter control section 16.

Therefore, the memory address counter 15 is reset every one normal scanning period and outputs memory address data ADD for each character information of the video memory that stores image information for one screen.

By the way, in the above-mentioned CRT controller, the character clock CLK is created by controlling the PLL circuit according to the horizontal synchronization signal on the television set side, but since the PLL circuit is used, the hardware of the CRT controller is complicated. There were disadvantages in that the cost increased and it took a long time to pull in synchronization. In addition, since the vertical synchronization signal of the television display device initializes the vertical cursor (8) of the CRT controller only when the power is turned on, for example, if synchronization occurs due to noise or other causes while the screen is displayed, However, the phase difference between the signal from the television set and the signal from the CRT controller becomes 11, making it necessary to initialize the vertical counter again by turning the power back on.

Purpose of the Invention The purpose of the present invention is to:
In a character image display control device, based on the idea that both the horizontal counter and the vertical counter are initialized by an external synchronization signal in each horizontal scanning period and vertical scanning period, the hardware configuration is simplified and costs are reduced. The goal is to shorten synchronization pull-in time.

According to the invention, in a character image display device using a rask scan method, which regulates a horizontal scanning period and a vertical scanning period based on the outputs of a horizontal counter and a vertical counter, respectively, an external synchronizing signal is used. This is achieved by providing a character image display control device characterized in that both the horizontal counter and the vertical counter are initialized to a horizontal scanning period and a vertical scanning period, respectively.

Examples of the invention Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 4 shows the configuration of a character image display control device, ie, a video system using a CRT controller, according to an embodiment of the present invention. The system shown in the figure is
H7, CRT controller 18, oscillation circuit 19, video memory 20, and parallel-serial conversion circuit 21@, but no PLL circuit is used.

TV monitor device 17, oscillation circuit 19, video memory 2
0 and the parallel-to-serial conversion circuit 21 may be the same as those used in the system of FIG.

In the system shown in Figure 4, the CRT controller) 0-218
When the CRT controller operates in internal synchronization, the clock pulse CLK from the oscillation circuit 19 is counted by a horizontal counter and a vertical counter in the CRT controller 18 to generate a horizontal synchronization signal and a vertical synchronization signal with a preset period. A signal is created. Then, the video memory 20 is accessed at a timing synchronized with each of these synchronization signals,
The signal read from the video memory 20 is converted into a video signal via the parallel-to-serial conversion circuit 21 and the like, and is input to the television set 17 and displayed on the CR7 screen.

Further, when the CRT controller 18 operates in external synchronization mode, the horizontal synchronization signal) I (TV) and the vertical synchronization signal V (TV) from the television display device 17 are transmitted.
CR for each horizontal scanning period and vertical scanning period.
The horizontal and vertical counters in T-controller 18 are initialized.

Horizontal and vertical synchronizing signals are created in the CRT controller 18 in synchronization with each synchronizing signal from the television set 17, and a video signal is created based on these synchronizing signals and then output to the television screen. It is input to the sealing device 17. In this way, the image signal inside the television set 17 and the text information etc. from the video memory 20 are synchronously superimposed and displayed on the same screen.

FIG. 5 shows a detailed configuration of a CRT controller used in the system of FIG. 4 and according to an embodiment of the present invention. The CRT controller in the same figure, like the CRT controller in FIG. , a vertical synchronization generation circuit 30, a memory address counter 32, and a memory address counter control section 33, and further includes a horizontal synchronization position generation circuit 26, a vertical synchronization position generation circuit 31, and tristate buffers 34, 35, 36, .
It has 37.

In the CRT controller shown in FIG. 5, clock pulses CLK from the oscillation circuit 19 shown in FIG. 4 are counted by a horizontal counter 22 and a memory address counter 32, respectively. The output of the horizontal counter 22 is inputted as count data to a comparator 24 and sent to a horizontal period setting circuit 23.
It is compared with the horizontal period setting value outputted from (12). If both values match,
The comparator 24 outputs one pulse, and the horizontal counter 22 is reset by this pulse.

Further, this pulse is input to the vertical counter 27 as a count clock and counted. The count value of the vertical counter 27 is input as count data to the comparator 29 and compared with the vertical cycle setting value output from the vertical synchronization setting circuit 28. When both data match, the vertical counter 27 is reset. In this way, the horizontal counter 22 and the vertical counter 27 each count according to a preset count value. Then, the outputs of the horizontal counter 22 and the vertical counter 27 are input to the horizontal synchronization generation circuit 25 and the vertical synchronization generation circuit 30, respectively, to create horizontal and vertical synchronization signals H and V, respectively. Output. Furthermore, when both the comparators 24 and 29 output matching signals, the memory address counter control section 33 resets the memory address counter 32. In this case, the memory address counter 32 sequentially outputs memory addresses ADD for accessing the area of the video memory that stores image information for 18 screens.

In the above-mentioned CRT controller, when performing external synchronization using a synchronization signal from the television set, for example,
The external synchronization control signal CNT is set to a low level, for example, to cut off the tristate buffers 34 and 36, and turn the tristate buffers 35 and 37 on.

As a result, the horizontal and vertical synchronizing signals on the television set side are transferred to tri-state buffers 35 and 37, respectively.
The signal is inputted to the horizontal synchronization position generation circuit 26 and the vertical synchronization position generation circuit 31 via. Then, the horizontal synchronization position generation circuit 26 and the vertical synchronization position generation circuit 31 output the horizontal counter 22 and the vertical counter 27 at the time when the horizontal and vertical synchronization signals are inputted from the television learning device, respectively.
The count value of each counter in the synchronous state at the horizontal synchronous position and vertical synchronous position is loaded into . For this,
The horizontal counter 22 and the vertical counter 27 are set to predetermined count values at the positions of the horizontal and vertical synchronizing signals, respectively, and output counts at a period synchronized with each synchronizing signal of the television device. In the CRT controller shown in FIG. 5, the phase synchronization of clock pulses between the television device side and the CRT controller side is not performed, so a deviation in display in the minimum display unit occurs.
Since this deviation is very small compared to the display screen width, it does not pose any practical problem.

Effects of the Invention As described above, according to the present invention, in a CRT controller, the horizontal counter and the vertical counter are initialized for each horizontal scanning period and each vertical scanning period using an external synchronizing signal, so a phase synchronizing circuit is not required. This simplifies the circuit configuration and significantly shortens the synchronization pull-in time to a maximum of one horizontal scanning period or one vertical scanning period.

[Brief explanation of the drawing]

Figure 1 is a block circuit diagram showing a (15) video system using a conventional CRT controller, Figure 2 ial and (b) are waveform diagrams showing the synchronization status of vertical and horizontal synchronizing signals, and Figure 3 is a conventional FIG. 4 is a block circuit diagram showing the configuration of a CRT controller according to an embodiment of the present invention, and FIG. 5 is a block circuit diagram showing the configuration of a video system using a CRT controller according to an embodiment of the present invention. FIG. 2 is a block circuit diagram showing the configuration of a CRT controller related to FIG. 1.17: Television set, 2.18: CRT controller, 3.19: Oscillator circuit, 4: Phase synchronization circuit, 5, 20: Video memory, 6.21: Parallel-serial conversion circuit, 7.22: Horizontal counter , 8.23: Horizontal period setting circuit, 9.13.24, 29; Comparator, 10.25: Horizontal synchronization generation circuit, 11.27; Vertical counter, 12.28: Vertical period setting circuit, (16) 14 .30: Vertical synchronization generation circuit, 15.32: Memory address counter, 16.33: Memory address counter control section, 26; Horizontal synchronization position generation circuit, 31: Vertical synchronization position generation circuit, 34.35, 36, 37: ) license state buffer. Patent applicant Fujitsu Ltd. Patent application agent Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney Yukio Uchida Patent attorney Akiyuki Yamaguchi

Claims (1)

[Claims] In a character image display device using the rask scan method, which regulates the horizontal scanning period and vertical scanning period based on the outputs of a horizontal counter and a vertical counter, respectively, both the horizontal counter and the vertical counter regulate the horizontal scanning period and the vertical scanning period, respectively, according to an external synchronization signal. A character image display control device characterized in that initialization is performed every vertical scanning period.