CN111277725B - Automatic video detection phase synchronization system and method - Google Patents
Automatic video detection phase synchronization system and method Download PDFInfo
- Publication number
- CN111277725B CN111277725B CN201811493418.5A CN201811493418A CN111277725B CN 111277725 B CN111277725 B CN 111277725B CN 201811493418 A CN201811493418 A CN 201811493418A CN 111277725 B CN111277725 B CN 111277725B
- Authority
- CN
- China
- Prior art keywords
- signal
- data
- new
- frequency
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000001514 detection method Methods 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims description 27
- 230000000630 rising effect Effects 0.000 claims description 10
- 230000003139 buffering effect Effects 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
Abstract
The invention discloses a video automatic detection phase synchronization system, which comprises: the phase-locked loop unit receives a source frequency signal and generates a frequency reading signal according to the source frequency signal; and the adjusting signal unit is used for receiving the frequency reading signal, the vertical synchronizing signal and the data enable signal, synchronizing the frequency of each picture according to the vertical synchronizing signal and the data enable signal and further correcting the error of the output frequency.
Description
Technical Field
The present invention relates to the field of video automatic detection phase synchronization technology, and in particular, to a video automatic detection phase synchronization system and method.
Background
Conventionally, when a High Definition Multimedia Interface (HDMI) transmits data, input/output resolutions are different, and therefore, a picture needs to be enlarged or reduced, and a frequency needs to be adjusted to satisfy a same Frame Rate (Frame Rate). In the process of frequency adjustment, the most accurate frequency may not be achieved due to some special specifications, and the picture error may be caused under the accumulated error for a long time. In the frequency conversion, a Phase-Locked Loop (PLL) circuit is usually used to generate a required output frequency, and a high precision is required in HDMI, otherwise, frame rate difference and picture error are caused.
Therefore, how to effectively achieve the automatic video phase detection is a subject to be studied by various manufacturers.
Disclosure of Invention
The embodiment of the invention provides a system and a method for video automatic detection phase synchronization, which are used for detecting a phase, further effectively adjusting a horizontal synchronization signal and a vertical synchronization signal, correcting an output frequency error, further enabling each picture to be synchronous, and solving the problem that each picture is not synchronous in output in the prior art.
In order to solve the technical problem, the invention is realized as follows:
in a first aspect, a video auto-detection phase synchronization system is provided, which includes: the phase-locked loop unit receives a source frequency signal and generates a frequency reading signal according to the source frequency signal; and the adjusting signal unit is used for receiving the frequency reading signal, the vertical synchronizing signal and the data enabling signal, synchronizing the frequency of each picture according to the vertical synchronizing signal and the data enabling signal and further correcting the error of the output frequency.
In a second aspect, a method for video auto-detection of phase synchronization is provided, which includes: receiving a source frequency signal by using a phase-locked loop unit, and generating a frequency reading signal according to the source frequency signal; and the application adjusting signal unit receives the frequency reading signal, the vertical synchronizing signal and the data enabling signal, synchronizes the frequency of each picture according to the vertical synchronizing signal and the data enabling signal, and further corrects the error of the output frequency.
In the embodiment of the invention, the system and the method for video automatic detection phase synchronization can detect the phase, and further effectively adjust the horizontal synchronization signal and the vertical synchronization signal to correct the output frequency error, so that each output picture can be synchronized.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a diagram of an embodiment of a video auto-detection phase synchronization system;
FIG. 2 is a signal waveform diagram to which the present invention is applied;
FIG. 3 is a flowchart illustrating a method for video auto-detection phase synchronization according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Please refer to fig. 1, which is a schematic diagram of a video auto-detection phase synchronization system according to an embodiment of the present invention. The video auto-detection phase synchronization system comprises: a phase locked loop unit 11 and an adjustment signal unit 12. The phase-locked loop unit 11 receives the source frequency signal and generates a frequency reading signal according to the source frequency signal. The adjusting signal unit 12, coupled to the phase-locked loop unit 11, receives the frequency reading signal, the vertical synchronization signal and the data enable signal, and synchronizes the frequency of each frame according to the vertical synchronization signal and the data enable signal, so as to correct the error of the output frequency.
The aforementioned adjusting signal unit 12 further includes: a detection phase unit 121 for receiving the vertical synchronization signal and the data enable signal, and synchronizing a start point of each frame according to the vertical synchronization signal and the data enable signal to correct a time difference of each frame, thereby synchronizing a frequency of each frame; a pulse generating unit 122 for receiving the reset signal and the frequency reading signal, correcting an error of the output frequency according to the reset signal and the frequency reading signal, and outputting a new horizontal synchronization signal, a new vertical synchronization signal, and a new data enable signal; the buffer unit 123 receives the new horizontal synchronization signal, the new vertical synchronization signal, the new data enable signal, the frequency write signal, the frequency read signal, and the data signal, adjusts the data signal according to the new vertical synchronization signal, the new horizontal synchronization signal, and the new data enable signal to generate a new data signal, obtains an output format according to the new data enable signal, and applies the output format to the output frequency and the new data signal.
In addition, the buffer unit 123 may directly output a new horizontal synchronization signal, a new vertical synchronization signal, a new data enable signal, and a new data signal and an output frequency to which the output format is applied. The detection phase unit 121 generates a reset signal according to the vertical synchronization signal and the data enable signal.
In addition, in the present embodiment, valid data and blank data are carried between every two pulses in the horizontal synchronization signal, and the horizontal synchronization signal determines the start position of each line. The vertical synchronization signal has an active line and a blank line between every two pulses, and the vertical synchronization signal determines the start position of each frame. The data enable signal determines the position of the first active line. The detecting phase unit 121 uses the data enable signal pulse to start the reset signal, the detecting phase unit 121 will start the reset signal at the time of the rising edge of the first pulse of the data enable signal, and adjust the blank data of the horizontal synchronization signal and the blank line time of the vertical synchronization signal according to the frequency reading signal output by the phase-locked loop unit 11 at the time of the rising edge of the second pulse of the data enable signal, so as to correct the error of the output frequency. The detecting phase unit 121 determines that the data signal is the first line by determining that the high level of the first pulse of the data enable signal is preceded by the pulse of the vertical synchronization signal before adjusting the blank data of the horizontal synchronization signal and the blank line of the vertical synchronization signal.
In this embodiment, during the transmission through the HDMI frame, the resolution (resolution) is changed according to the preference of the user or the difference of the output screen, and if the resolution is changed, the data is output to the display screen after scaling (scaler) is performed in the circuit.
In the process of changing the resolution, since the same frame rate needs to be satisfied, the pixel frequency also changes, as shown in the following formula:
because of the limited number of bits available, the input/output resolution can be rounded without division, and thus the most accurate frequency cannot be presented.
If there is an error in the pixel conversion process of each frame, the error of each frame will be caused by long-time accumulation, so the circuit designed by the present invention can synchronize each frame by the detecting phase unit 121 at the starting point of each frame to solve the problem of time error.
In the process of signal scaling conversion, the input frequency from the HDMI source is different from the output frequency of the signal scaler.
For example, in the case where 720 × 480P (858 × 525) is greater than 640 × 480P (800 × 525), the HDMI source frequency is 27.027 megahertz (MHz) (the frame rate is 60 hertz (Hz)), and the output frequency is ((800 × 525)/(858 × 525)) -27.027 MHz, 800/858 ═ 0.932400 infinite loop, so that the 25.2MHz obtained by multiplying 27.027MHz is also a rounded value, which causes a frequency error.
The signal conditioning unit 12 of the present invention performs pixel conversion on the original video data by using different sampling rates (sample rates), stores the increased or decreased data in the buffer unit 123, and determines when to output the data by using the detection phase unit 121. In the pixel converting unit (not shown), for example, 720 × 480P (858 × 525) is greater than 640 × 480P (800 × 525), the frame is a resolution reduction conversion, and the frame is changed from 720 effective pixels to 640 effective pixels, the converting manner of the pixel converter 123 of the embodiment is that every nine pixels are one less pixel, and so on, the line conversion is also the same. When the resolution is an improved conversion, the conversion is performed by finding the smallest integer ratio and then repeating the pixels or lines.
Fig. 2 is a signal waveform diagram to which the present invention is applied. As shown in fig. 2, before describing the method of detecting the phase, it is necessary to first describe some signals used in the circuits, such as a data enable signal, a horizontal synchronization signal, and a vertical synchronization signal (the horizontal synchronization signal and the vertical synchronization signal are not fixed as high pulses or low pulses, and the following description will use high pulses as an example, depending on the resolution).
Data enable signal: when the data is high pulse, the data transmitted in this period is all video data, and when the data is low pulse, the data is not video data, as shown in fig. 2, when the data enable signal is high pulse, the data enable signal is effective video frequency, and the combination of high pulse and low pulse displayed by the data enable signal is the total frequency of each line.
The horizontal synchronization signal represents the start position of each line, and valid data (active data) and blank data (blanking data) are carried between every two pulses, as shown in fig. 2, the low pulse time between two pulses is blank data, and the high pulse time is valid data.
The vertical synchronization signal represents the start position of each frame, and each two pulses are accompanied by an active line (active line) and a blank line (blanking line), as shown in fig. 2, the low pulse time between two pulses is the blank line, and the high pulse time is the active line.
For example, a resolution of 1920 x 1080 indicates that the frequency of the valid video is 1920, which also indicates that 1920 data samples are obtained after 1920 samples of the data are started. An active line equal to 1080 indicates that each picture consists of 1080 active lines.
Since the start position of each frame is determined by the vertical synchronization signal and the position of the first valid line is determined by the data enable signal, in this embodiment, during phase detection, the reset is performed at the rising edge of the first input data enable signal, and the reset is set at the rising edge of the second data enable signal, at this time, video data output is started, and the pulse of the vertical synchronization signal is preceded by the high pulse of the first data enable signal to ensure that the data enable is the first line, and the time for changing the blank is used to solve the error caused by the error due to the frequency conversion.
FIG. 3 is a flowchart illustrating a method for video auto-detection phase synchronization according to an embodiment of the present invention. As shown in fig. 3, the pll unit 11 receives a source clock signal and generates a clock read signal according to the source clock signal (s201), and the signal adjusting unit 12 receives the clock read signal, a vertical synchronization signal and a data enable signal and synchronizes the frequency of each frame according to the vertical synchronization signal and the data enable signal to correct the error of the output frequency (s 202).
In this embodiment, the step of applying the adjustment signal unit further includes: the application detection phase unit 121 receives the vertical synchronization signal and the data enable signal, and synchronizes the start point of each frame according to the vertical synchronization signal and the data enable signal to correct the time difference of each frame, thereby synchronizing the frequency of each frame; the application pulse generating unit 122 receives the reset signal and the frequency reading signal, further corrects an error of the output frequency according to the reset signal and the frequency reading signal, and outputs a new horizontal synchronization signal, a new vertical synchronization signal, and a new data enable signal; the application buffer unit 123 receives the new horizontal synchronization signal, the new vertical synchronization signal, the new data enable signal, the frequency write signal, the frequency read signal, and the data signal, adjusts the data signal according to the new vertical synchronization signal, the new horizontal synchronization signal, and the new data enable signal, generates a new data signal, obtains an output format according to the new data enable signal, and applies the output format to the output frequency and the new data signal. The buffer unit 123 may directly output the new horizontal synchronization signal, the new vertical synchronization signal, the new data enable signal, and the output frequency and the new data signal using the output format.
In this embodiment, valid data and blank data are carried between every two pulses in the horizontal synchronization signal, and the horizontal synchronization signal determines the start position of each line. The vertical synchronization signal has an active line and a blank line between every two pulses, and the vertical synchronization signal determines the start position of each frame. The data enable signal determines the position of the first active line. The detecting phase unit 121 uses the pulse of the data enable signal to enable the reset signal, wherein the detecting phase unit 121 will enable the reset signal at the time of the rising edge of the first pulse of the data enable signal, and adjust the blank data of the horizontal synchronization signal and the blank line time of the vertical synchronization signal according to the frequency reading signal outputted by the phase-locked loop unit 11 at the time of the rising edge of the second pulse of the data enable signal, so as to correct the error of the output frequency. The detecting phase unit 121 determines that the data signal is the first line by determining that the high level of the first pulse of the data enable signal is preceded by the pulse of the vertical synchronization signal before adjusting the blank data of the horizontal synchronization signal and the blank line of the vertical synchronization signal.
In summary, the present invention provides a system and method for video synchronization with automatic phase detection, so as to detect the phase and further effectively adjust the horizontal synchronization signal and the vertical synchronization signal to correct the output frequency error, thereby synchronizing each frame. The invention synchronizes each picture by detecting the phase, so the tolerance of the frequency generated by the phase-locked loop circuit is higher.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (14)
1. An automatic video detection phase synchronization system, comprising:
the phase-locked loop unit receives a source frequency signal and generates a frequency reading signal according to the source frequency signal;
the adjusting signal unit is used for receiving the frequency reading signal, the vertical synchronizing signal and the data enabling signal, synchronizing the frequency of each picture according to the vertical synchronizing signal and the data enabling signal and further correcting the error of the output frequency;
wherein the adjustment signal unit further comprises:
the detection phase unit is used for receiving the vertical synchronizing signal and the data enabling signal and synchronizing the starting point of each picture according to the vertical synchronizing signal and the data enabling signal so as to correct the time difference of each picture;
the pulse generating unit is used for receiving a reset signal and the frequency reading signal and outputting a new horizontal synchronizing signal, a new vertical synchronizing signal and a new data enable signal according to the reset signal and the frequency reading signal;
and the buffer unit receives the new horizontal synchronization signal, the new vertical synchronization signal, the new data enable signal and the data signal, generates a new data signal according to the new vertical synchronization signal, the new horizontal synchronization signal and the new data enable signal, obtains an output format according to the new data enable signal, and applies the output format to the output frequency and the data signal.
2. The video auto-detection phase synchronization system of claim 1, wherein valid data and blank data are carried between every two pulses of the horizontal synchronization signal, and the horizontal synchronization signal determines the start position of each line.
3. The video auto-detection phase synchronization system of claim 1, wherein an active line and a blank line are carried between every two pulses in the vertical synchronization signal, and the vertical synchronization signal determines a start position of each of the frames.
4. The video auto-detection phase synchronization system of claim 3, wherein the data enable signal determines a position of the first active line.
5. The video auto-detection phase synchronization system of claim 1, wherein the detection phase unit applies the pulse of the data enable signal to activate the reset signal, the detection phase unit activates the reset signal at the time of the rising edge of the pulse of the first one of the data enable signals, and adjusts the timing of the blank data of the horizontal synchronization signal and the blank line of the vertical synchronization signal according to the frequency read signal output by the phase-locked loop unit at the time of the rising edge of the pulse of the second one of the data enable signals to correct the error of the output frequency.
6. The video automatic detection phase synchronization system of claim 5, wherein the detection phase unit confirms that the high level of the first pulse of the data enable signal is preceded by the pulse of the vertical synchronization signal before adjusting the timing of the blank data of the horizontal synchronization signal and the blank line of the vertical synchronization signal to ensure that the data signal is the first line.
7. The video auto-detection phase synchronization system of claim 1, wherein the buffering unit outputs the new horizontal synchronization signal, the new vertical synchronization signal, the new data enable signal, and the new data signal and the output frequency using the output format.
8. A method for video auto-detection of phase synchronization, comprising:
receiving a source frequency signal by using a phase-locked loop unit, and generating a frequency reading signal according to the source frequency signal;
an application adjusting signal unit receives the frequency reading signal, the vertical synchronizing signal and the data enabling signal, synchronizes the frequency of each picture according to the vertical synchronizing signal and the data enabling signal, and further corrects the error of the output frequency;
wherein the step of applying the adjustment signal unit further comprises:
receiving the vertical synchronizing signal and the data enabling signal by using a detecting phase unit, and synchronizing the starting point of each picture according to the vertical synchronizing signal and the data enabling signal so as to correct the time difference of each picture;
the application pulse generating unit receives a reset signal and the frequency reading signal and outputs a new horizontal synchronizing signal, a new vertical synchronizing signal and a new data enabling signal according to the reset signal and the frequency reading signal;
and the application buffer unit is used for receiving the new horizontal synchronizing signal, the new vertical synchronizing signal, the new data enable signal, the frequency reading signal and the data signal, generating a new data signal according to the new vertical synchronizing signal, the new horizontal synchronizing signal and the new data enable signal, obtaining an output format according to the new data enable signal, and applying the output format to the output frequency and the new data signal.
9. The method of claim 8, wherein the horizontal synchronization signal is a horizontal synchronization signal, wherein valid data and blank data are carried between every two pulses, and the horizontal synchronization signal determines a start position of each line.
10. The method of claim 8, wherein an active line and a blank line are carried between every two pulses of the vertical synchronization signal, and the vertical synchronization signal determines a start position of each of the frames.
11. The method of claim 9, wherein the data enable signal determines a position of the first active line.
12. The method of claim 8, wherein the detecting phase unit uses the pulse of the data enable signal to enable the reset signal, the detecting phase unit enables the reset signal at a rising edge of a first pulse of the data enable signal, and adjusts blank data of the horizontal sync signal and blank line time of the vertical sync signal according to the frequency read signal output by the phase-locked loop unit at a rising edge of a second pulse of the data enable signal to correct the error of the output frequency.
13. The method of claim 12, wherein the detection phase unit is preceded by the timing of adjusting the blank data of the horizontal sync signal and the blank line of the vertical sync signal and is preceded by the high level of the first pulse of the data enable signal by the pulse of the vertical sync signal to ensure that the data signal is the first line.
14. The method of claim 8, wherein the buffer unit outputs the new horizontal sync signal, the new vertical sync signal, the new data enable signal, and the new data signal and the output frequency using the output format.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107216482U TWM575585U (en) | 2018-12-04 | 2018-12-04 | Automatic video detecting phase synchronization system |
| TW107216482 | 2018-12-04 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111277725A CN111277725A (en) | 2020-06-12 |
| CN111277725B true CN111277725B (en) | 2022-02-25 |
Family
ID=66591336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811493418.5A Active CN111277725B (en) | 2018-12-04 | 2018-12-07 | Automatic video detection phase synchronization system and method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN111277725B (en) |
| TW (1) | TWM575585U (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6316974B1 (en) * | 2000-08-26 | 2001-11-13 | Rgb Systems, Inc. | Method and apparatus for vertically locking input and output signals |
| CN100501565C (en) * | 2005-07-14 | 2009-06-17 | 中华映管股份有限公司 | Light-source driver and method for projector |
| KR100747668B1 (en) * | 2005-10-31 | 2007-08-08 | 삼성전자주식회사 | Video signal receiver including display synchronizing signal generation device and control method thereof |
| US9122443B1 (en) * | 2008-05-01 | 2015-09-01 | Rockwell Collins, Inc. | System and method for synchronizing multiple video streams |
| CN107784992A (en) * | 2016-08-25 | 2018-03-09 | 晨星半导体股份有限公司 | Display control apparatus and control method |
-
2018
- 2018-12-04 TW TW107216482U patent/TWM575585U/en unknown
- 2018-12-07 CN CN201811493418.5A patent/CN111277725B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| TWM575585U (en) | 2019-03-11 |
| CN111277725A (en) | 2020-06-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9147375B2 (en) | Display timing control circuit with adjustable clock divisor and method thereof | |
| US7286126B2 (en) | Apparatus for and method of processing display signal | |
| TWI220368B (en) | Method and apparatus for bridging different video format | |
| US8502919B2 (en) | Video display device and video display method | |
| JP4154820B2 (en) | Dot clock adjustment method and dot clock adjustment device for image display device | |
| US20050057551A1 (en) | Apparatus and method for image frame synchronization | |
| US8405774B2 (en) | Synchronization signal control circuit and display apparatus | |
| US8917280B2 (en) | Apparatus and method for controlling display devices | |
| JPH0783467B2 (en) | TV display system | |
| US7535982B2 (en) | Method and apparatus for adjusting phase of sampling frequency of ADC | |
| TW538631B (en) | Digital synchronization of video signals | |
| CN111277725B (en) | Automatic video detection phase synchronization system and method | |
| JP4017335B2 (en) | Video signal valid period detection circuit | |
| JP6788996B2 (en) | Semiconductor devices, video display systems and video signal output methods | |
| US8379149B2 (en) | Display apparatus and control method thereof | |
| KR100654771B1 (en) | Display apparatus and control method thereof | |
| JP2009077042A (en) | Device and method for processing video image | |
| KR20010070301A (en) | Synchronous frequency converting circuit | |
| JP4744212B2 (en) | Image display device control method and image display device | |
| US6765620B2 (en) | Synchronous signal generation circuit and synchronous signal generation method | |
| US7202865B2 (en) | Image signal repeater apparatus, image display apparatus with image signal repeater function, and method of controlling same | |
| JP3814955B2 (en) | Synchronization signal generating circuit for television receiver and television receiver | |
| JP2001142438A (en) | Synchronous signal period measuring device | |
| JP4291618B2 (en) | Synchronization control method and image display apparatus | |
| JP3960716B2 (en) | Automatic clock phase adjustment device for pixel-compatible display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |