JP4744212B2 - Image display device control method and image display device - Google Patents

Description

  The present invention relates to an image display apparatus control method and an image display apparatus. In particular, the present invention relates to an image display apparatus control method and an image display apparatus that sample and display an analog video signal at an appropriate cycle and phase.

  Flat panel display devices such as liquid crystal panels and plasma display panels are thin and lightweight, and are widely used as display devices for display units of television receivers and computer display devices. In addition, a micro device called a liquid crystal or DMD is widely used as a display device in a projection data projector or a projection television. Further, large display devices using LEDs, organic EL for small display devices, and the like have begun to spread. In the matrix type display device in which the structure of one pixel is determined in advance, when the input image signal is an analog signal, it is necessary to display it after converting it to digital data using an A / D converter. In general, an analog video signal is not accompanied by a clock for sampling the signal, and therefore it is necessary to generate a sampling clock on the receiving side. The frequency of the sampling clock must be determined appropriately according to the type of the input video signal. Also, video signals that are created by converting a digital image into analog, such as a video output signal of a personal computer, sample around the center of one pixel because the brightness level changes for each pixel. Otherwise, blurring of the video may occur.

  For the above reasons, it is necessary to optimize not only the frequency of the sampling clock but also the phase with respect to the input video signal, but various delays, depending on the cables and connectors in the transmission path, passive elements and active elements, Since the waveform is disturbed, there is a problem that the frequency and phase cannot be determined in advance. Methods for adjusting the frequency and phase of these sampling clocks are disclosed in the following patent documents.

JP-A-7-219485 JP-A-9-149291 Japanese Patent No. 3486343 Japanese Patent No. 3586116 JP 2001-166766 A JP 11-119723 A

  In any of the above documents, a method for adjusting the frequency and phase of a sampling clock based on the characteristics of sampled image data is disclosed. As a characteristic of image data, correlation of video signals between frames (Patent Document 1). The autocorrelation of image data sampled at different phases (Patent Document 2), the difference between adjacent pixels (Patent Document 3, Patent Document 4, Patent Document 5), and the average luminance of the effective video period (Patent Document 6) are used. .

  According to the method disclosed in the above document, a feature amount is obtained using image data sampled while changing the phase, and the phase is adjusted based on the feature amount. A plurality of frames are required for detection of the image, and if the video changes during the adjustment, the image data cannot be compared, so that the phase cannot be adjusted correctly.

  Further, the relationship between the adjusted sampling clock and the video signal varies depending on the temperature characteristics of the clock generator (PLL) and the A / D converter, the temperature characteristics on the video signal generator side, or the like. For example, in recent high-resolution video signals such as 1280 pixels × 1024 pixels and 1600 pixels × 1200 pixels, the cycle of one clock is shortened, and a slight phase change is displayed as a disturbance of the image. It is necessary to readjust the phase according to the change. In the method described in the above document, check whether it is necessary to readjust the phase, accept the display of video disturbance due to the change of the sampling frequency or phase during the readjustment of the phase, or during the adjustment period. Needed to stop displaying video.

  The present invention has been made in view of the above problems, and by adjusting the phase based on image data sampled with a single phase, it is possible to adjust the phase with a video signal of one frame or less. An object of the present invention is to provide an image display device capable of adjusting the phase of a sampling clock even if the video is a moving image that changes every frame.

  It is another object of the present invention to provide an image display device capable of displaying an image without disturbance even during the phase adjustment of the sampling clock.

The present invention
A method of controlling an image display device that samples an analog video signal including an image signal and a synchronization signal to generate digital image data, and displays an image using the generated image data,
Sampling the synchronization signal and the image signal based on a sampling clock that is not necessarily synchronized with the video signal;
Obtaining a first phase corresponding to a time difference of the sampling clock with respect to the video signal from the sampled synchronization signal;
Receiving the image data sampled in the sampling step, and generating resampled image data equivalent to the image data obtained when sampling is performed at a different phase in the sampling step;
Extracting a feature amount from the generated resampled image data;
Determining an optimal resampling period and phase shift amount for displaying an image based on a feature amount of the resampling image data;
And a step of performing phase control for resampling based on the first phase, the resampling period and the phase shift amount.

  According to the control method of the image display device according to the present invention, the synchronization signal and the image signal are sampled based on the sampling clock that is not necessarily synchronized with the video signal, and the time difference of the sampling clock with respect to the video signal is sampled from the sampled synchronization signal. A corresponding first phase is obtained, a sampled image signal is received, and first resampled image data equivalent to the image data obtained when the A / D converter is sampled at a different phase is generated. , Detecting the feature amount from the generated first resampled image data, and controlling the phase of the resampled image data to be displayed from the first phase and the detected feature amount, thereby performing phase adjustment at high speed So that the video will not change during the adjustment, A case but that varies can also be properly adjusted phase.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of an image display apparatus according to the present invention. A video signal including a synchronization signal and an image signal is input from the input terminal 1. There are various formats for video signals. Here, a case where a video signal is a composite video signal in which an image signal and a synchronization signal are superimposed will be described. The video signal input to the input terminal 1 is input to the A / D converter 2. On the other hand, the clock generator 3 generates a sampling clock for converting the video signal input to the input terminal 1 into digital data by the A / D converter 2. The frequency of the sampling clock generated by the clock generator 3 is higher than the signal band of the video signal input to the input terminal 1, and is preferably about 1.5 times the frequency of the signal band. The sampling clock is not necessarily synchronized with the video signal (particularly the image signal) input from the input terminal 1.

  The sampling clock generated by the clock generation unit 3 is input to the A / D changing unit 2, and the A / D converter 2 converts the video signal input to the input terminal 1 into digital image data. The image data output from the A / D converter 2 is input to the first digital filter 4 and the synchronization processing unit 5.

  The synchronization processing unit 5 separates the synchronization signal (Vsync, Hsync) from the input image data. The separated synchronization signal is composed of a horizontal synchronization signal Hsync and a vertical synchronization signal Vsync, and is used, for example, for display timing control of the entire image display apparatus for specifying the position of image data to be displayed and displaying an image correctly. It is done.

The synchronization processing unit 5 compares the horizontal synchronization signal Hsync separated from the video signal with a threshold Ls, and obtains a first phase Δ corresponding to the time difference of the sampling clock with respect to the video signal (for example, the horizontal synchronization signal Hsync). The threshold value Ls is set to a value that is ½ of the peak value of the horizontal synchronization signal Hsync, for example. FIG. 2 is a diagram showing an example of the relationship between the separated horizontal synchronization signal and the threshold value, and shows the falling portion of the horizontal synchronization signal Hsync in one line of the video signal. In FIG. 2, the horizontal direction indicates time or the horizontal position, and the vertical axis indicates the signal level. In the figure, the white circles are data sampled by the A / D converter 2 (of which some of them are denoted by symbols S _j−3 , S _j−2 , S _j−1 , S _j , S _{j + 1} , S _{j + 2)} . Ls indicates the threshold level. The symbols S _j-3 , S _j-2 , S _j−1 , S _j , S _{j + 1} , S _{j + 2,} etc. are also used to represent sampling points.

FIG. 2 shows a point P at which the value of the sampled synchronization signal passes the threshold value Ls during the sampling point S _j−1 to S _j . Here, “the value of the sampled synchronization signal passes the threshold value Ls during the period from the sampling point S _j−1 to S _j ” means that the sampling point S _j−1 of the preceding sampling point S _j−1 is among the sampling points that _{follow each} other. This means that the value of the sample data is higher than the threshold value Ls, and the value of the sample data at the subsequent sampling point S _j is lower than the threshold value Ls. (Note that when the phase with respect to the sampling clock is detected at the rising edge of the horizontal synchronization signal Hsync, “the value of the sampled synchronization signal passes the threshold value Ls during the period from the sampling points S _j−1 to S _j ”. Indicates that the sampling data value of the preceding sampling point S _j-1 is lower than the threshold value Ls and the sampling data value of the subsequent sampling point S _j is higher than the threshold value Ls among the sampling points that follow each other. means.)

The synchronization signal processing unit 5 is based on the value of the sampling point data S _j−1 located immediately before the passing point P and the value of the sampling point data S _j located immediately after the passing point P and the threshold Ls as follows. The first phase Δ is obtained using equation (1).
Δ = (Ls−S _j ) / (S _j−1 −S _j ) (1)

As described above, the sampling clock generated by the clock generation unit 3 is higher than the signal band of the video signal, and the phase is not necessarily synchronized with the video signal, so the data S _{j of the} sampling points located on both sides of the passing point P. The values of ₋₁ and S _j vary from line to line. Accordingly, the first phase Δ output from the synchronization processing unit 5 also changes for each line. FIG. 3 is a diagram illustrating an example of a change in the first phase Δ output from the synchronization processing unit 5, where the horizontal direction h is the sampling point of the A / D converter 2 and the vertical direction v is the vertical position of the video signal. (A horizontal line represents one line), and P _i to P _{i + 3} are points where the value of the horizontal synchronizing signal passes the threshold value Ls. In FIG. 3, P _i is a position close to S _j−1 (sampling point immediately before P _i ), P _{i + 1} is a position close to S _j (sampling point immediately after P _{i + 1} ), and P _{i + 2} is S _A case is shown in the vicinity of _j-1 (sampling point immediately before P _{i + 2} ) and S _j (sampling point immediately after P _{i + 2} ).

As shown in FIG. 3, the first phase Δ output from the synchronization processing unit 5 (Δ _i to Δ _{i + 3 in} FIG. ₃ ) indicates a change in phase for each line. By using it, the phase for each line of the image data sampled by the A / D converter 2 is obtained.

  The first phase Δ obtained as described above is input to the horizontal AFC 6, and the horizontal AFC 6 changes abruptly when Δ is obtained when the periodicity of the horizontal period is disturbed due to, for example, noise or disturbance of the video signal itself. In order to prevent this, a stable first phase Δ ′ is output to the phase control unit 7. The horizontal AFC 6 is used for stable display with respect to the disturbance of the horizontal period, and therefore may not be provided if the disturbance of the periodicity of the video signal does not occur.

  The first digital filter 4 shifts the phase of the input digital video signal. This phase shift is equivalent to data when the sampling phase of the A / D converter 2 is shifted, that is, resampling equivalent to image data obtained when the A / D converter 2 samples at a different phase. This is for obtaining image data. The phase shift amount is determined by the control amount θ (n) output from the phase control unit 7, and details will be described later.

  When the digital filter 4 is used for the phase shift as described above, the frequency characteristics and the group delay are relatively flat to the sampling frequency regardless of how the respective sets of filter coefficients are determined. It is necessary to be.

  4 and 5 are diagrams showing examples of amplitude characteristics and group delay characteristics used in the first digital filter 4. The horizontal axis of FIG. 4 shows frequency, the vertical axis shows amplitude, and the horizontal axis of FIG. The frequency and the vertical axis indicate the delay time. fs is the sampling frequency of the A / D converter 2, and both the amplitude characteristic and the group delay characteristic show substantially flat characteristics up to the sampling frequency fs.

  An example of the filter coefficient (coefficient given to each tap) for obtaining the characteristics of FIGS. 4 and 5 is shown in FIG. 6 below. The table of FIG. 6 shows combinations of coefficients capable of 32 phase shifts with respect to the sampling period of the A / D converter 2, where δ0 to δ31 indicate the respective phases, and h0 to h13 indicate the filter. The coefficient is shown. If it is necessary to shift the phase more finely, the number of stages in the phase direction is increased (increase the number of combinations of filter coefficients), and in the case of simplification, the number of stages can be reduced, and the required display quality. In consideration of the above, an arbitrary number of stages can be selected. 6 shows the filter coefficient when the digital filter 4 has 14 taps, the present invention is not limited to this, and the accuracy is higher than the amplitude characteristic and group delay characteristic shown in FIGS. 4 and 5 (sampling frequency). If the filter is configured with a high flatness up to fs), the number of taps can be increased, and if the accuracy required for the filter is not so high, the number of taps can be reduced. The number of taps can be selected.

  The first digital filter 4 shifts the phase of the input image data based on the phase θ (n) output from the phase control unit 7 and outputs resampling image data.

Next, the operation of the phase control unit 7 will be described.
The phase control unit 7 calculates the first phase Δ ′ output from the horizontal AFC 6, the phase k generated inside the phase control unit 7, the number q of phase shifts, the time Tk for one phase shift, and the resampling period T. The resampling phase θ (n) is calculated using the following equation (2A).
θ (n) = Δ ′ + k / q + nT
(K = 0, 1, 2, 3... T / Tk) (2A)

Here, n represents the data number counted from the horizontal synchronizing signal, that is, the nth data counted from the horizontal synchronizing signal.
In this example, since the number of phase shift stages is 32, the following equation (2B) is used to calculate θ (n).
θ (n) = Δ ′ + k / 32 + nT (2B)

  Assuming that the resampling period T is, for example, sampled at a frequency 1.5 times higher than the dot clock frequency constituting the pixel of the input video signal by the A / D converter 2, the resampling period T is This is 1.5 times the dot clock cycle. This is the image data (output of the A / D converter 2) obtained by sampling the input video signal at a frequency (1 / 1.5 cycle) 1.5 times the dot clock, that is, the actual number of pixels. This is an operation of converting (reducing) the image data sampled as 1.5 times the number of pixels to the original number of pixels.

  As described above, since the sampling frequency is not limited to 1.5 times, this resampling period T is also calculated in accordance with the actual sampling period.

As described above, the phase control unit 7 initially sets the internally generated phase k to 0, increments n by 1 for each sampling, and sets the value of θ (n) for n to the following equation (3) Calculate and output by The value of n is reset to 0 when, for example, a horizontal synchronizing signal is detected.
θ (n) = Δ ′ + 0/32 + nT (3)
(N = 0, 1, 2, 3 ...)

The first digital filter 4 determines a resampling position from the phase control signal θ (n) output from the phase control unit 7 and outputs resampled image data. The resampling position is represented by the number N of the image data from the horizontal synchronizing signal and the phase δ which is the internal dividing point of the adjacent image data, and the following equations (4) and (5) can be used.
N = INT (θ (n) / Ts) (4)
δ = θ (n) mod Ts (5)
Here, for arbitrary variables x and y, INT (x) is an integer part of x, and x mod y is a remainder obtained by dividing x by y. Ts is the sampling period of the A / D converter 2.
The obtained phase δ is used for controlling the first digital filter 4 as a phase shift amount.

  As described above, the first digital filter 4 obtains the number N of the image data and the phase shift amount δ according to the phase control signal θ (n) output from the phase control unit 4, and the position of the pixel used for the filter by N. Is selected, and the filter coefficient used as shown in FIG. 6 is selected according to the phase shift amount δ, so that the input image data is resampled, and the resulting resampled image data is characterized. It outputs to the quantity detection part 8 and the display part 9.

  The feature amount detection unit 8 detects the feature amount when k = 0 from the input resampled image data, and outputs it to the phase control unit 7. The phase control unit 7 holds the feature amount output by the feature amount detection unit 8 when k = 0.

Next, the phase control unit 7 obtains the phase control signal θ (n) when k = 1 by the following equation (6) similarly to the above-described operation, and outputs it to the first digital filter 4.
θ (n) = Δ ′ + 1/32 + nT (6)

  The first digital filter 4 resamples the input image data based on the phase control signal θ (n) output from the phase control unit 4, and the resampled image data is converted into the feature amount detection unit 8 and the display unit. Output to 9. The resampling position when k = 1 is out of phase by Ts / 32 with respect to the resampling position when k = 0.

  The feature amount detection unit 8 detects the feature amount of the resampled image data resampled when k = 1, and outputs it to the phase control unit 7. The phase control unit 7 holds the feature amount of the resampled image data when k = 1 output from the feature amount detection unit 8 in the same manner as when k = 0.

  The above operation is repeated up to T / Tk, and the phase control unit 7 holds the feature values for all the values of k. When the number of phase shift stages is 32 and sampling is 1.5 times, this number is 47, ie, the number of phase shift stages × 1.5, which corresponds to the period of the pixel clock of the input video signal.

  Finally, the phase control unit 7 determines k suitable for display from the retained feature amount, and outputs a phase control signal θ (n) to the first digital filter 4 based on the determined k.

  The first digital filter 4 resamples the input image data based on the phase control signal θ (n) output from the phase control unit 7 and outputs the resampled image data to the display unit 9. The display unit 9 displays the input resampled image data at a predetermined timing.

  Next, the phase adjustment operation in the first digital filter 4, the phase control unit 7, and the feature amount detection unit 8 will be further described.

  FIG. 7 is a diagram illustrating an example of the feature amount detection unit 8. The illustrated feature detection unit 8 includes an absolute difference calculator 10 and a maximum value detector 11. The absolute difference calculator 10 calculates the absolute value of the difference between the image data of two pixels adjacent in the horizontal (main scanning) direction of the image (hereinafter abbreviated as absolute difference). The maximum value detector 11 calculates the absolute difference calculator 10. The maximum value in a predetermined period (for example, a period required for sampling for one line) is detected from the absolute difference calculated in step (b).

  As an operation of phase adjustment in the image display device of the present invention, a case where an input video signal is output from a video output device capable of outputting a plurality of formats such as a personal computer (PC) will be described. The format of the video signal output from the PC is defined by, for example, VESA (Video Electronics Standard Association), and the phase control unit 7 stores in advance resampling periods T suitable for these video signal formats. Keep it.

  As described so far, in the image display device according to Embodiment 1 of the present invention, the sampling clock cycle when the input video signal is sampled by the A / D converter 2 is fixed, and the input video signal The optimum sampling period is realized by resampling of the first digital filter 4 based on the resampling period T stored in the phase control unit 7.

  Since the format of the input video signal is unknown, first, the phase control unit 7 uses the first one T1 among the plurality of (m) resampling periods T1 to Tm stored. Resampling is performed.

  As described above, the image data output from the A / D conversion unit 2 is subjected to filter processing based on the phase control signal θ (n) output from the phase controller 7 by the first digital filter 4. At this time, k used in the phase controller 5 (initially) is set to 0. The resampled image data output from the first digital filter 4 has a maximum absolute difference between adjacent pixels in the horizontal direction in the absolute difference calculator 10 and the maximum value detector 11 of the feature amount detector 8. Detected. The maximum value of the absolute difference detected by the maximum value detector 11 during a predetermined period is output to the phase control unit 7, and the phase control unit 7 sets the maximum value of the input absolute difference during the predetermined period as k = 0. Is stored as a feature value.

  Next, the phase control unit 7 outputs the phase control signal θ (n) when k = 1 to the first digital filter 4 and resampling the image data input from the A / D converter 2. . The resampled image data is input to the feature amount detection unit 8, and similarly to the case of k = 0, the maximum value during a predetermined period of the absolute difference between pixels adjacent in the horizontal direction is detected, and the phase control unit 7 Output to. The maximum value of the absolute difference input to the phase control unit 7 during a predetermined period is held as a feature value when k = 1.

  The above operation is repeated until k reaches one period of the resampling period T selected. For example, when the number of phase shift stages of the first digital filter 4 is 32 and the resampling period T is 1.5 times the sampling period of the A / D converter 2, it is repeated from k = 0 to k = 47. Become.

  The characteristic amount obtained as described above is approximately as shown in FIG. 8A or FIG. 8B. In FIGS. 8A and 8B, the vertical axis indicates the maximum value of the absolute difference, which is the feature value for each k value held by the phase control unit 7, and the horizontal axis indicates k. FIG. 8A shows a case where the resampling period T1 coincides with the dot clock period of the input video signal, and the maximum value of the absolute difference as the feature value has a maximum value or a minimum value. On the other hand, when the resampling period T1 does not coincide with the dot clock of the input video signal, the value is almost constant as shown in FIG. In this way, the validity of the resampling cycle can be determined based on the presence or absence of the maximum value or the minimum value.

  When it is determined that the resampling period T1 is not valid, the same operation is performed for the second resampling period T2.

  Until the resampling period T is determined to be appropriate, the above operation is detected for all or part of the stored resampling periods T1 to Tm.

  When the resampling period T coincides with the dot clock of the input video signal, the feature value stored in the phase control unit 7 has a maximum value or a minimum value as shown in FIG. The control unit 7 selects k corresponding to the maximum value or k corresponding to the vicinity of the center of the two minimum values as the optimum phase.

  As described above, the resampling period T and phase k are determined, and the adjustment operation is terminated.

  Thereafter, the phase control unit 7 outputs a phase control signal θ (n) based on the determined resampling period T and phase k, and the first digital filter 4 outputs the phase control output by the phase control unit 7. In accordance with the signal θ (n), the resampled image data is output to the display unit 9.

  The display unit 9 displays the input image data at a predetermined timing.

  In the above description of the operation, the case where the correct resampling period is detected using the stored resampling period when adjusting the frequency of the dot clock is shown. If a period that seems to be suitable is not found, a display indicating that automatic adjustment could not be performed may be performed, and the image signal may be changed and automatically adjusted again, or manual adjustment may be prompted.

  9 and 10 are flowcharts showing a processing procedure in the image display apparatus according to the present embodiment described above.

  First, as illustrated in FIG. 9, the phase control unit 7 includes, in the resampling period T, a first of a plurality of resampling periods (for example, m resampling periods T1 to Tm) stored in advance. Is set (St1), and then the phase k is set to 0 (St2). Then, the feature quantity is detected and stored for the resampling period T and phase k set in this way (St3).

That is, in step St21 of FIG. 10 (showing details of step St3), the video signal is sampled by the A / D converter 2 based on the clock generated by the clock generator 3. Then, the synchronization processing unit 5 determines whether or not a specific portion of the synchronization signal is sampled (St22). That is, whether or not the passage of the threshold value Ls has occurred based on the data (S _j ) obtained by sampling this time (immediately before step St21) and the data (S _j-1 ) obtained by previous sampling. Make a decision.

When it is determined that it is a specific part of the synchronization signal (Yes in St22), the process proceeds to Step St23. In step St23, the synchronization processing unit 5 calculates the first phase Δ from the data S _j−1 and S _j obtained by sampling in the A / D converter 2 by the above equation (1) (St23). Then, the parameter n is set to 0 (St24), and then the process proceeds to Step St26.

  If it is determined in step St22 that the sampled video signal is not a specific part of the synchronization signal (No in St22), 1 is added to n in step St25, and the process proceeds to step St26.

  In step St26, the phase control unit 7 calculates the phase control signal θ (n) by the above equation (2B) based on the first phase Δ, the resampling period T and the phase k output from the synchronization processing unit 5. Calculate and output to the first digital filter 4.

The first digital filter 4 resamples the image data output from the A / D converter 2 based on the phase control signal θ (n) output from the phase controller 7 (St27).
The feature amount detection unit 8 detects the absolute difference between pixels adjacent in the horizontal direction from the image data resampled by the first digital filter 4, and stores the absolute difference in association with the value of n (St28).

  Next, the feature amount detection unit 8 determines whether or not a predetermined number of samplings have been performed, that is, whether or not n has reached a predetermined number (St29), and if not (No in Step St29). Return to Step St21. If it has reached (Yes in step St29), the process proceeds to step St30, and the maximum value of the absolute difference is detected as a feature quantity based on the detected absolute difference (the value of each absolute difference for different values of n). The feature quantity detected by the feature quantity detection unit 7 is held in the phase control unit 7 (St31).

  Next, the process proceeds to step St4 in FIG. 9, and the phase control unit 7 determines whether or not the phase k has reached T / Tk. If not (No in St4), 1 is added to k ( St5), the process returns to step St3, and the feature quantity is detected and stored for the new value of k. The process of step St3 is repeated until k reaches T / Tk.

  If k reaches T / Tk (Yes in St4), it is determined whether the resampling cycle is appropriate (St6) from the retained feature amount. If not (No in St6), the last sampling cycle If it is not the last, the process proceeds to step St8, and the next one (T2) is selected from the resampling periods T1 to Tm stored in advance (St8). Returning to step St3, the feature amount detection and storage processing (St2 to St5) is repeated for all values of the phase k for the new resampling period T.

  When it is determined in step St7 that the last sampling cycle is Tm, that is, when an appropriate sampling cycle is not found from the resampling cycles stored in advance (Yes in St7), an error display or the like is performed. Then, the adjustment operation is finished (St9).

  On the other hand, if it is determined in step St6 that the resampling cycle is appropriate (Yes in St6), the resampling cycle T is determined (St10). That is, a resampling period determined to be appropriate is adopted. Then, the optimum phase k is selected from the retained feature values (St11).

  Finally, the phase control unit 7 outputs the phase control signal θ (n) according to the above equation (2B) based on the optimum resampling period T and phase k, and the first digital filter 4 Based on the phase control signal θ (n) output from the control unit 7, the image data output from the A / D converter 2 is resampled, and the resampled image data is output to the display unit 9 to perform the display operation. (St12).

  Among the above, steps St1, St2, St4, St5, St6, St7, St8, St9, St10, ST11, St12, St24, St25, St26, and St29 are performed by the phase controller 7, and steps St28 and St30 are performed. , St31 is performed by the feature detection unit 8, step St27 is performed by the first digital filter 4, the processing of step St21 is performed by the A / D conversion unit 2, and the processing of steps St22 and St23 is performed by the synchronization processing unit 5. Done in

  In the conventional image display device, since the sampling clock itself is adjusted, a period necessary for changing the sampling clock and a period until it becomes stable when the sampling clock is changed are required, and a large period is required for the adjustment. However, by configuring as described with reference to FIGS. 1 to 10 above, it is possible to display with the optimum resampling period and phase even if the sampling frequency of the A / D converter 2 is constant. Therefore, it is not necessary to adjust the period and phase of the sampling clock itself according to the image. Therefore, it is possible to adjust the sampling cycle and phase at high speed, and correct adjustment is possible even when the video changes from time to time like a moving image.

Embodiment 2. FIG.
FIG. 11 is a diagram showing a configuration of an image display device according to Embodiment 2 of the present invention.
The image display apparatus according to the second embodiment is generally the same as the image display apparatus shown in FIG. 1, but in FIG. 1, a video signal (composite video signal) in which a synchronization signal indicating video timing is superimposed on the image signal. 11 is received and displayed, whereas the configuration of FIG. 11 is different in that a video signal in which an image signal and a synchronization signal are configured as different signals is received and displayed.

  That is, an image signal is input to the input terminal 1 in FIG. 11, and the image signal input from the input terminal 1 is input to the A / D converter 2. On the other hand, the synchronization signal is input to the input terminal 14, and the synchronization signal input from the input terminal 14 is input to the A / D converter 15. The A / D converter 2 and the A / D converter 15 sample the input image signal and synchronization signal based on the sampling clock generated by the clock generator 3.

  The image data sampled by the A / D converter 2 is input to the first digital filter 4. On the other hand, the synchronization signal sampled by the A / D converter 15 is input to the synchronization processing unit 5.

  The other operations are the same as those in FIG. As described above, when the video signal is divided into the image signal and the synchronization signal, the same processing can be performed by preparing an A / D converter corresponding to each signal.

Embodiment 3 FIG.
FIG. 12 is a diagram showing the configuration of the image display apparatus according to Embodiment 3 of the present invention.
The image display device according to the third embodiment is generally the same as the image display device shown in FIG. 1, but a storage unit 16, selection units 17 and 18 are added to FIG. 1 showing the image display device in FIG. Has been. The configurations other than the storage unit 16 and the selection units 17 and 18 are the same as those in the first embodiment, and the same reference numerals are given to the same parts.

  In the image display apparatus of FIG. 12, the feature amount detection unit 8 detects the feature amount based on the resampled image data using the image data stored in the storage unit 16.

  The data output from the A / D converter 2 is input to the synchronization processing unit 6, the storage unit 16, and the selection units 17 and 18. The storage unit 16 stores part of the image data sampled by the A / D converter 2, for example, image data for a predetermined period such as one frame or one line.

  The selection unit 17 first selects the image data stored in the storage unit 16 and outputs it to the first digital filter 4 in order to adjust the resampling cycle and phase. On the other hand, the selection unit 18 selects the image data output from the A / D converter 2 and outputs it to the display unit 9 during the resampling cycle and phase adjustment operations.

  The first digital filter 4, the phase control unit 7, and the feature amount detection unit 8 use the image data stored in the storage unit 16 in the same manner as in the first embodiment, and use the optimal resampling cycle T and phase k. To decide.

  During the display operation period after the optimum resampling period T and phase k are determined, the selection unit 17 selects the image data output from the A / D converter 2 and outputs the image data to the first digital filter 4. . The first digital filter 4 resamples the input image data based on the phase control signal θ (n) output from the phase control unit 5. The selection unit 18 selects the resampled image data output from the first digital filter 4 and outputs it to the display unit 9. Other operations are the same as those in the first embodiment.

  With the configuration described above, the image data necessary for adjustment is stored in the storage unit 16, so that the adjustment is performed correctly even when the input video signal is changing at any time. be able to.

  If the difference between adjacent images is included, the adjustment operation can be performed. Therefore, a high-pass filter is provided in the storage unit 16 to detect a change in the image, for example, one frame. By storing the image at the position showing the maximum difference among the image data of the period, the amount of stored images can be minimized.

Embodiment 4 FIG.
FIG. 13 is a diagram showing a configuration of an image display apparatus according to Embodiment 4 of the present invention. The image display device according to the fourth embodiment is generally the same as the image display device shown in FIG. 1, but instead of the synchronization processing unit 5 and the clock generation unit 3 shown in FIG. Part 20 is used. The configuration other than the synchronization processing unit 19 and the clock generation unit 20 is the same as that of the first embodiment, and the same parts are denoted by the same reference numerals.

  In FIG. 13, the synchronization processing unit 19 measures the period of the synchronization signal with respect to the image display apparatus of FIG. 1, and estimates the format of the input video signal based on the measured period of the synchronization signal. It is composed.

  The video signal sampled by the A / D conversion unit 2 is input to the first digital filter 4 and the synchronization processing unit 19. The synchronization processing unit 19 measures the vertical period and horizontal period of the input synchronization signal, and estimates the format of the input video signal based on the measurement result.

  On the other hand, the clock generator 20 can generate a plurality of types of sampling clock frequencies, and the dot clock 1.5 of the video signal input based on the video signal format estimated by the synchronization processor 19. It is adjusted so that the sampling clock is about double.

  As described above, by adjusting the sampling clock based on the format of the video signal estimated by the synchronization processing unit 19, for example, the dot clock of the input video signal has various frequencies from a high frequency to a low frequency. Even if there is something, an appropriate sampling clock is set.

  In the first embodiment, in the resampling cycle setting operation, the resampling cycles stored in advance in the phase controller 7 are selected in order from the first (T1), and the feature amount is sequentially determined until it is determined as a suitable resampling cycle. However, as shown in FIG. 13, it is considered that the format is estimated from the vertical period and horizontal period of the video signal, so that it is most suitable from the resampling periods stored in advance. Since it is possible to preferentially select the object and detect the feature amount, the adjustment operation can be performed in a shorter time.

  The clock generation unit 20 shown in FIG. 13 has been described with respect to the case where a plurality of types of clock frequencies can be generated. However, only the clock of one type of frequency may be generated as in the first embodiment, and phase control may be performed. The unit 7 preferentially selects a re-sampling period stored in advance according to the format of the video signal estimated by the synchronization signal processing unit 19 and detects a feature amount. Therefore, the adjusting operation can be performed in a short time.

Embodiment 5 FIG.
FIG. 14 is a diagram showing a configuration of an image display apparatus according to Embodiment 5 of the present invention. The image display apparatus according to the fifth embodiment is generally the same as the image display apparatus shown in FIG. 1, except that a storage unit 21, a phase adjustment unit 22, a phase holding unit 23, and a second digital filter 24 are added. The display unit 9 receives the output of the second digital filter 24 and performs display.
The phase adjustment unit 22 has substantially the same function as the phase control unit 7 of the first embodiment, but the phase adjustment unit 22 and the phase holding unit 23 constitute the phase control unit 25 of the present embodiment. ing. As will be described below, the phase control unit 25 performs a first operation based on the first phase Δ obtained by the synchronization processing unit 5 and the feature amount of the first resampled image data detected by the feature amount detection unit 8. Phase control means for performing phase control of resampling of the second digital filter 24 is configured.

  The configurations other than the storage unit 21, the phase control unit 25, and the second digital filter 24 are the same as those in the first embodiment, and the same reference numerals are given to the same parts.

  A video signal including a synchronization signal and an image signal is input from the input terminal 1. The video signal input to the input terminal 1 is input to the A / D converter 2. On the other hand, the clock generator 3 generates a sampling clock for converting the video signal input to the input terminal 1 into digital image data by the A / D converter 3.

  The sampling clock generated by the clock generation unit 3 is input to the A / D changing unit 2, and the A / D converter 2 converts the input video signal based on the sampling clock into digital image data. Image data output from the A / D converter 2 is input to the storage unit 21, the second digital filter 24, and the synchronization processing unit 5.

  The synchronization processing unit 5 calculates the separation of the synchronization signal and the first phase Δ as in the first embodiment, and outputs the first phase Δ to the horizontal AFC 6. The horizontal AFC 6 also outputs a stable first phase Δ ′ to the phase controller 7 as in the first embodiment.

  On the other hand, the image data input to the storage unit 21 stores a part of the image data sampled by the A / D converter 2, for example, data for a predetermined period such as one frame or one line. Since the stored image data needs to include a portion having a large difference between adjacent pixels necessary for detection of the image feature amount described later, a high-pass filter is provided in the storage unit 21 to It is also possible to minimize the amount of stored image by detecting the change and storing the image at the position showing the maximum difference among the image data for a period of one frame, for example.

  The image data stored in the storage unit 21 is input to the first digital filter 4. Thereafter, using the image data stored in the storage unit 21, the feature amount detection unit 8 and the phase adjustment unit 22 sequentially detect and hold the feature amount of the image, and obtain the optimum resampling period T and phase k. Since this operation is the same as that of the first embodiment, detailed description thereof is omitted.

  The phase adjustment unit 22 outputs the determined resampling period T and phase k to the phase holding unit 23. The phase holding unit 23 calculates the phase control signal θ ′ (n) in the same manner as the phase adjusting unit 22 by using the resampling period T and the phase k output from the phase adjusting unit 22, and sends them to the second digital filter 24. Output.

  The second digital filter 24 resamples the image data output from the A / D conversion unit 2 in accordance with the phase control signal θ ′ (n) output from the phase holding unit 23 and outputs it to the display unit 9.

  The display unit 9 displays the image data resampled by the second digital filter 24 at a predetermined timing.

  As described above, the resampling period T and phase k are determined from the detected feature values. Of these, the resampling period T is determined by the format of the image, but the optimum value of the phase k varies depending on the temperature characteristics of the image generating apparatus and the temperature characteristics of the A / D converter 2 and the like. Therefore, the optimal phase may change as time passes. When the phase k is readjusted in this way, the phase holding unit 23 performs the readjustment by outputting the phase control signal θ ′ (n) based on the resampling period T and the phase k determined at the previous adjustment. Images can continue to be displayed during operation. The image displayed here needs to be readjusted in phase, but does not cause a large disturbance. When k is sequentially changed from 0 as in the case of detecting a feature value for readjustment. In comparison, a sufficiently practical image is displayed, and the user does not need to be aware that re-adjustment is in progress.

  In readjustment of the phase, the storage unit 21 newly stores image data for a predetermined period, detects the feature amount by sequentially changing the phase k, and obtains the optimum phase k. The new phase k obtained by the phase adjustment unit 22 is output to the phase holding unit 23, and the phase holding unit 23 generates the phase control signal θ ′ (n) based on the new phase k, and the second digital Output to the filter 24. Subsequent display operations are as described above.

  In the case of phase readjustment, it is needless to say that an adjustment operation related to the resampling cycle T is unnecessary because the resampling cycle T need not be changed.

  With the configuration described above, it is possible to display an image without any disturbance even during adjustment.

It is a block diagram which shows the image display apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows the relationship between a 1st phase and a synchronizing signal. It is a figure which shows the relationship between the 1st phase and sampling position in each display line. It is a figure which shows the amplitude characteristic of a digital filter. It is a figure which shows the delay characteristic of a digital filter. 6 is a table showing an example of filter coefficients for showing the characteristics of FIGS. 4 and 5. It is a figure which shows an example of the feature-value detection part. (A) And (b) is a figure which shows the relationship between a feature-value and transfer. It is a flowchart explaining the process sequence in the image display apparatus which concerns on Embodiment 1 of this invention. It is a flowchart explaining the process sequence in the image display apparatus which concerns on Embodiment 1 of this invention. It is a block diagram which shows the image display apparatus which concerns on Embodiment 2 of this invention. It is a block diagram which shows the image display apparatus which concerns on Embodiment 3 of this invention. It is a block diagram which shows the image display apparatus which concerns on Embodiment 4 of this invention. It is a block diagram which shows the image display apparatus which concerns on Embodiment 5 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Input terminal, 2 A / D converter, 3 Clock generation part, 4 First digital filter, 5 Synchronization processing part, 6 Horizontal AFC, 7 Phase control part, 8 Feature-value detection part, 9 Display part, 10 Maximum difference Computing unit, 11 maximum value detector, 14 input terminal, 15 A / D converter, 16 storage unit, 17, 18 selection unit, 19 synchronization processing unit, 20 clock generation unit, 21 storage unit, 22 phase adjustment unit, 23 A phase holding unit, 24 a second digital filter, and 25 a phase control unit;

Claims (16)

A method of controlling an image display device that samples an analog video signal including an image signal and a synchronization signal to generate digital image data, and displays an image using the generated image data,
Sampling the synchronization signal and the image signal based on a sampling clock that is not necessarily synchronized with the video signal;
Obtaining a first phase corresponding to a time difference of the sampling clock with respect to the video signal from the sampled synchronization signal;
Receiving the image data sampled in the sampling step, and generating resampled image data equivalent to the image data obtained when sampling is performed at a different phase in the sampling step;
Extracting a feature amount from the generated resampled image data;
Determining an optimal resampling period and phase shift amount for displaying an image based on a feature amount of the resampling image data;
And a step of performing phase control for resampling based on the first phase, the resampling period and the phase shift amount. A method of controlling an image display device that samples an analog video signal including an image signal and a synchronization signal to generate digital image data, and displays an image using the generated image data,
Sampling the synchronization signal and the image signal based on a sampling clock that is not necessarily synchronized with the video signal;
Obtaining a first phase corresponding to a time difference of the sampling clock with respect to the video signal from the sampled synchronization signal;
Receiving the image data sampled in the sampling step, and generating first resampled image data equivalent to the image data obtained when sampling is performed at a different phase in the sampling step;
Extracting a feature amount from the first resampled image data;
Determining a resampling period and a phase shift amount of the second resampled image data based on the feature amount of the first resampled image data;
Control method for an image display device characterized by having a step of performing phase control for the second resampling on the basis the first phase, the period and the phase shift amount of the resampling. Storing and reading a portion of the sampled image data;
The method of controlling an image display device according to claim 2, wherein the first resampling is performed in response to the stored image data.   In the step of obtaining the first phase, the first phase is determined based on the sample values of the sampling points immediately before and immediately after the point at which the value of the sampled synchronization signal passes a predetermined threshold value, and the threshold value. The method for controlling an image display device according to claim 1, wherein the method is obtained. In the step of determining the first phase,
Δ = (Ls−S _j ) / (S _j−1 −S _j ) (1)
(Where Δ is the first phase, Ls is the predetermined threshold value, S _j−1 , S _j are sample values of sampling points immediately before and immediately after the point at which the value of the synchronization signal passes the threshold value. Is)
The method for controlling the image display device according to claim 4, wherein the first phase is obtained based on the first phase.   Change the resampling period, investigate the relationship between the resampling period change and the feature quantity change, and use the resampling period at which the periodicity is detected in the feature quantity change as the optimal resampling period The method for controlling an image display device according to claim 1, wherein the control method is adopted.   The method for controlling an image display device according to claim 6, wherein an optimum resampling phase is obtained from a relationship between a feature quantity and a resampling phase in the optimum resampling period. An image display device that samples an analog video signal including an image signal and a synchronization signal to generate digital image data, and displays an image using the generated image data,
A clock generator for generating a sampling clock that is not necessarily synchronized with the video signal;
An A / D converter that samples an image signal and a synchronization signal included in the video signal based on a sampling clock generated by the clock generator;
A synchronization processing unit for obtaining a first phase corresponding to a time difference of the sampling clock with respect to the video signal from the synchronization signal sampled by the A / D conversion unit;
A first digital filter that receives image data sampled by the A / D converter and generates resampling image data equivalent to image data obtained when the A / D converter is sampled at a different phase. When,
A feature amount detection unit that extracts a feature amount from the generated first resampled image data;
A phase control unit that controls the phase of resampling of the first digital filter based on the first phase obtained by the synchronization processing unit and the feature amount detected by the feature amount detection unit;
An image display device comprising: a display unit that displays resampling image data output from the first digital filter.   9. The image display apparatus according to claim 8, wherein the digital filter has a flat frequency characteristic and a flat group delay characteristic up to a frequency approximately 1.5 times the signal band of the video signal. A storage unit for storing a part of the sampled image data;
The digital filter selects one of the sampled image data and the image data stored in the storage unit to generate resampling image data,
The image according to claim 8, wherein the feature amount detection unit detects a feature amount using resampling image data generated by the digital filter selecting image data stored in the storage unit. Display device. An image display device that samples an analog video signal including an image signal and a synchronization signal to generate digital image data, and displays an image using the generated image data,
A clock generator for generating a sampling clock that is not necessarily synchronized with the video signal;
An A / D converter that samples an image signal and a synchronization signal included in the video signal based on a sampling clock generated by the clock generator;
A synchronization processing unit for obtaining a first phase corresponding to a time difference of the sampling clock with respect to the video signal from the synchronization signal sampled by the A / D conversion unit;
A storage unit for storing a part of the image data sampled by the A / D conversion unit;
A first digital filter that receives the image data stored in the storage unit and generates first resampled image data equivalent to the image data obtained when the A / D converter is sampled at a different phase. When,
A second unit that receives the image data sampled by the A / D converter and generates second resampled image data equivalent to the image data obtained when the A / D converter is sampled at a different phase. With a digital filter,
A feature amount detection unit that extracts a feature amount from the first resampling image data generated by the first digital filter;
Phase control for performing resampling phase control of the second digital filter based on the first phase obtained by the synchronization processing unit and the feature amount of the first resampling image data detected by the feature amount detection unit And
An image display device comprising: a display unit configured to display second resampling image data output from the second digital filter. The phase control unit is
Based on the first phase obtained by the synchronization processing unit and the feature quantity detected by the feature quantity detection unit, a signal for designating a resampling phase of the first digital filter is generated. A phase adjustment unit for controlling the digital filter of
A phase holding unit that controls a phase of resampling of the second digital filter by holding a signal generated by the phase adjustment unit and supplying the signal to the second digital filter. The image display device according to claim 11.   The synchronization processing unit obtains the first phase based on a sample value immediately before and immediately after a point at which the value of the sampled synchronization signal passes a predetermined threshold and a threshold. The image display device according to claim 8 or 11. The synchronization processing unit
Δ = (Ls−S _j ) / (S _j−1 −S _j ) (1)
(Where Δ is the first phase, Ls is the predetermined threshold value, S _j−1 , S _j are sample values of sampling points immediately before and immediately after the point at which the value of the synchronization signal passes the threshold value. Is)
The image display device according to claim 13, wherein the first phase is obtained based on the first phase.   The synchronization processing unit changes the resampling cycle, investigates the relationship between the resampling cycle change and the feature amount change, and optimizes the resampling cycle at which periodicity is detected in the feature amount change. The image display device according to claim 8, wherein the image display device is used as a cycle of accurate resampling.   16. The image display device according to claim 15, wherein an optimum resampling phase is obtained from a relationship between a feature amount and a resampling phase in the optimum resampling cycle.

Images