KR100598194B1 - Method for automatically adjusting sampling clock - Google Patents

Abstract

Disclosed is a sampling clock automatic adjustment method capable of providing an optimal sampling clock and phase in an image display apparatus.

When the digital video signal converted by the basic sampling clock and phase is not good, the sampling clock automatic adjustment method of the present invention sets the clock and phase ranges based on the basic sampling clock, and sets the analog image according to the set clock and phase, respectively. Converts the signal into a digital image signal, calculates a difference of values of adjacent pixels in the converted digital image signal sequentially, sums the difference values calculated in one frame, and optimizes sampling using the calculated sums Determine the clock and phase.

Therefore, by converting an analog video signal into a digital video signal according to the optimal sampling clock and phase determined as described above, an image having improved image quality can be obtained.

Video display device, sampling clock, phase, sum

Description

{Method for automatically adjusting sampling clock}             

1 is a flow chart illustrating a method for automatically adjusting a sampling clock in accordance with one preferred embodiment of the present invention.

2 is an exemplary diagram illustrating a pixel area included in one frame.

3 is an exemplary diagram illustrating patterns of various input analog video signals.

4 is a graph showing the sums calculated for each sampling clock and for each phase.

The present invention relates to an image display apparatus, and more particularly, to a method for automatically adjusting a sampling clock capable of providing an optimal sampling clock and phase.

A video display device including a PC monitor, a television receiver, or the like converts an input analog video signal into a digital video signal, and then converts and displays the format according to the characteristics of each video display device.

To do this, the sampling clock and phase used to convert analog video signals to digital video signals must be accurately adjusted.

However, to date, the sampling clock and phase are not automatically adjusted, but are only manually adjusted based on a user interface concept using an on screen display (OSD) of the monitor.

In this way, the sampling clock and phase need to be adjusted not only because the number of pixels of the video signal included in the horizontal synchronizing signal is inputted analog, but also the number of pixels cannot be counted. This is because the signal generators are slightly different.

Therefore, if it is not adjusted to the correct sampling clock and phase, as accurate data is not sampled from the analog video signal, there is a high possibility that erroneous data is displayed on the screen or certain data is missed and not displayed.

Accordingly, an object of the present invention is to provide a sampling clock automatic adjustment method capable of selecting an optimal sampling clock and phase for accurately converting an input analog video signal into a digital video signal. There is this.

According to a preferred embodiment of the present invention for achieving the above object, the sampling clock automatic adjustment method, if the digital video signal converted by the base sampling clock and phase is not good, the clock and the reference based on the base sampling clock Setting a phase range; Converting an analog video signal into a digital video signal by the set clock and phase; Calculating totals for each clock and phase by accumulating difference values between sequential adjacent pixel values in the digital image signal; And comparing the calculated sums with a set threshold to determine an optimal sampling clock and phase.

By converting the analog video signal into a digital video signal using the optimal sampling clock and phase determined as described above, an image having improved image quality can be obtained.

Hereinafter, a sampling clock automatic adjustment method of the present invention will be described with reference to the accompanying drawings.

1 is a flowchart illustrating a method of automatically adjusting a sampling clock according to an exemplary embodiment of the present invention.

Referring to FIG. 1, first, R, G, and B analog video signals are input (step 11).

Horizontal / vertical sync signals included in the input analog video signal are separated (step 12).

Typically, when the analog video signal is provided from the outside, a horizontal / vertical sync signal representing the resolution of the analog video signal is provided together. Therefore, the resolution of the analog video signal can be determined through the horizontal / vertical synchronization signal.

Typically, even when an analog image signal having various resolutions is input into the system, a scaling function for converting the image into a resolution corresponding to the various resolutions is provided in the system. Therefore, when an analog image signal corresponding to a resolution supported by the scaling function of the system is input, the image signal is displayed on the screen by converting the image to a resolution supported by the scaling function. Also, when an analog video signal corresponding to a resolution not supported by the scaling function is input, the analog video signal may be converted into a resolution most similar to the analog video signal among the resolutions supported by the scaling function.

The base sampling clock and the phase are set based on the horizontal / vertical sync signals separated by step 12 (step 13). That is, a predetermined resolution may be inferred by the horizontal / vertical synchronization signal, and a basic sampling clock and phase for converting the analog video signal into a digital video signal may be set according to the inferred resolution.

The analog video signal is converted into a digital video signal according to the set basic sampling clock and phase (step 14). The converted digital video signal may be temporarily stored. Temporarily storing the converted digital video signal may include an optimal sampling clock using respective pixel values in the converted video signal when the converted video signal is not correctly converted by the basic sampling clock and phase. This is to use the converted video signal to select a phase.

At this time, it is determined whether the sampling is good (step 15). That is, it may be determined whether the displayed digital video signal is clearly displayed without deterioration of image quality. If the basic sampling clock and phase are correct, the digital video signal can be displayed on the screen without missing data and without deterioration of image quality. However, if the basic sampling clock and phase are not accurate, when the analog video signal is converted into a digital video signal, sampling may not be performed correctly, and some data may be missing or incorrect data may be sampled, resulting in image quality on the screen. This degraded image is displayed. Such good sampling can be determined by the user or the system itself.

If the sampling is judged to be good, the converted digital video signal is converted and displayed to be suitable for the screen resolution (step 21).

However, if it is determined that sampling is not good, the sampling clock and phase range are set based on the set basic sampling clock (step 16).

For example, if the basic sampling clock is 1650 and the range is ± 3, the sampling clocks included in the range may be 1647, 1648, 1649, 1650, 1651, 1652, and 1653. At this time, the phase range is preferably classified into 12 phases for each clock. In other words, the phase range may be 0 °, 30 °, 60 °, 90 °, 120 °, 150 °, 180 °, 210 °, 240 °, 270 °, 300 °, 330 °.

In this way, when the sampling clock and the phase range are set, the total is calculated for one frame of the digital video signal (step 17).

In general, as shown in FIG. 2, N × K pixel values exist within one frame of the digital video signal. At this time, each pixel value is displayed in a pixel corresponding to the screen.

As described above, when N × K pixel values are sequentially present in a frame, a total is calculated using the difference values between the sequential adjacent pixel values, and the sum may be expressed as in Equation 1 below. have.

∑∑│P (n: k) -P (n + 1: k) │

Here, P (n: k) represents the (n, k) th pixel value, and P (n + 1: k) represents the (n + 1, k) th pixel value.

Accordingly, first, the analog video signal is converted into a digital video signal according to a basic sampling clock (for example, 1650) and a phase (for example, 0 °), and sequential adjacent pixel values existing within one frame of the converted digital image signal The difference between the two values is calculated, and the sum is calculated by accumulating the calculated difference values.

Next, the analog video signal is converted into a digital video signal according to the basic sampling clock (e.g., 1650) and the next phase (e.g., 30 °), and a sequential contiguous present within one frame of the converted digital image signal. The difference value between the pixel values is calculated, and the sum is calculated by accumulating the difference values.

As described above, the phases included in the phase range set for the basic sampling clock (for example, 1650) are changed one by one, and the analog image signal is converted into a digital image signal to sum the total value according to the difference between the pixels of each phase. Calculate.

When this process is completed, the phases included in the phase range set for the set sampling clock (eg, 1647) are changed one by one, and the analog image signal is converted into a digital image signal so that the difference value between adjacent pixels for each phase is changed. Calculate the total.

The above process is repeatedly performed for each of the set sampling clocks and phases to calculate totals according to difference values between adjacent pixel values. In this case, the sums calculated for each sampling clock and each phase may be stored.

Meanwhile, the calculated sums largely depend on the pattern of the input analog video signal.

3 is an exemplary diagram illustrating patterns of various input analog video signals. As shown in FIG. 3, the input image signal is represented in various patterns by the difference of each pixel value. For example, (a) shows the difference value between the pixel values of the analog video signal in a large pattern, while (d) shows the difference value between the pixel values of the analog video signal in a constant pattern. (b) and (c) show irregular values between the pixel values of the analog video signal. Therefore, when the sum is calculated for the analog video signal as shown in (a), the sum for each set sampling clock and for each phase is generally large. On the other hand, when the sum is calculated for the analog video signal as shown in (d), the sum for each set sampling clock and phase is generally small. When the sum is calculated for the analog video signals such as (b) and (c), the sum may be large or small for each set sampling clock and phase.

When sums are calculated for each sampling clock and phase as described above, it is determined whether the calculated sums are larger than a threshold value (step 18). Here, the threshold is a value derived to determine an optimal sampling clock and phase, and this threshold may be set through an iterative experiment.

As a result of the determination in step 18, when the sums calculated for each sampling clock and phase are larger than the threshold value, the sampling clock and phase corresponding to the maximum sum are determined as the optimal sampling clock and phase, and the sampling corresponding to the maximum sum is determined. The clock and phase are selected (step 19). Here, the maximum sum means the sum with the largest value among the sums calculated for each sampling clock and phase. For example, as illustrated in FIG. 4, sampling clocks set on the horizontal axis are 1647, 1648, 1649, 1650, and 1651, and phases are 0 °, 30 °, 60 °, 90 °, 120 °, and 150 for each sampling clock. When set to °, 180 °, 210 °, 240 °, 270 °, 300 °, and 330 °, sums are calculated and plotted on the vertical axis. At this time, there is a maximum sum X having the largest value among the calculated sums, where the sampling clock and phase corresponding to the maximum sum are approximately 1649 and 90 °. Therefore, the sampling clock 1649 and the phase 90 ° at this time can be selected as the optimal sampling clock and phase.

On the other hand, if the sums calculated for each sampling clock and phase are smaller than the threshold, the sampling clock and phase corresponding to the minimum sum are determined as the optimal sampling clock and phase, and the sampling clock and phase corresponding to the minimum sum are selected. (Step 20). Here, the minimum sum means the sum with the smallest value among the sums calculated for each sampling clock and phase.

If the optimal sampling clock and phase are selected by the step 19 or 20, the process moves to the step 14 to convert the input analog video signal into a digital signal according to the selected sampling clock and phase. In addition, the digital video signal converted in step 14 is displayed after the format conversion.

Therefore, when the digital video signal converted according to the base sampling clock and phase determined by the horizontal / vertical synchronization signal is not good, the present invention sets a predetermined range of sampling clocks and phases with the base sampling clock as the mood. After converting the analog video signal to the digital video signal according to the set sampling clock and phase, the sums are calculated according to the difference values between the sequential adjacent pixel values of the converted digital video signals, and then the calculated sums are calculated. To determine the optimal sampling clock and phase. The analog video signal is converted into a digital video signal according to the determined sampling clock and phase and then displayed through format conversion.

As described above, according to the sampling clock automatic adjustment method of the present invention, when converting an analog video signal into a digital video signal for each sampling clock and phase of a predetermined range based on a basic sampling clock, respectively, the converted digital video The sums calculated from the signals can be used to simply determine the optimal sampling clock and phase.

In addition, according to the method for automatically adjusting the sampling clock of the present invention, by determining the optimal sampling clock and phase thus simply determined, converting the analog image signal into a digital image signal according to the optimal sampling clock and phase, and displaying the image quality, An improved image can be displayed.

Claims (10)

Setting a clock and phase range based on the base sampling clock when the digital video signal converted by the base sampling clock and phase set from the input horizontal / vertical synchronization signal is not good; Converting an analog video signal into a digital video signal by the set clock and phase; Calculating totals for each clock and phase by accumulating difference values between sequential adjacent pixel values in the digital image signal; And Comparing the calculated sums with a set threshold to determine an optimal sampling clock and phase Sampling clock automatic adjustment method comprising a. delete The sampling clock automatic adjustment of claim 1, wherein when the calculated totals are greater than the set threshold, a clock and a phase corresponding to the largest sum among the calculated totals are determined as an optimal sampling clock and phase. Way. The sampling clock automatic adjustment of claim 1, wherein when the calculated sums are smaller than the set threshold, a clock and a phase corresponding to the smallest sum among the calculated sums are determined as an optimal sampling clock and phase. Way. The method of claim 1, wherein the converted digital video signal is temporarily stored. Sampling clock automatic adjustment method further comprising. The method of claim 1, further comprising: storing the sums calculated for each clock and each phase. Sampling clock automatic adjustment method further comprising. The method of claim 1, further comprising: displaying a digital video signal converted by the determined optimal sampling clock and phase. Sampling clock automatic adjustment method further comprising. The method of claim 1, wherein the sum is a value calculated for one frame in the digital video signal. The method of claim 1, wherein the calculated total becomes larger as a difference between adjacent pixel values in the digital image signal increases. The method of claim 1, wherein the calculated sum is smaller as a difference between adjacent pixel values in the digital image signal is smaller.

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