TWI395465B - Method and system of automatically correcting a sampling clock in a digital video system - Google Patents

Description

Method and system for automatically correcting sampling clock in digital video system

The present invention relates to analog to digital conversion (ADC), and more particularly to a digital to analog conversion suitable for digital video systems for automatically correcting the phase or frequency of the sampling clock.

When a digital video system (such as a digital display or a graphics digitizer) receives and processes an analog video signal, the analog video signal must first be converted to digital form to facilitate processing of the signal in the digital domain. The block diagram of the first figure shows an analog video source 10 (such as a computer graphics card) and a digital video system 12 (such as a liquid crystal display). The analog video source 10 transmits an analog video signal (e.g., analog RGB (Red Green Blue) or YPbPr color difference signal) to the digital video system 12 via cable 14A. The received analog video signal is converted to a digital video signal by an analog to digital converter (ADC) 120. While transmitting the analog video signal, cable 14B also transmits synchronization signals (e.g., horizontal sync signal H _syn and vertical sync signal V _syn ). The received sync signal is processed by clock generator 122, thereby generating a sample clock (or pixel clock) for triggering analog to digital converter (ADC) 120 for conversion.

Due to the difference in impedance and length between cable 14A and cable 14B, analog video signals and sync marks may arrive at digital video system 12 at slightly different times. In other words, the phase or even the frequency of the sampling clock of the analog analog to digital converter (ADC) 120 may not be synchronized with the phase/frequency of the pixel clock of the analog video source 10 used to generate the analog video signal. This results in a degradation in the quality of the output (e.g., display image) of the digital video system 12.

In order to improve the shortcomings of traditional digital video systems, some improvements have been proposed. For example, U.S. Patent No. 5,767,916 ("Method and Apparatus for Automatic Pixel Clock Phase and Frequency Correction in Analog to Digital Video Signal Conversion") proposes a technique for comparing the actual width of a video image with an expected image width, Used to adjust the pixel clock frequency. However, when the video image has a relatively large blank area, this technique cannot accurately and efficiently generate the pixel clock frequency.

U.S. Patent No. 6,268,848 ("Method and Apparatus Implemented in an Automatic Sampling Phase Control System for Digital Monitors") proposes a technique for controlling sampling by collecting digital samples of horizontal lines and finding their peaks and valleys. Phase.

US Patent Application No. 2006/0274207 (titled "Method and Apparatus for Analog Graphics Sample Clock Frequency Verification") proposes a technique for automatically selecting a sample by measuring the difference between successive image frames. frequency. However, this technique must store the image data of the entire frame in order to measure the difference.

The above conventional techniques cannot effectively or simply solve the phase/frequency problem of the sampling clock, so there is a need to propose a novel mechanism for correcting the phase/frequency of the sampling clock in an efficient manner and with minimal resources or time.

In view of the foregoing, it is an object of embodiments of the present invention to provide a method and system for efficiently and simply correcting the phase or/and frequency of a sampling clock for performing analog to digital conversion (ADC).

According to one of the embodiments of the present invention, a complex sampling clock having a desired frequency and different phases is generated and sequentially transmitted to an analog to digital converter (ADC). For each phase, the sum of the absolute differences (SAD) of the adjacent data output from the analog to digital converter (ADC) is determined. A maximum difference is determined and a sampling clock corresponding to the phase of the maximum difference is generated.

According to another embodiment of the present invention, a complex sampling clock having a plurality of candidate frequencies and having different phases is generated and sequentially transmitted to an analog to digital converter (ADC). For each phase and each candidate frequency, the sum of the absolute differences (SAD) of the adjacent data output from the analog to digital converter (ADC) is determined. A maximum difference is determined and a sampling clock corresponding to the phase and frequency of the largest difference is generated.

The second figure shows a block diagram of a system 2 of an embodiment of the invention that is suitable for use with a digital video system to automatically correct the sampling clock (or pixel clock). The third figure shows a flow chart of a method according to a first embodiment of the invention, which is suitable for use in a digital video system to automatically correct the sampling clock. Although the present embodiment is exemplified by a digital display (for example, a liquid crystal display), the present invention is also applicable to other digital video systems, such as a graphics digitizer.

Referring to the second figure, an analog to digital converter (ADC) 20 receives an analog video signal from an analog video source (e.g., 10 of the first figure, such as a computer graphics card). Next, an analog to digital converter (ADC) 20 converts analog video signals (eg, analog RGB (red green blue) or YPbPr color difference signals) into digital video signals.

On the other hand, the clock generator 22 also receives synchronization signals from the analog video source, such as the horizontal sync signal H _syn and the vertical sync signal V _syn . The clock generator 22 generates a sampling clock (or pixel clock) for triggering an analog to digital converter (ADC) 20 to convert based on the received synchronization signal and the system clock of the system 2. The fourth A diagram shows a detailed block diagram of the clock generator 22 of the embodiment of the present invention. First, the scan line interval is measured by the interval measuring unit 220, which is counted by the number of system clocks per line (step 31, third figure). The fourth B diagram illustrates a scan line interval H _total which starts from the rising edge of the horizontal synchronizing signal H _syn and finally the rising edge of the next horizontal synchronizing signal H _syn . Next, in step 32, the measured scan line interval is mapped to the corresponding expected sampling clock by the look-up table (LUT) 222, which has a frequency f0. In the present embodiment, the contents of the lookup table (LUT) 222 include a plurality of pieces of data, each of which includes a scan line interval and a corresponding sampling clock having an individual frequency. These materials can be obtained experimentally. In another embodiment, the sampling clock is simultaneously mapped according to the horizontal synchronizing signal H _syn and the vertical synchronizing signal V _syn . It should be noted that the interval measurement unit 220 and the look up table (LUT) 222 are not necessarily implemented in the clock generator 22.

In the next step 33, the clock generator 22 generates a plurality of sampling clocks having frequencies f0 but different phases, and sequentially transmits them to an analog to digital converter (ADC) 20. The clock generator 22 generates phase clocks of different phases (e.g., p1, p2, ... pm) based on the phase information provided by the phase controller 24. The phase controller 24 is in turn controlled by the phase control signal PCS of the controller 26. The fifth diagram illustrates a timing diagram of an analog video signal and a sampling clock having different phases p1-pm, where An represents an analog video signal level input to an analog to digital converter (ADC) 20, and Dn represents an analogy to The sampled data (or digital video signal) output by the digital converter (ADC) 20. This pattern shows that this video signal cannot be correctly sampled by phase p1.

Next, for each phase, the difference unit 28 determines the difference between at least one set of adjacent data output by the analog to digital converter (ADC) 20 (step 34). In one embodiment, for each phase pn (n = 1 to m), the sum of absolute differences of the adjacent data of the (partial or complete) scan line (or field or frame) is calculated (sum of absolute differences, SAD) Sn (n = 1 to m) as shown in Figure 6A. The SAD value S can be expressed by:

Where D _i represents the i-th data of the scan line (or field or frame).

Figure 6B shows a detailed block diagram of the difference unit 28 (or SAD unit) for calculating the SAD values of adjacent R, G, B (red, green, blue) data. The current data (eg, R (red)) and the previous data stored in the register 280 are transferred to the absolute difference unit 282 for calculating the absolute difference. The absolute difference is accumulated for the entire scan line via the accumulator 284, thus obtaining the sum of absolute differences (SAD). Different video components (e.g., R, G, B in this example) are summed via adder 286, thus producing a final SAD value corresponding to phase pn. Although the present embodiment is exemplified by video data R, G, B, the present invention is also applicable to other color spaces (for example, YUV).

The calculated SAD value Sn is sequentially transmitted to the controller 26. When all of the phase (p1-pm) data has been processed (step 35), the controller 26 determines the maximum SAD value (step 36). The controller 26 then issues a phase control signal PCS for controlling the phase controller 24, which controls the phase offset based on the phase control signal PCS. The phase controller 24 then sends the phase information to the clock generator 22 such that the phase of the sampling clock generated by the clock generator 22 corresponds to the maximum SAD value (step 37). Since the correctness of the phase is proportional to the SAD value, the sampling clock obtained in step 37 can correctly sample the analog video signal. Furthermore, since the SAD is an extremely fast and simple metric, the sampling clock can be corrected efficiently and easily.

Although the present embodiment takes SAD as an example, other difference metrics such as sum of squared differences (SSD) may be used. Furthermore, it is not necessary to calculate the SAD values of all phases. For example, in another embodiment, the SAD value can be calculated for a certain phase (eg, intermediate phase p3). If the calculated SAD value is greater than a predetermined reference value, the phase correction of the sampling clock is mapped to the current SAD value; otherwise, the SAD value is continuously calculated for the other phase. This procedure can be performed in a binary search manner until the obtained SAD value is greater than the preset reference value.

Figure 7 is a flow chart showing the method of the second embodiment of the present invention, which is suitable for use in a digital video system to automatically correct the sampling clock. This embodiment (seventh figure) is similar to the previous embodiment (third figure), and the differences between them will be explained as follows. In the present (second) embodiment, after measuring the scan line interval (step 31), the mapping generates a plurality of candidate frequencies fr (r=0 to s-1) (for example, six candidate frequencies f0 to f5) ( Step 32B).

The clock generator 22 first generates a plurality of sampling clocks having frequencies f0 but different phases, and sequentially transmits them to an analog to digital converter (ADC) 20. Next, the clock generator 22 sequentially generates a plurality of sampling clocks having frequencies f1 but different phases. This procedure continues until all candidate frequencies are generated sequentially (step 38), as shown in the eighth figure.

After determining the maximum SAD value (step 36), controller 26 then issues a phase control signal PCS for controlling phase controller 24, which in turn sends phase information to clock generator 22. The controller 26 also issues a frequency control signal FCS for controlling the clock generator 22. Thereby, the phase and frequency of the sampling clock generated by the clock generator 22 are made to correspond to the maximum SAD value (step 37B). Therefore, the sampling clock acquired in step 37B can correctly sample the analog video signal.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

10. . . Analog video source

12. . . Digital video system

120. . . Analog to digital converter (ADC)

122. . . Clock generator

14A, 14B. . . cable

2. . . System for automatically correcting the sampling clock

20. . . Analog to digital converter (ADC)

twenty two. . . Clock generator

220. . . Interval measurement unit

222. . . Lookup table (LUT)

twenty four. . . Phase controller

26. . . Controller

28. . . Difference unit (SAD unit)

280. . . Register

282. . . Absolute difference unit

284. . . Accumulator

286. . . Adder

31-37B. . . step

The block diagram of the first figure shows an analog video source and a digital video system.

The second figure shows a system block diagram of an embodiment of the invention that is suitable for use with a digital video system to automatically correct the sampling clock.

The third figure shows a flow chart of a method according to a first embodiment of the invention, which is suitable for use in a digital video system to automatically correct the sampling clock.

Figure 4A shows a detailed block diagram of the clock generator of an embodiment of the present invention.

The fourth B diagram illustrates a scan line interval.

The fifth diagram illustrates the timing diagram of the analog video signal and the sampling clock with different phases.

Figure 6A shows the calculation of its SAD value for each phase.

Figure 6B shows a detailed block diagram of the SAD unit.

Figure 7 is a flow chart showing the method of the second embodiment of the present invention, which is suitable for use in a digital video system to automatically correct the sampling clock.

The eighth graph shows the SAD value calculated for each phase and frequency.

2. . . System for automatically correcting the sampling clock

20. . . Analog to digital converter (ADC)

twenty two. . . Clock generator

220. . . Interval measurement unit

222. . . Lookup table (LUT)

twenty four. . . Phase controller

26. . . Controller

28. . . Difference unit (SAD unit)

Claims (20)

A method for automatically correcting a sampling clock in a digital video system, comprising: generating the sampling clock to trigger an analog to digital conversion (ADC); generating a complex sampling clock having different phases; for each phase, determining Comparing the analog to the difference between at least one set of adjacent data output by the digital conversion (ADC); determining a maximum difference; and generating the sampling clock corresponding to the phase of the maximum difference; wherein the generating the sampling clock The step includes: measuring a scan line interval according to a synchronization signal and a system clock; and acquiring at least one frequency of the sampling clock according to the measured scan line interval. The method for automatically correcting a sampling clock in a digital video system as described in claim 1, wherein the digital video system is a digital display. A method for automatically correcting a sampling clock in a digital video system as described in claim 1, wherein the synchronization signal is a horizontal synchronization signal. The method for automatically correcting the sampling clock in the digital video system as described in claim 1 of the patent application, obtains an expected frequency of the sampling clock. A method for automatically correcting a sampling clock in a digital video system as described in claim 4, for each phase, calculating a sum of absolute differences (SAD) of the adjacent data of at least a portion of the scanning lines. The method for automatically correcting the sampling clock in the digital video system as described in claim 1 of the patent application section acquires the complex candidate frequency of the sampling clock. The method of automatically correcting the sampling clock in the digital video system as described in claim 6 of the patent application, and determining the difference for each of the candidate frequencies. The method of automatically correcting the sampling clock in the digital video system as described in claim 7 of the patent application further generates the sampling clock corresponding to the frequency of the maximum difference. For automatically correcting the sampling clock in the digital video system as described in claim 6, the sum of the absolute differences of the adjacent data of at least part of the scanning lines (SAD) is calculated for each of the phases and the candidate frequencies. . A system for automatically correcting a sampling clock in a digital video system, comprising: A type of analog to digital converter (ADC) for converting a analog video signal to a digital video signal; a clock generator for generating the sampling clock according to a synchronization signal and a system signal, the generation of which is different The complex phase samples the clock and transmits to the analog to digital converter (ADC); a difference unit, for each phase, determines at least one set of adjacent data output by the analog to digital converter (ADC) And a controller for determining a maximum difference and controlling the clock generator to generate the sampling clock corresponding to the phase of the maximum difference, wherein the clock generator comprises: an interval The measuring unit is configured to measure the scan line interval according to the synchronization signal and the system clock; and a look-up table for mapping the measured scan line interval to obtain at least one frequency of the sampling clock. A system for automatically correcting a sampling clock in a digital video system as described in claim 10, wherein the digital video system is a digital display. A system for automatically correcting a sampling clock in a digital video system as described in claim 10, wherein the synchronization signal is a horizontal synchronization signal. The system for automatically correcting the sampling clock in the digital video system as described in claim 10 of the patent application acquires an expected frequency of the sampling clock. A system for automatically correcting a sampling clock in a digital video system as described in claim 13 wherein said difference unit is a sum of absolute difference (SAD) units for calculating at least partial scanning for each of said phases. The sum of the absolute differences (SAD) of the adjacent data of the line. The system for automatically correcting the sampling clock in the digital video system as described in claim 10 of the patent application acquires the complex candidate frequency of the sampling clock. The system for automatically correcting the sampling clock in the digital video system as described in claim 15 of the patent application determines the difference for each of the candidate frequencies. A system for automatically correcting a sampling clock in a digital video system as described in claim 16 wherein the controller further issues a frequency control signal for controlling the clock generator. The system for automatically correcting the sampling clock in the digital video system as described in claim 17 of the patent application further generates the sampling clock corresponding to the frequency of the maximum difference. A system for automatically correcting a sampling clock in a digital video system as described in claim 15 wherein said difference unit is a sum of absolute difference (SAD) units for each of said phase and said candidate frequency. Calculating a sum of absolute differences (SAD) of the neighboring data of at least a portion of the scan lines. A system for automatically correcting a sampling clock in a digital video system as described in claim 10, further comprising a phase controller for providing phase information to the clock generator according to a phase control signal sent by the controller To control the phase offset.