CN101989417B - Method and system for automatically correcting sampling clocks in digital video system - Google Patents
Method and system for automatically correcting sampling clocks in digital video system Download PDFInfo
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- CN101989417B CN101989417B CN 200910164997 CN200910164997A CN101989417B CN 101989417 B CN101989417 B CN 101989417B CN 200910164997 CN200910164997 CN 200910164997 CN 200910164997 A CN200910164997 A CN 200910164997A CN 101989417 B CN101989417 B CN 101989417B
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Abstract
The invention relates to a method and a system for automatically correcting sampling clocks in a digital video system. The method comprises the following steps of: generating a plurality of sampling clocks with different phases and sequentially transmitting the sampling clocks to an analog to digital converter (ADC); aiming at each phase, deciding a difference value of at least one group of adjacent data output by the ADC; and deciding a maximum difference value and generating a sampling clock corresponding to the phase of the maximum difference value.
Description
Technical field
The present invention relates to simulate to digital conversion (ADC), particularly relate to a kind of numeral that is applicable to the digital video system to analog-converted, in order to phase place or the frequency of automatic calibration sampling clock.
Background technology
When digital video system (for example digital indicator or digiboard (graphics digitizer)) reception and treatment of simulated video signal, must first the analog video signal be converted to digital form, be convenient to signal and be able in digital field, process.Calcspar display simulation video signal source 10 (for example graphics card of computing machine) and the digital video system 12 (for example liquid crystal display) of Fig. 1.Analog video signal (for example analog rgb (RGB) or YPbPr colour difference signal) is transmitted to digital video system 12 via cable 14A in analog video source 10.The analog video signal that receives is converted into the digital video signal by analog-to-digital converter (ADC) 120.When transmitting the analog video signal, cable 14B also transmits synchronizing signal (horizontal-drive signal H for example
SynAnd vertical synchronizing signal V
Syn).The synchronizing signal that receives is by the processing of clock generator 122, thereby generation sampling clock (or pixel clock), changes in order to trigger analog-to-digital converter (ADC) 120.
Because the otherness of impedance and length between cable 14A and the cable 14B, analog video signal and synchronizing signal may arrive digital video system 12 in the slightly different time.In other words, control simulation to the phase place of the sampling clock of digital quantizer (ADC) 120 or even frequency may with analog video source 10 in synchronous mutually in order to the phase/frequency of the pixel clock that produces the analog video signal.Thereby cause the reduction of output (for example show image) quality of digital video system 12.
In order to improve the shortcoming of conventional digital video-signal system, thereby there is the people to propose some improvement mechanism.For example, United States Patent (USP) the 5th, 767, No. 916 (are entitled as " Method and Apparatus for Automatic Pixel Clock Phase and Frequency Correction in Analog to Digital Video Signal Conversion ") propose a kind of technology, it is by the developed width that compares video image and an expection image width, in order to adjust pixel clock frequency.Yet when video image had suitable white space, this technology can't accurately reach effective generation pixel clock frequency.
United States Patent (USP) the 6th, 268, No. 848 (are entitled as " Method and Apparatus Implemented in an Automatic Sampling Phase Control System for Digital Monitors ") propose a kind of technology, it is by collecting horizontal digital sampling value and seeking its peak value and valley, in order to control sampling phase.
No. the 2006/0274207th, U.S. Patent application (be entitled as " Method and Apparatus for Analog Graphics Sample Clock Frequency Verification ") proposes a kind of technology, it is by the difference that measures continuous image frame (frame), in order to automatic selection sampling clock.Yet the image data that this technology must store whole frame could measure its difference according to this.
Above-mentioned conventional art can't be effectively or is solved easily the phase/frequency problem of sampling clock, therefore needs the mechanism that proposes a kind of novelty badly, with effective means and use minimum resource or time, in order to proofread and correct the phase/frequency of sampling clock.
Summary of the invention
In view of above-mentioned, one of purpose of the embodiment of the invention is to propose a kind of method and system, effectively and easily proofreaies and correct phase place or/and the frequency of sampling clock, in order to analog to digital conversion (ADC).
According to one embodiment of the invention, produce a plurality of sampling clocks that have an expectation frequency and have out of phase, and be orderly sent to analog-to-digital converter (ADC).For each phase place, determine analog-to-digital converter (ADC) adjacent data of exporting absolute difference with (SAD).Determine a maximum difference, and produce the sampling clock corresponding to the phase place of maximum difference.
According to another embodiment of the present invention, produce a plurality of sampling clocks that have a plurality of Candidate Frequencies and have out of phase, and be orderly sent to analog-to-digital converter (ADC).For each phase place and each Candidate Frequency, determine analog-to-digital converter (ADC) adjacent data of exporting absolute difference with (SAD).Determine a maximum difference, and produce the sampling clock corresponding to phase place and the frequency of maximum difference.
The invention provides a kind of in the digital video system method of automatic calibration sampling clock, comprise: produce this sampling clock, simulate to digital conversion in order to triggering; Generation has a plurality of sampling clocks of out of phase; For each this phase place, determine that this simulates the difference of at least one group of adjacent data of exporting to digital conversion; Determine a maximum difference; And produce this sampling clock corresponding to the phase place of this maximum difference, wherein the step of above-mentioned generation sampling clock comprises: according to synchronizing signal and system clock, measure scan line spacings; And according to the scan line spacings that measures gained, obtain a plurality of Candidate Frequencies of this sampling clock, wherein for each Candidate Frequency, determine this difference.
The present invention also provide a kind of in the digital video system system of automatic calibration sampling clock, comprise: an analog-to-digital converter, in order to change analog video signal to a digital video signal; One clock generator, it is according to synchronous signal and a system signal, and in order to produce this sampling clock, its generation has a plurality of sampling clocks of out of phase, and is sent to this analog-to-digital converter; One difference unit for each this phase place, determines the difference of at least one group of adjacent data that this analog-to-digital converter is exported; An and controller, in order to determining a maximum difference, and control this clock generator to produce this sampling clock corresponding to the phase place of this maximum difference, wherein above-mentioned clock generator comprises: an amount of space measurement unit, according to this synchronizing signal and system clock, measure scan line spacings; Reach one and table look-up, the scan line spacings in order to mapping measurement gained to obtain a plurality of Candidate Frequencies of this sampling clock, wherein for each Candidate Frequency, determines this difference.
Description of drawings
Calcspar display simulation video signal source and the digital video system of Fig. 1.
Fig. 2 shows the system block diagrams of the embodiment of the invention, and it is applicable to the digital video system with the automatic calibration sampling clock.
Fig. 3 shows the method flow diagram of first embodiment of the invention, and it is applicable to the digital video system with the automatic calibration sampling clock.
Fig. 4 A shows the detailed block diagram of the clock generator of the embodiment of the invention.
Fig. 4 B illustration one scan line interval.
Fig. 5 illustration analog video signal and have the sequential chart of the sampling clock of out of phase.
Fig. 6 A show needle to each phase place to calculate its sad value.
Fig. 6 B shows the detailed block diagram of SAD unit.
Fig. 7 shows the method flow diagram of second embodiment of the invention, and it is applicable to the digital video system with the automatic calibration sampling clock.
Fig. 8 show needle to each phase place and frequency to calculate its sad value.
The reference numeral explanation
10 analog video sources
12 digital video systems
120 analog-to-digital converters (ADC)
122 clock generators
14A, 14B cable
The system of 2 automatic calibration sampling clocks
20 analog-to-digital converters (ADC)
22 clock generators
220 amount of space measurement units
222 table look-up (LUT)
24 phase controllers
26 controllers
28 difference unit (SAD unit)
280 working storages
282 absolute difference unit
284 accumulators
286 totalizers
The 31-37B step
Embodiment
Fig. 2 shows the calcspar of the system 2 of the embodiment of the invention, and it is applicable to the digital video system with automatic calibration sampling clock (or pixel clock).Fig. 3 shows the method flow diagram of first embodiment of the invention, and it is applicable to the digital video system with the automatic calibration sampling clock.Although present embodiment is with digital indicator (for example liquid crystal display) as an example, however the present invention also applicable to other digital video system, digiboard (graphics digitizer) for example.
Consult Fig. 2, analog-to-digital converter (ADC) 20 self simulation video signal sources (for example 10 of Fig. 1, such as computer graphics card) receives the analog video signal.Then, analog-to-digital converter (ADC) 20 is converted to the digital video signal with analog video signal (for example analog rgb (RGB) or YPbPr colour difference signal).
On the other hand, clock generator 22 also receives synchronizing signal, for example horizontal-drive signal H in self simulation video signal source
SynAnd vertical synchronizing signal V
SynClock generator 22 produces sampling clock (or pixel clock) according to this according to the system clock of the synchronizing signal that receives and system 2, changes in order to trigger analog-to-digital converter (ADC) 20.Fig. 4 A shows the detailed block diagram of the clock generator 22 of the embodiment of the invention.At first, measure scan line spacings (scan line interval) with amount of space measurement unit 220, its system clock number with each line count (step 31, Fig. 3).Fig. 4 B illustration one scan line interval H
Total, it starts from horizontal-drive signal H
SynRise edge and next horizontal-drive signal H finally
SynRise edge.Then, in step 32, measure the scan line spacings that obtains and map to corresponding expection sampling clock by tabling look-up (LUT) 222, it has frequency f 0.In the present embodiment, the content of (LUT) 222 that table look-up comprises many data, and each data comprises scan line spacings and the corresponding sampling clock with individual frequencies thereof.These data can be obtained by experiment.In another embodiment, sampling clock then is simultaneously according to horizontal-drive signal H
SynAnd vertical synchronizing signal V
SynThe reflection and get.It should be noted that amount of space measurement unit 220 and (LUT) 222 that table look-up not necessarily will be implemented in the clock generator 22.
In next step 33, clock generator 22 produces a plurality ofly has frequency f 0 but the sampling clock of out of phase, and is orderly sent to analog-to-digital converter (ADC) 20.The phase information that clock generator 22 provides according to phase controller 24 is to produce the sampling clock of out of phase (for example p1, p2...pm).This phase controller 24 is controlled by the phase control signal PCS of controller 26 again.Fig. 5 illustration analog video signal and have the sequential chart of the sampling clock of out of phase p1-pm, wherein, the An representative inputs to the analog video signal level of analog-to-digital converter (ADC) 20, and the Dn representative is from the sampled data (or digital video signal) of analog-to-digital converter (ADC) 20 outputs.This figure demonstrates, and the analog video signal can't correctly be taken a sample by phase place p1.
Then, for each phase place, determined the difference (step 34) of at least one group of adjacent data that analog-to-digital converter (ADC) 20 is exported by difference unit 28.In one embodiment, for each phase place pn (n=1 to m), calculate (partial or complete) sweep trace (or or frame) adjacent data absolute difference and (sum of absolute differences, SAD) Sn (n=1 to m), as shown in Figure 6A.Sad value S can be expressed from the next:
Wherein, D
iRepresent i the data of sweep trace (or field or frame).
Fig. 6 B shows the detailed block diagram of difference unit 28 (or SAD unit), in order to calculate the sad value of adjacent R, G, B (red, green, blue) data.Wherein, at present data (for example R (red)) and the last data that is stored in working storage 280 are sent to absolute difference unit 282, in order to calculate its absolute difference.After absolute difference is accumulated for the whole piece sweep trace via accumulator 284, thus obtain absolute difference and (SAD).Different video signals form (for example R in this example, G, B) and are added up via totalizer 286, thereby produce the corresponding final sad value of phase place pn.Although present embodiment with video signal data R, G, B as illustration, yet the present invention is also applicable to other color space (for example YUV).
The sad value Sn that calculates is orderly sent to controller 26.After the data of all phase places (p1-pm) all are disposed (step 35), controller 26 namely determines maximum sad value (step 36).Controller 26 then sends phase control signal PCS in order to control phase controller 24, its according to phase control signal PCS with the control phase side-play amount.Phase controller 24 is sent phase information again to clock generator 22, so that the phase place of the sampling clock that clock generator 22 produces corresponds to maximum sad value (step 37).In view of the correctness of phase place can be proportional to sad value, so the sampling clock that step 37 is obtained namely can correctly be taken a sample to the analog video signal.Moreover because SAD is a kind of very quick and easy tolerance, so sampling clock can be effectively and obtain easily proofreading and correct.
Although present embodiment is with SAD as an example, yet also can use other difference metric, for example the difference of two squares and (sum of squared differences, SSD).Moreover, do not need to calculate the sad value of all phase places.For example, in another embodiment, can be for a certain phase place (for example intermediate phase p3) to calculate its sad value.If calculate the sad value of gained greater than a preset reference value, then the phase correction with sampling clock corresponds to present sad value; Otherwise, continue to calculate its sad value for another phase place.This program can mode be carried out according to binary search (binary search), until resulting sad value is greater than the preset reference value.
Fig. 7 shows the method flow diagram of second embodiment of the invention, and it is applicable to the digital video system with the automatic calibration sampling clock.Present embodiment (Fig. 7) is similar to last embodiment (Fig. 3), and both differences will be described as follows.In this (second) embodiment, in measuring scan line spacings (step 31) afterwards, reflection produces a plurality of Candidate Frequency fr (r=0 to s-1) (for example, six Candidate Frequency f0 to f5) (step 32B).
In determining maximum sad value (step 36) afterwards, controller 26 then sends phase control signal PCS in order to control phase controller 24, and it sends phase information again to clock generator 22.Controller 26 also sends frequency control signal FCS in order to control clock generator 22.By this, so that the phase place of the sampling clock that clock generator 22 produces and frequency correspond to maximum sad value (step 37B).Therefore, the sampling clock that obtains of step 37B namely can correctly be taken a sample to the analog video signal.
The above is preferred embodiment of the present invention only, is not the scope that limits claim of the present invention; All other do not break away from the equivalence of finishing under the spirit that invention discloses and changes or modify, and all should be included in the claim of the present invention.
Claims (16)
1. the method for an automatic calibration sampling clock in the digital video system comprises:
Produce this sampling clock, simulate to digital conversion in order to triggering;
Generation has a plurality of sampling clocks of out of phase;
For each this phase place, determine that this simulates the difference of at least one group of adjacent data of exporting to digital conversion;
Determine a maximum difference; And
Generation is corresponding to this sampling clock of the phase place of this maximum difference,
Wherein the step of above-mentioned generation sampling clock comprises:
According to synchronizing signal and system clock, measure scan line spacings; And
According to the scan line spacings that measures gained, obtain a plurality of Candidate Frequencies of this sampling clock,
Wherein for each Candidate Frequency, determine this difference.
2. the method for automatic calibration sampling clock in the digital video system as claimed in claim 1, wherein above-mentioned digital video system is digital indicator.
3. the method for automatic calibration sampling clock in the digital video system as claimed in claim 1, wherein above-mentioned synchronizing signal is a horizontal-drive signal.
4. the method for automatic calibration sampling clock in the digital video system is as claimed in claim 1 obtained an expected frequence of this sampling clock.
5. the method for automatic calibration sampling clock in the digital video system as claimed in claim 4, for each this phase place, be calculated to the small part sweep trace this adjacent data absolute difference and.
6. the method for automatic calibration sampling clock in the digital video system as claimed in claim 1 also produces this sampling clock corresponding to the frequency of this maximum difference.
7. the method for automatic calibration sampling clock in the digital video system as claimed in claim 1, for each this phase place and this Candidate Frequency, be calculated to the small part sweep trace this adjacent data absolute difference and.
8. the system of an automatic calibration sampling clock in the digital video system comprises:
One analog-to-digital converter is in order to change analog video signal to a digital video signal;
One clock generator, it is according to synchronous signal and a system signal, and in order to produce this sampling clock, its generation has a plurality of sampling clocks of out of phase, and is sent to this analog-to-digital converter;
One difference unit for each this phase place, determines the difference of at least one group of adjacent data that this analog-to-digital converter is exported; And
One controller in order to determining a maximum difference, and is controlled this clock generator producing this sampling clock corresponding to the phase place of this maximum difference,
Wherein above-mentioned clock generator comprises:
One amount of space measurement unit according to this synchronizing signal and system clock, measures scan line spacings; And
One tables look-up, and measures the scan line spacings of gained in order to mapping, obtaining a plurality of Candidate Frequencies of this sampling clock,
Wherein for each Candidate Frequency, determine this difference.
9. the system of automatic calibration sampling clock in the digital video system as claimed in claim 8, wherein above-mentioned digital video system is digital indicator.
10. the system of automatic calibration sampling clock in the digital video system as claimed in claim 8, wherein above-mentioned synchronizing signal is a horizontal-drive signal.
11. the system of automatic calibration sampling clock in the digital video system as claimed in claim 8 obtains an expected frequence of this sampling clock.
12. the system of automatic calibration sampling clock in the digital video system as claimed in claim 11, wherein above-mentioned difference unit be an absolute difference and the unit, it is for each this phase place, be calculated to the small part sweep trace this adjacent data absolute difference and.
13. the system of automatic calibration sampling clock in the digital video system as claimed in claim 8, wherein above-mentioned controller also sends a frequency control signal, in order to control this clock generator.
14. the system of automatic calibration sampling clock in the digital video system also produces this sampling clock corresponding to the frequency of this maximum difference as claimed in claim 13.
15. the system of automatic calibration sampling clock in the digital video system as claimed in claim 8, wherein above-mentioned difference unit be an absolute difference and the unit, it is for each this phase place and this Candidate Frequency, be calculated to the small part sweep trace this adjacent data absolute difference and.
16. the system of automatic calibration sampling clock in the digital video system also comprises a phase controller as claimed in claim 8, its phase control signal that sends according to this controller is to provide phase information to this clock generator, in order to the control phase side-play amount.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6097444A (en) * | 1998-09-11 | 2000-08-01 | Mitsubishi Denki Kabushiki Kaisha | Automatic image quality adjustment device adjusting phase of sampling clock for analog video signal to digital video signal conversion |
| US20020018125A1 (en) * | 2000-06-15 | 2002-02-14 | Miyuki Tachibana | Image display apparatus |
| JP2004144842A (en) * | 2002-10-22 | 2004-05-20 | Sanyo Electric Co Ltd | Matrix type display device and method of automatic adjustment of sampling clock in matrix type display device |
| CN101499258A (en) * | 2008-01-31 | 2009-08-05 | 恩益禧电子股份有限公司 | Signal processing method and circuit to convert analog signal to digital signal |
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2009
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6097444A (en) * | 1998-09-11 | 2000-08-01 | Mitsubishi Denki Kabushiki Kaisha | Automatic image quality adjustment device adjusting phase of sampling clock for analog video signal to digital video signal conversion |
| US20020018125A1 (en) * | 2000-06-15 | 2002-02-14 | Miyuki Tachibana | Image display apparatus |
| JP2004144842A (en) * | 2002-10-22 | 2004-05-20 | Sanyo Electric Co Ltd | Matrix type display device and method of automatic adjustment of sampling clock in matrix type display device |
| CN101499258A (en) * | 2008-01-31 | 2009-08-05 | 恩益禧电子股份有限公司 | Signal processing method and circuit to convert analog signal to digital signal |
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