KR20160050121A

KR20160050121A - High Resolution Target simulator with Dual Sampling Clock Rates.

Info

Publication number: KR20160050121A
Application number: KR1020140147066A
Authority: KR
Inventors: 이일근; 이종필
Original assignee: 한남대학교 산학협력단
Priority date: 2014-10-28
Filing date: 2014-10-28
Publication date: 2016-05-11

Abstract

The present invention relates to a radar target simulator using multisampling clock frequencies, and more specifically, to a high resolution radar target simulator capable of automatically simulating the moving distance of a target via accumulated differences between two clocks by differently controlling an ADC sampling clock and a DAC sampling clock. The radar target simulator using multisampling clock frequencies of the present invention comprises: an ADC (200); a range delay control block (110); a memory control block (120); a memory (130); an FPGA (100); a first DDS(300); a second DDS(400); and a DAC (500).

Description

TECHNICAL FIELD [0001] The present invention relates to a radar target simulator using a multiple sampling clock frequency.

[0001] The present invention relates to a radar target simulator using multiple sampling clock frequencies, and more particularly, to a system and method for controlling a radar target simulator using multiple sampling clock frequencies, The distance control resolution is also related to a high resolution radar target simulator that can provide significantly improved performance over conventional methods.

A simulated target device for radar test, which is one of the test equipment for radar performance verification used in the radar development process requiring performance such as SAR (Synthetic Aperture Radar) requiring acquisition of image with a resolution of several tens of centimeters at over 20 km, And the Doppler frequency according to the relative speed between the radar and the target.

However, the distance and Doppler frequency simulation method actually used in the target distance simulator are sampled by an ADC (analog to digital converter), and after storing the data stored in the memory, the data is delayed by the sampling clock unit, The delay control unit can not be controlled more precisely than the cycle of the ADC sampling clock.

In addition, the Doppler frequency simulation changes the frequency in the local generator independent of the distance simulation of the target, so that phase distortion occurs in the time domain where the distance of the target changes, and the target signal quality of the radar simulation is degraded.

In recent years, attempts have been made to compensate for the shortcomings due to the phase correction according to the distance control values, but the calculation and correction methods are complicated and difficult to implement.

1 is a block diagram of a target distance simulator using a conventional single sampling clock.

As shown in FIG. 1, the simulated target apparatus for radar testing should simulate the target signal delay time, Doppler frequency, and signal strength according to the distance and the moving speed of the target.

Conventionally, in the implementation of such a target distance simulator, a scheme configured to use an ADC clock and a DAC clock of the same value has been mainly used.

In other words, when a radar signal is input, the signal is sampled at 500 MHz ADC clock, and the acquired data is stored in the memory inside the FPGA.

Then, a simulated target signal is generated using a DAC having the same clock value after a certain time delay.

If the delay time of the target signal is smaller than 1 cycle of the ADC sampling clock, there is no change in the delay time. If the delay time of the target signal is larger than 1 cycle of the ADC sampling clock, Change.

The target signal should change the delay time according to the initial distance and the moving speed, and the following Equation 1 for calculating the delay time of the target signal according to the distance of the target may be used.

&Lt; Formula 1 >

When the target information is given as shown in FIG. 2, a scenario calculation for simulating the delay time of the moving target using Equation 1 can be performed to obtain the theoretical result as shown in FIG.

However, this calculation method provides the result obtained by the ideal method in which sampling clock information of the DAC, which is the hardware characteristic of the simulator, is not reflected. Actually, when calculating the delay time using this method, Lt; / RTI >

FIG. 4 shows that a propagation delay time of 2 usec in hardware defined by a sampling clock of 500 MHz is generated in the DAC, thereby causing a movement distance and a target distance error of a simulated target signal.

As a concrete application example, when the target moves for 3 seconds, the difference between the delay time due to the target distance simulator and the ideal calculation result by the conventional single sampling clock utilization method, which is actually applied, The delay time and the delay time error are respectively generated.

The distance and Doppler frequency simulator of the single sampling clock method used in the existing simulated target device cause the target distance error due to the delay time error. In other words, the conventional target distance simulator is obtained by ADC and delay time based on DAC clock when restoring data stored in digital memory,

It is difficult to control the distance control of the target signal to a unit smaller than the DAC clock unit by basically simulating the movement distance of the target signal in a scaled manner, so that it is not suitable for the recently developed high resolution radar test.

Therefore, it was necessary to provide a simulator that can control the ADC sampling clock and the DAC sampling clock differently, and can automatically simulate the moving distance of the target by the cumulative difference of the two clocks.

Korean Patent Application No. 10-2011-0022611 (March 15, 2011)

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems of the prior art, and it is an object of the present invention to provide a method of controlling a DC sampling clock and a DAC sampling clock, Resolution radar target simulator capable of providing a significantly improved performance in distance control resolution compared to the conventional method.

According to an aspect of the present invention, there is provided a radar target simulator using a multiple sampling clock frequency,

An ADC 200 for converting the analog load signal into digital data with a sampling clock of 500 MHz and storing the digital data in a memory when a radar signal is input;

A Range Delay control block 110 for calculating a delay time to perform a time delay,

A memory control block 120 for providing data in the memory to the DAC,

A memory 130 for storing digital data provided by the ADC,

(FPGA) 100 comprising a DDS control block 140 for providing frequency control data to a first DDS and a second DDS;

A first DDS 300 and a second DDS 400 for receiving frequency control data from the DDS control block to generate different sampling clocks and supplying them to the ADC and the DAC, respectively;

And a DAC (500) for converting the digital data of the memory into an analog signal, thereby solving the problems of the present invention.

The radar target simulator using the multiple sampling clock frequency according to the present invention having the above-

DC sampling clocks and DAC sampling clocks are controlled differently, so that the cumulative difference between two clocks automatically simulates the moving distance of the target, and the distance control resolution can provide much improved performance compared to the conventional method .

1 is a block diagram of a target distance simulator using a conventional single sampling clock.
Fig. 2 shows an example of the target information, and Fig. 3 shows a result of calculating the delay time of the theoretical target.
FIG. 4 is a graph illustrating a delay time simulation result using a conventional single sampling clock utilizing method, and FIG. 5 is a diagram simulating a delay time using a conventional single sampling clock type target distance simulator.
FIG. 6 is an error diagram of a delay time occurring when a conventional single sampling clock type target distance simulator is used.
FIG. 7 is a block diagram of a radar target simulator using a multiple sampling clock frequency according to an embodiment of the present invention, FIG. 8 is a detailed block diagram of a memory controller for generating a target distance using an FPGA, FIG. 9 is a block diagram of a high- Distance simulator shape.
FIG. 10 shows a basic target distance control method, and FIG. 11 shows a target distance simulator travel distance control method of the present invention.
FIG. 12 is a diagram comparing delay time simulations using a conventional target distance simulator according to the present invention, and FIG. 13 is a diagram comparing delay time errors using a conventional target distance simulator according to the present invention.

Hereinafter, embodiments of a radar target simulator using a multiple sampling clock frequency according to the present invention will be described in detail.

Generally, the high resolution target distance simulator is a core component of the simulated target generator, and applies the delay time and the Doppler frequency according to the distance of the simulated target signal according to the moving speed.

7 is a block diagram of a radar target simulator using multiple sampling clock frequencies in accordance with an embodiment of the present invention.

7, the radar target simulator using the multiple sampling clock frequency of the present invention includes an ADC 200, an FPGA 100, a first DDS 300 and a second DDS 400, a DAC 500, .

That is, when the radar signal is input, the ADC 200 converts the analog signal into digital data with a sampling clock of 500 MHz and stores the converted digital data in the memory.

The FPGA (100) includes a Range Delay control block (110) for calculating a delay time to perform a time delay, a memory control block (120) for providing data in a memory as a DAC, A memory 130 for storing the provided digital data, and a DDS control block 140 for providing frequency control data to the first DDS and the second DDS.

At this time, the first DDS 300 and the second DDS 400 receive frequency control data from the DDS control block, generate different sampling clocks, and supply the same to the ADC and the DAC, respectively.

The DAC 500 converts the digital data of the memory into an analog signal.

In operation, when a radar signal is input, the ADC converts the analog signal into digital data with a sampling clock of 500 MHz, stores it in memory, and then uses the Range Delay Control block to calculate the time delay by the delay time calculated in Equation 1 .

The delayed data is controlled by a memory control block, and the data in the memory is transferred to the DAC, which converts the data into an analog signal, thereby generating a target signal with a delay time according to the distance of the target.

At this time, the first DDS 300 and the second DDS 400 receive the respective frequency control data from the DDS Control block, generate different sampling clocks, and supply them to the ADC and the DAC.

The following describes the structure and operation principle of the memory controller for generating the target distance, which is implemented in the FPGA as a main part of the simulator.

Fig. 8 is a detailed block diagram of an F-Fiji memory controller for generating a target distance constituting the radar target simulator of the present invention.

In order to control the waveform storage memory, it is divided into an address counter for memory write and an address counter for read, and the difference between the time stored in the memory and the read time is used to calculate the distance Apply the delay time.

Also, the address counter for the memory read address is designed to apply the delay time change according to the movement of the target by dividing the address counter for starting distance and the address counter for moving distance.

If the address counter value for the starting distance is added to the data of the address counter for the moving distance, the distance of the target is increased. On the other hand, if the address counter for the starting distance is subtracted from the starting distance address counter, do.

The address counter for specifying the memory address used here is implemented as a ring buffer, which is repeatedly counted up to a maximum value.

The shape of the high-resolution target distance simulator using the dual sampling clock produced using the principle and method described above is shown in FIG.

The following describes the distance control method of the basic target expressed as shown in FIG. 10 in order to explain the method of implementing the target distance using the target distance simulator and the performance analysis result.

As shown in FIG. 10 (A), when a radar transmission pulse is input to the simulator, the ADC acquires data every 2 nsec, which is one cycle of a sampling clock of 500 MHz, and stores it in the memory.

The memory used in this simulator is implemented as a ring buffer in which data is continuously stored as shown in (B).

In this case, if the rewriting operation is performed before the stored data is read, the target signal can not be generated.

Therefore, the stored data must be read out before the signal is overwritten.

Thus, a distance delay of a target longer than the memory maximum storage time can not be simulated.

(C) starts reading the memory data after a delay time of 10usec when simulating a 1.5km distance of the simulated target signal. In case of (D), when simulating the simulated target signal at a distance of 150km, a time delay of 1msec And starts reading data in the memory.

The maximum delay time (maximum storage time) in the design of the target distance simulator is determined by the capacity of the memory and the ADC sampling clock.

Maximum storage time = (11,700,000 bits / 18 bits) * 2 nsec = 1,300,000 nsec <Formula 2>

Next, a distance simulation method according to the movement of the target in the target distance simulator constructed in the present invention will be described with reference to FIG.

The radar transmission signal input to the distance simulator acquires data at a sampling frequency of 500 MHz using an ADC as shown in FIG. 11 (A), and stores the data in a digital memory.

As shown in FIG. 11B, the stored data is delayed according to the start distance of the radar target, and then the data is read and converted into an analog signal using the DAC.

In this case, if the DAC clock is controlled to be equal to the ADC clock, the distance of the target signal is fixed. If the sampling clock of the DAC is controlled as shown in Equation 3 according to the target speed as shown in FIG. 11C, The time difference of the DAC sampling clock is accumulated to generate a target signal whose distance moves.

Finally, the sampling clock of the DAC shown in FIG. 11 (D) is obtained as shown in Equation (3).

&Quot; (3) "

In order to analyze the performance of the target distance simulator of the present invention, simulations were performed using the conventional simulator and the simulator of the present invention, respectively, after applying the target-related conditions of FIG.

That is, when the target moves for 3 seconds, the results of obtaining the delay time and the delay time error according to the pulse number change using the conventional method and the target distance simulators of the present invention are shown in FIG. 12 and FIG. 13, respectively.

As shown in FIG. 12, the target distance simulator using this double sampling clock differs from the propagation delay time simulated using the conventional single sampling clock in a step-like manner. As shown in FIG. 13, Is increased with linear characteristics.

FIG. 13 shows a comparison between results of graphs representing errors of the propagation delay time simulated by the conventional method and the improved method.

In the conventional method, it is confirmed that the propagation delay time due to the increase in distance is repeatedly increased / decreased in the minimum unit cycle that can be controlled. On the other hand, in the method using the double sampling clock, the propagation delay time error is relatively higher It can be confirmed that it is small.

That is, the error RMS value when the propagation delay time is simulated in the conventional manner is 0.5859 * 10-9sec, and the error RMS value when the propagation delay time is simulated by the method of the present invention is 0.0001 * 10-9sec. It is confirmed that the characteristics of the high resolution target distance simulator using the double sampling clock of the method are greatly improved.

The target distance simulator using the conventional single sampling clock method is a method of delaying the time based on the DAC clock when the data stored in the digital memory is acquired by the ADC and changing the delay time according to the distance change. It is difficult to control the distance control of the target signal in units smaller than the DAC clock unit, and the distance and Doppler frequency simulator cause a target distance error due to the delay time error.

Accordingly, in the present invention, the ADC sampling clock and the DAC sampling clock are controlled differently so that the moving distance of the target is automatically simulated by the cumulative difference of the two clocks. In addition, the distance control resolution has a high resolution A target distance simulator is provided.

Utilizing the present invention, it will be possible to utilize not only conventional navigation radar but also radar performance evaluation in radar development in synthetic aperture radar, FMCW radar, and weather radar, which require high resolution distance resolution.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is to be understood, therefore, that the embodiments described above are to be considered in all respects as illustrative and not restrictive.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: F
200: ADC
300: 1st DDS
400: my 2DDS
500: DAC

Claims

In a radar target simulator using a sampling clock frequency,
An ADC 200 for converting the analog load signal into digital data with a sampling clock of 500 MHz and storing the digital data in a memory when a radar signal is input;
A Range Delay control block 110 for calculating a delay time to perform a time delay,
A memory control block 120 for providing data in the memory to the DAC,
A memory 130 for storing digital data provided by the ADC,
(FPGA) 100 comprising a DDS control block 140 for providing frequency control data to a first DDS and a second DDS;
A first DDS 300 and a second DDS 400 for receiving frequency control data from the DDS control block to generate different sampling clocks and supplying them to the ADC and the DAC, respectively;
And a DAC (500) for converting the digital data of the memory into an analog signal, thereby generating a target signal to which a delay time according to the distance of the target is applied. .

The method according to claim 1,
The sampling clock of the DAC 500,
Wherein the radar target simulator is calculated by the following equation.

The method according to claim 1,
The FPGA (100)
A waveform storage memory, and a distance delay circuit. In order to control the waveform storage memory, the address counter for memory writing and the address counter for reading are used and the distance delay time of the target is calculated by using the difference between the time stored in the memory and the reading time. Wherein the radar target simulator includes a plurality of sampling clock frequencies.