JP2007295096A - Device and method for generating synchronization signal, and digital camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronization signal generating device that makes the frame rate of imaging same as that of display even if the period of the synchronization signal for imaging differs from that for display and can cope with various systems, and to provide a digital camera having such a synchronization signal generating device and such a synchronization signal generating method. <P>SOLUTION: A vertical synchronization signal for imaging and that of display are inputted to a phase comparator 33 in an imaging synchronization generator for detecting the phase difference between them. The phase difference is inputted into a period controller 34 for comparison with a target phase difference. When the phase difference between the vertical synchronization signal for imaging and that for display differs from the target phase difference, the period of a horizontal synchronization signal for imaging is controlled so that the difference becomes small. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a synchronization signal generation device that generates a synchronization signal for driving an image sensor and a display device, a digital camera including the synchronization signal generation device, and a synchronization signal generation method.

  Proposal regarding a digital camera having a function (referred to as a through-image display function, a live view display function, etc.) for displaying an image obtained by an image sensor composed of a CCD element, a CMOS element or the like on a display device such as an LCD in real time. There have been many.

  In a conventional digital camera having such a display function, an image signal acquired in real time by an image sensor is subjected to image processing in an image processing unit and then displayed on a display device. At this time, the imaging device is driven in accordance with the imaging synchronization signal generated in the imaging synchronization signal generation device, and the display device is driven in accordance with the display synchronization signal generated in the display synchronization signal generation device.

  Here, if the imaging synchronization signal and the display synchronization signal are asynchronous, the time difference from when the imaging is performed until the image is displayed differs for each frame. This is because the processing time of the image obtained by the image sensor varies from frame to frame. In this case, the image of the previous frame is not displayed in time for the display timing of the image, and the image of the previous frame is displayed continuously, or conversely, a part of the image captured is not displayed for the timing of image capturing. The quality of the live view display may deteriorate.

Therefore, in Patent Document 1, an imaging synchronization signal for driving the imaging device and an imaging clock for generating the imaging synchronization signal are also supplied to the display device, and the supplied imaging device is supplied on the display device side. The display synchronization signal is generated based on the synchronization signal and the imaging clock to synchronize the imaging synchronization signal and the display synchronization signal so that the frame rates of the imaging and display match.
JP-A-9-307786

  Here, the imaging clock varies depending on the type of the imaging element (generally, the clock frequency increases in the case of a high pixel), and similarly, the display clock varies depending on the type of the display device. Even in such a system in which the imaging clock and the display clock are different from each other, it is desirable to match the frame rate of imaging and display. The display synchronization signal is generated based on the imaging clock and cannot be easily applied to a system in which the imaging clock and the display clock are asynchronous.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and a synchronization signal generation device that can make the frame rate of imaging and display the same even when the imaging clock and the display clock are asynchronous and can be used for various systems. Another object of the present invention is to provide a digital camera including such a synchronization signal generation device and such a synchronization signal generation method.

  In order to achieve the above object, a synchronization signal generation device according to a first aspect of the present invention is configured to drive an imaging synchronization signal generation unit that generates an imaging synchronization signal for driving an imaging device and a display device. In the synchronization signal generation device having a display synchronization signal generation unit that generates a display synchronization signal, the imaging synchronization signal generation unit detects a phase difference between the imaging synchronization signal and the display synchronization signal. A phase difference detection unit and a cycle control unit that controls a cycle of the imaging synchronization signal based on the phase difference detected by the phase difference detection unit.

  According to the first aspect, the frame rate of imaging and display can be made the same by controlling the period of the imaging synchronization signal in consideration of the phase difference between the imaging synchronization signal and the display synchronization signal. .

  In order to achieve the above object, a synchronization signal generation device according to a second aspect of the present invention drives an imaging synchronization signal generation unit that generates an imaging synchronization signal for driving an imaging element, and a display device. A display synchronization signal generating device for generating a display synchronization signal for detecting a phase difference between the imaging synchronization signal and the display synchronization signal And a cycle control unit that controls the cycle of the display synchronization signal based on the phase difference detected by the phase difference detection unit.

  According to the second aspect, the frame rate of imaging and display can be made the same by controlling the cycle of the synchronization signal for display in consideration of the phase difference between the synchronization signal for imaging and the synchronization signal for display. .

  In order to achieve the above object, a digital camera according to the third aspect of the present invention includes an image sensor that captures an image of a subject and obtains an image signal, and an imaging synchronization signal for driving the image sensor. An imaging synchronization signal generation unit that generates, an image processing unit that processes the imaging signal acquired by the imaging device to obtain image data, and a display device that displays an image based on the image data obtained by the image processing unit A display synchronization signal generation unit that generates a display synchronization signal that is asynchronous with the imaging synchronization signal and drives the display device, and between the imaging synchronization signal and the display synchronization signal A phase difference detection unit that detects a phase difference between the imaging synchronization signal and the display synchronization signal so that the phase difference detected by the phase difference detection unit approaches the target phase difference. Characterized by comprising a cycle control unit for.

  In order to achieve the above object, a synchronization signal generation method according to a fourth aspect of the present invention includes an imaging synchronization signal for driving an imaging device, and a signal asynchronous with the imaging synchronization signal. A synchronization signal generation method for generating a display synchronization signal for driving a display device, wherein a phase difference between the imaging synchronization signal and the display synchronization signal is detected, and the detected phase difference is detected. One of the periods of the imaging synchronization signal and the display synchronization signal is controlled so as to be close to the target phase difference.

  According to these third and fourth aspects, even if the imaging synchronization signal and the display synchronization signal are asynchronous, the phase difference between the imaging synchronization signal and the display synchronization signal becomes the target phase difference. By controlling either the imaging synchronization signal or the display synchronization signal, the imaging and display frame rates can be made the same.

  According to the present invention, even when the period of the synchronization signal for imaging and the period of the synchronization signal for display are different, the synchronization signal generating device that can make the frame rate of imaging and display the same and can support various systems, such synchronization It is possible to provide a digital camera including a signal generation device and such a synchronization signal generation method.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a block diagram of a main part of a digital camera provided with a synchronization signal generating device according to the first embodiment of the present invention. Here, the digital camera of FIG. 1 shows only the configuration related to the live view display operation. The configuration other than that shown in FIG. 1 may be the same as that of a conventional digital camera. For example, a recording medium for recording imaging data may be provided in addition to the configuration shown in FIG.

  The digital camera shown in FIG. 1 includes an imaging device (CCD) 1, a timing generator (TG) 2, an imaging synchronization signal generation unit 3, an imaging clock generation unit 4, an imaging interface (I / F) unit 5, Data bus 6, memory controller 7, memory (SDRAM) 8, image processing unit 9, display I / F unit 10, display unit (TFT) 11, display synchronization signal generation unit 12, and display clock generation Part 13.

  The image pickup device 1 is, for example, a CCD image pickup device, and picks up an image signal by picking up a subject (not shown). The TG 2 generates a drive signal for driving the imaging device 1 based on the imaging synchronization signal from the imaging synchronization signal generation unit 3 and outputs the drive signal to the imaging device 1. The imaging synchronization signal generation unit 3 generates an imaging synchronization signal based on the imaging clock from the imaging clock generation unit 4 and the display synchronization signal from the display synchronization signal generation unit 12 to generate the TG 2 and the imaging I / F. To the unit 5. The imaging clock generation unit 4 includes an oscillation circuit and the like, and generates an imaging clock for generating an imaging synchronization signal in the imaging synchronization signal generation unit 3. Here, the configuration and operation of the imaging synchronization signal generation unit 3 will be described in detail later.

  The imaging I / F 5 receives an imaging synchronization signal from the imaging synchronization signal generation unit 3, acquires an imaging signal from the imaging device 1, performs analog processing such as noise removal and amplification, and digital conversion processing of the analog processed imaging signal, and the like Pre-processing is performed. Then, the imaging data obtained by the preprocessing is stored in the memory 8 via the data bus 6.

  The memory controller 7 performs address control when reading / writing data from / to the memory 8. The memory 8 is composed of, for example, SDRAM, and temporarily stores various data such as imaging data acquired in the imaging I / F 5 and imaging data after image processing is performed in the image processing unit 9. The image processing unit 9 reads out the imaging data from the memory 8 via the data bus 6, performs various image processing for display such as gradation conversion processing and resizing processing, and stores the processed imaging data in the memory 8. To do.

  The display I / F unit 10 reads the imaging data from the memory 8 at the timing of receiving the display synchronization signal from the display synchronization signal generation unit 12, converts it into a video signal, and outputs it to the display unit 11. The display unit 11 is a display unit composed of, for example, a TFT liquid crystal, and displays an image based on the video signal input from the display I / F unit 10. The display synchronization signal generation unit 12 generates a display synchronization signal based on the display clock from the display clock generation unit 13 and outputs the display synchronization signal to the display I / F unit 10, the display unit 11, and the imaging synchronization signal generation unit 3. To do. The display clock generation unit 13 includes an oscillation circuit and the like, and generates a display clock for generating a display synchronization signal in the display synchronization signal generation unit 12.

  The live view display operation in the digital camera shown in FIG. 1 will be described below with reference to FIG. FIG. 2 is a timing chart showing operations of the imaging synchronization signal generation unit 3, the imaging I / F unit 5, the image processing unit 9, the display synchronization signal generation unit 12, and the display I / F unit 10 during live view display. .

  When the vertical synchronization signal CCD_VD is input from the imaging synchronization signal generation unit 3 to TG2, after the invalid period (blanking period), the imaging signal acquired by the imaging device 1 according to the horizontal synchronization signal CCD_HD is one frame at a time, Captured by the imaging I / F unit 5 and preprocessed. Imaging data obtained by preprocessing in the imaging I / F unit 5 is stored in the memory 8 via the data bus 6 under the control of the memory controller 7. When the image data of the number of lines necessary for image processing in the image processing unit 9 is stored in the memory 8, the imaged data is read out by the image processing unit 9, processed, and stored in the memory 8 again.

  After that, when the vertical synchronization signal TFT_VD is input to the display I / F unit 10, the image-processed imaging data stored in the memory 8 is read and converted into a video signal, and the display unit is based on the video signal. 11 displays an image.

  Here, in the first embodiment, the vertical synchronization signal TFT_VD is input from the display synchronization signal generation unit 12 to the display I / F unit 10 with a certain phase difference after the vertical synchronization signal CCD_VD for imaging is input. To do. This constant phase difference is the time from when the capturing of the imaging signal by the imaging I / F unit 5 is started until the imaging data is read out by the display I / F unit 10, particularly the image processing time in the image processing unit 9. Is set according to As shown in FIG. 2, the image processing time varies depending on the traffic of the data bus 6, but a certain degree of estimation is possible. Based on the image processing time, a time is set from the time when the vertical synchronization signal CCD_VD is input to the shortest time at which the display timing does not pass the image processing timing.

  By generating the synchronization signal in this way, a frame that cannot be displayed because the imaging timing is earlier than the display timing occurs, or the display timing is earlier than the imaging timing and the same frame image continues. Will not be displayed.

  FIG. 3 is a block diagram illustrating a configuration of the imaging synchronization signal generation unit 3 for realizing the synchronization signal generation method according to the first embodiment. The imaging synchronization signal generation unit 3 includes a horizontal counter 31, a vertical counter 32, a phase comparator 33, and a cycle controller 34.

  The horizontal counter 31 is a counter for generating a horizontal synchronization signal CCD_HD for imaging. The horizontal counter 31 counts up every time an imaging clock is input from the imaging clock generation unit 4 and corresponds to the next horizontal line when counting up to one cycle of CCD_HD designated by the cycle controller 34. The CCD_HD to be output is output to the TG 2, the imaging I / F unit 5, and the vertical counter 32. Then, when one CCD_HD is output, the counter is initialized.

  The vertical counter 32 is a counter for generating a vertical synchronization signal CCD_VD for imaging. The vertical counter 32 counts up every time the horizontal synchronization signal CCD_HD is input from the horizontal counter 31, and when counting up to one cycle (one frame) of CCD_VD, CCD_VD corresponding to the next frame is set as TG2. And output to the imaging I / F unit 5 and the phase comparator 33. Then, the counter is initialized when one CCD_VD is output.

  The phase comparator 33 detects the phase difference between the vertical sync signal CCD_VD for imaging input from the vertical counter 32 and the vertical sync signal TFT_VD for display input from the display sync signal generation unit 12, and the detected level is detected. The value of the phase difference is output to the cycle controller 34. The cycle controller 34 sets the cycle of the imaging synchronization signal so that the phase difference detected by the phase comparator 33 becomes a predetermined target phase difference.

Hereinafter, the cycle control of the synchronization signal for imaging performed by the cycle controller 34 will be described.
First, in the cycle controller 34, a target value (target phase difference) of the phase difference between the vertical sync signal CCD_VD for imaging and the vertical sync signal TFT_VD for display as shown in FIG. 4A is set. . This target phase difference is set corresponding to the time difference shown in FIG.

  The cycle controller 34 compares the phase difference between the CCD_VD and TFT_VD input from the phase comparator 33 with the target phase difference, and the next frame so that the difference between the phase difference between the CCD_VD and TFT_VD and the target phase difference becomes small. The period of CCD_VD at is set.

  For example, as shown in FIG. 4A, when the difference between the phase difference between the CCD_VD and the TFT_VD and the target phase difference is 0 or very small, the CCD_VD cycle in the next frame is the same as the CCD_VD cycle in the current frame. Set to. Thereby, the phase difference between CCD_VD and TFT_VD in the next frame is also equal to the target phase difference.

  As shown in FIG. 4B, when the phase difference between the CCD_VD and the TFT_VD is larger than the target phase difference, the period of the CCD_VD in the next frame is extended by the amount of deviation from the target phase difference. . As a result, the phase difference between CCD_VD and TFT_VD comes closer to the target phase difference than the current frame.

  Conversely, when the phase difference between CCD_VD and TFT_VD is smaller than the target phase difference as shown in FIG. 4C, the period of CCD_VD in the next frame is shortened by the amount of deviation from the target phase difference. . As a result, the phase difference between CCD_VD and TFT_VD comes closer to the target phase difference than the current frame.

  FIGS. 5A to 5C are diagrams illustrating specific examples of the cycle control of the CCD_VD. Here, in the first embodiment, the CCD_VD cycle is controlled by extending or shortening the CCD_HD cycle. That is, by changing the CCD_HD cycle in the horizontal counter 31, it is possible to delay or speed up the timing for outputting the CCD_VD from the vertical counter 32.

  FIG. 5A is a timing chart of cycle control when the phase difference between CCD_VD and TFT_VD is substantially equal to the target phase difference in the previous frame. In this case, as shown in FIG. 5A, the cycle of each CCD_HD of the next frame is made the same as that of the current frame.

  FIG. 6A is a diagram illustrating an outline of the imaging operation when the cycle control of FIG. 5A is performed. The period of the predetermined line after the CCD_VD is input to the TG 2 and the imaging I / F unit 5 is an invalid period (blanking period). This invalid period is a period for synchronizing the readout of the imaging signal, and readout of the imaging signal is not performed within this invalid period. After the invalid period, an image signal for one horizontal line is read each time CCD_HD is input. After the image signal for one frame is read in this way, the CCD_VD corresponding to the next frame is input, and the image signal is read in the same manner for the next frame.

  FIG. 5B is a timing chart of cycle control when the phase difference between CCD_VD and TFT_VD is larger than the target phase difference in the previous frame. In this case, as shown in FIG. 5B, the CCD_HD cycle is extended by the amount of deviation from the target phase difference. In the example of FIG. 5B, the period of the CCD_HD input in the invalid period 2 and the invalid period 3 is extended by a predetermined time so that the total of the extended times becomes a deviation amount.

  FIG. 6B is a diagram illustrating an outline of the imaging operation when the cycle control of FIG. 5B is performed. In the cycle control of FIG. 5B, as shown in FIG. 6B, the cycle of the invalid period is extended. In this case, the readout of the imaging signal is delayed by the extended period, and the imaging and display frame rates are matched without affecting the readout operation of the imaging signal within the effective period.

  FIG. 5C is a timing chart of cycle control when the phase difference between CCD_VD and TFT_VD is smaller than the target phase difference in the previous frame. In this case, as shown in FIG. 5C, the CCD_HD cycle is shortened by the amount of deviation from the target phase difference. In the example of FIG. 5C, the period of the CCD_HD input in the invalid period 2 and the invalid period 3 is shortened by a predetermined time so that the total of the shortened times becomes the deviation amount.

  FIG. 6C is a diagram showing an outline of the imaging operation when the cycle control of FIG. 5C is performed. In the cycle control of FIG. 5C, the period of the invalid period is shortened as shown in FIG. In this case, since the readout of the imaging signal is accelerated by the shortened period, the imaging and display frame rates match.

  As described above, in the first embodiment, even if the imaging clock and the display clock are asynchronous, the phase difference between the imaging synchronization signal and the display synchronization signal always approaches the target phase difference. In addition, the period of the imaging synchronization signal is controlled. Thereby, it is possible to make the frame rate of an imaging and a display correspond.

  Here, the cycle control of the CCD_HD may be performed on only one horizontal line, or may be performed on a plurality of lines as shown in FIGS. 5B and 5C. Actually, the limit of the period that can be expanded and contracted for each horizontal line is determined by the configuration of the horizontal counter, etc., so that a plurality of horizontal lines are formed as shown in FIGS. 5B and 5C. It is preferable to perform the period control separately.

  Furthermore, the cycle of CCD_HD may be changed within the effective period, but it is more preferable to change the period within the ineffective period as shown in FIGS. 5B and 5C. By performing cycle control within the invalid period, it is possible to reduce the possibility that a malfunction such as malfunction of the apparatus will occur because the effective pixel readout is not affected.

  6A and 6B show an example in which the CCD_HD cycle is controlled for each frame, it may be changed only once every several frames. In the first embodiment, the period of the imaging synchronization signal for the next frame is controlled based on the phase difference of the current frame, but the imaging synchronization signal of the next frame is controlled based on the phase difference of the past several frames. The period may be controlled. As described above, CCD_HD can be gently changed by using the phase comparison result of the past frame.

  In the first embodiment, the example in which the cycle of the imaging synchronization signal is controlled has been described. However, the cycle on the display synchronization signal side may be controlled. A block diagram of the digital camera in this case is shown in FIG. FIG. 7 is different from FIG. 1 only in that the imaging synchronization signal from the imaging synchronization signal generation unit 3 is input to the display synchronization signal generation unit 12.

  FIG. 8 shows the configuration of the display synchronization signal generator 12 corresponding to the modification shown in FIG. The display synchronization signal generation unit 12 in FIG. 8 has substantially the same configuration as the imaging synchronization signal generation unit 3 in FIG. 3, and includes a horizontal counter 121, a vertical counter 122, a phase comparator 123, and a cycle controller 124. Composed. However, in this modification, the relationship of cycle control in the cycle controller 124 is opposite to that of the cycle controller 34. That is, when the phase difference between the CCD_VD and the TFT_VD is larger than the target phase difference, the period of the TFT_VD in the next frame is shortened by the amount of deviation from the target phase difference. Conversely, if the phase difference between CCD_VD and TFT_VD is smaller than the target phase difference, the period of TFT_VD in the next frame is extended by the amount of deviation from the target phase difference.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. In the second embodiment, the synchronization between imaging and display is controlled by controlling the period of the imaging clock based on the phase difference between the imaging synchronization signal and the display synchronization signal.

  FIG. 9 is a block diagram of a main part of a digital camera including a synchronization signal generation device according to the second embodiment. In FIG. 9, the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG. In the digital camera shown in FIG. 9, an imaging clock control unit 14 is provided between the imaging synchronization signal generation unit 3 and the imaging clock generation unit 4, and the imaging clock control unit 14 receives from the imaging synchronization signal generation unit 3. The difference from the first embodiment is that the imaging synchronization signal and the display synchronization signal from the display synchronization signal generator 12 are input. In the second embodiment, it is not necessary to provide the phase comparator 33 and the period controller 34 inside the imaging synchronization signal generator 3 shown in FIG.

  FIG. 10 is a block diagram illustrating a configuration of the imaging clock control unit 14 for realizing the synchronization signal generation method according to the second embodiment. The imaging clock controller 14 includes a frequency divider / multiplier 141, a phase comparator 142, a cycle controller 143, and a selector 144.

  The frequency divider / multiplier 141 divides or multiplies the imaging clock from the imaging clock generator 4 and outputs it to the selector 144.

  The phase comparator 142 detects a phase difference between the vertical synchronization signal CCD_VD for imaging input from the imaging synchronization signal generation unit 3 and the vertical synchronization signal TFT_VD for display input from the display synchronization signal generation unit 12, The detected phase difference value is output to the period controller 34. The period controller 143 receives the phase difference detected by the phase comparator 142 and the horizontal synchronization signal CCD_HD from the imaging synchronization signal generator 3. The period controller 143 compares the phase difference detected by the phase comparator 142 with the target phase difference, and the invalid period (blanking period) so that the phase difference detected by the phase comparator 142 approaches the target phase difference. The period of the imaging clock in () is set. Here, the determination as to whether or not the current period is an invalid period is made by counting CCD_HD, for example. The selector 144 receives the clock selection signal from the period controller 34 and receives either the imaging clock input from the imaging clock generator 4 and the imaging clock after frequency division or multiplication in the frequency divider / multiplier 141. Is output to the imaging synchronization signal generator 3.

  FIG. 11 is a timing chart illustrating the imaging clock selection control according to the second embodiment.

  As shown in FIG. 11, the clock frequency of the imaging clock input from the imaging clock generation unit 4 to the imaging clock control unit 14 is constant. When the imaging clock is input to the frequency divider / multiplier 141, the imaging clock is frequency-divided and multiplied. In FIG. 11, only the imaging clock after frequency division is shown.

  In this state, the phase difference between the CCD_VD and the TFT_VD detected by the phase comparator 142 is input to the cycle controller 143. The period controller 143 compares the phase difference input from the phase comparator 142 with the target phase difference, and controls the period of the imaging clock so that the phase difference approaches the target phase difference. For example, when the phase difference input from the phase comparator 142 is larger than the target phase difference, the period of the CCD_VD in the next frame is extended by the amount of deviation from the target phase difference, as in the first embodiment. In this case, a clock selection signal for setting the imaging clock during the invalid period to the imaging clock after frequency division is input to the selector 144. In response to this, the selector 144 selects the divided imaging clock. Therefore, the period of the imaging synchronization signal within this period is longer than the period of the imaging synchronization signal within the other period.

  As described above, in the second embodiment, the period of the imaging clock for generating the imaging synchronization signal is the time width set so that the phase difference between the CCD_VD and the TFT_VD approaches the target phase difference. It is possible to make the frame rate of imaging and display coincide by controlling so that

  Here, the frequency divider / multiplier 141 is composed of at least one frequency divider and multiplier, but a plurality of frequency dividers and multipliers are provided so that a plurality of frequency divided clocks and frequency multiplied clocks can be generated. Anyway. By generating a plurality of divided clocks and multiplied clocks in this way, it is possible to improve the resolution of the period control of the imaging clock.

  Also in the second embodiment, the period of the display clock for generating the display synchronization signal may be controlled as in the first embodiment. A block diagram of the digital camera in this case is shown in FIG. FIG. 12 differs from FIG. 9 in that a display clock control unit 15 is provided instead of the imaging clock control unit 14.

  FIG. 13 shows the configuration of the display clock controller 15 corresponding to the modification shown in FIG. The display clock control unit 15 in FIG. 13 has substantially the same configuration as the imaging clock control unit 14 in FIG. 10, and includes a frequency divider / multiplier 151, a phase comparator 152, a period controller 153, and a selector 154. Composed. However, in this modification, the relationship of the cycle control in the cycle controller 153 is opposite to that of the cycle controller 143.

  Although the present invention has been described based on the above embodiments, the present invention is not limited to the above-described embodiments, and various modifications and applications are naturally possible within the scope of the gist of the present invention.

  Further, the above-described embodiments include various stages of the invention, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some configuration requirements are deleted from all the configuration requirements shown in the embodiment, the above-described problem can be solved, and this configuration requirement is deleted when the above-described effects can be obtained. The configuration can also be extracted as an invention.

It is a block diagram of the principal part of a digital camera provided with the synchronous signal generation apparatus which concerns on the 1st Embodiment of this invention. It is a timing chart at the time of live view display. It is a block diagram which shows the structure of the imaging synchronization signal generation part 3 in 1st Embodiment. It is a figure for demonstrating the concept of the period control of the synchronizing signal for imaging. It is a figure which shows the specific example of the period control of the vertical synchronizing signal CCD_VD. It is a figure shown about the outline of imaging operation in case the period control of vertical synchronizing signal CCD_VD is performed. It is a block diagram of the principal part of the digital camera in the modification of 1st Embodiment. It is a block diagram which shows the structure of the display synchronous signal generation part 12 in the modification of 1st Embodiment. It is a block diagram of the principal part of a digital camera provided with the synchronous signal generation apparatus which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the imaging clock control part 14 in 2nd Embodiment. 6 is a timing chart illustrating selection control of an imaging clock according to the second embodiment. It is a block diagram of the principal part of the digital camera in the modification of 2nd Embodiment. It is a block diagram which shows the structure of the display clock control part 15 in the modification of 2nd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Imaging device, 2 ... Timing generator (TG), 3 ... Imaging synchronous signal generation part, 4 ... Imaging clock generation part, 5 ... Imaging interface (I / F) part, 6 ... Data bus, 7 ... Memory controller, 8 ... Memory, 9 ... Image processing unit, 10 ... Display interface (I / F) unit, 11 ... Display unit, 12 ... Display synchronization signal generation unit, 13 ... Display clock generation unit, 14 ... Imaging clock control unit, 15 ... Display Clock control unit 31, 121 ... Horizontal counter, 32, 122 ... Vertical counter, 33, 123, 142, 152 ... Phase comparator, 34, 124, 143, 153 ... Period controller, 141, 151 ... Frequency division and multiplication , 144, 154 ... selector

Claims (19)

In a synchronization signal generation device having an imaging synchronization signal generation unit that generates an imaging synchronization signal for driving an imaging device and a display synchronization signal generation unit that generates a display synchronization signal for driving a display device,
The imaging synchronization signal generator is
A phase difference detector that detects a phase difference between the imaging synchronization signal and the display synchronization signal;
A cycle control unit that controls the cycle of the imaging synchronization signal based on the phase difference detected by the phase difference detection unit;
A synchronization signal generating device comprising:   The cycle control unit receives a target phase difference between the imaging synchronization signal and the display synchronization signal, and determines the phase difference between the imaging synchronization signal and the display synchronization signal as the target position. The synchronization signal generating apparatus according to claim 1, wherein a cycle of the imaging synchronization signal is controlled so as to approach a phase difference. The imaging synchronization signal generation unit includes a counter unit that counts an imaging clock for generating the imaging synchronization signal and generates the imaging synchronization signal,
The cycle control unit controls the operation of the counter unit to bring the phase difference between the imaging synchronization signal and the display synchronization signal closer to the target phase difference. The synchronization signal generator according to claim 1. The imaging synchronization signal generation unit includes an imaging clock control unit that controls a cycle of an imaging clock for generating the imaging synchronization signal,
The cycle control unit controls the operation of the imaging clock control unit to bring the phase difference between the imaging synchronization signal and the display synchronization signal closer to the target phase difference. Item 3. The synchronization signal generation device according to Item 2. The imaging clock controller is
A frequency division and multiplication unit for dividing or multiplying the imaging clock;
A switching unit that selectively switches and outputs the imaging clock and the divided or multiplied imaging clock so as to have a time width set to bring the phase difference closer to the target phase difference;
The synchronization signal generating apparatus according to claim 4, further comprising:   The target phase difference is set based on a time from when the image pickup device acquires the image pickup signal to when an image based on the image pickup signal is displayed on the display device. The synchronization signal generating device described.   The synchronization signal generation apparatus according to claim 3, wherein the cycle control unit controls a cycle of an imaging synchronization signal of an arbitrary horizontal line.   The synchronization signal generating apparatus according to claim 4, wherein the cycle control unit controls a cycle of an imaging clock for an arbitrary horizontal line.   The synchronization signal generating apparatus according to claim 3, wherein the cycle control unit controls the cycle of the synchronization signal for imaging the horizontal line during the blanking period.   The synchronization signal generating apparatus according to claim 4, wherein the cycle control unit controls a cycle of an imaging clock for a horizontal line during a blanking period.   The synchronization signal generating apparatus according to claim 1, wherein an imaging clock for generating the imaging synchronization signal and a display clock for generating the display synchronization signal are asynchronous. In a synchronization signal generation device having an imaging synchronization signal generation unit that generates an imaging synchronization signal for driving an imaging device and a display synchronization signal generation unit that generates a display synchronization signal for driving a display device,
The display synchronization signal generator is
A phase difference detector that detects a phase difference between the imaging synchronization signal and the display synchronization signal;
A cycle control unit that controls the cycle of the display synchronization signal based on the phase difference detected by the phase difference detection unit;
A synchronization signal generating device comprising:   The cycle control unit receives a target phase difference between the imaging synchronization signal and the display synchronization signal, and determines the phase difference between the imaging synchronization signal and the display synchronization signal as the target position. The synchronization signal generating apparatus according to claim 12, wherein a cycle of the display synchronization signal is controlled so as to approach a phase difference. The display synchronization signal generation unit includes a counter unit that counts a display clock for generating the display synchronization signal and generates the display synchronization signal,
The cycle control unit controls the operation of the counter unit to bring the phase difference between the imaging synchronization signal and the display synchronization signal closer to the target phase difference. The synchronization signal generator according to claim 1. The display synchronization signal generation unit includes a display clock control unit that controls a cycle of a display clock for generating the display synchronization signal,
The cycle control unit controls the operation of the display clock control unit to bring the phase difference between the imaging synchronization signal and the display synchronization signal closer to the target phase difference. Item 14. The synchronization signal generation device according to Item 13. The display clock control unit
A frequency division and multiplication unit for dividing or multiplying the display clock;
A switching unit that selectively switches and outputs the display clock and the divided or multiplied display clock so as to have a time width determined to bring the phase difference closer to the target phase difference;
The synchronization signal generation device according to claim 15, comprising:   13. The synchronization signal generation apparatus according to claim 12, wherein an imaging clock for generating the imaging synchronization signal and a display clock for generating the display synchronization signal are asynchronous. An image sensor that captures an image of a subject and obtains an image signal;
An imaging synchronization signal generating unit that generates an imaging synchronization signal for driving the imaging element;
An image processing unit that obtains image data by processing an imaging signal acquired by the imaging element;
A display device for displaying an image based on the image data obtained in the image processing unit;
A display synchronization signal generating unit that generates a display synchronization signal for driving the display device, which is a signal asynchronous with the imaging synchronization signal;
A phase difference detector that detects a phase difference between the imaging synchronization signal and the display synchronization signal;
A cycle control unit that controls a cycle of the imaging synchronization signal and the display synchronization signal so that the phase difference detected by the phase difference detection unit approaches a target phase difference;
A digital camera comprising: A synchronization signal generating method for generating an imaging synchronization signal for driving an imaging device and a display synchronization signal for driving the display device that is asynchronous with the imaging synchronization signal,
Detecting a phase difference between the imaging synchronization signal and the display synchronization signal;
Controlling the period of either the imaging synchronization signal and the display synchronization signal so that the detected phase difference approaches the target phase difference;
A method of generating a synchronization signal.

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