JP2000267619A - Liquid crystal projector device with image pickup camera - Google Patents

Abstract

PROBLEM TO BE SOLVED: To apply video dots units of information picked up by a camera to dots units of a liquid crystal projector, and make it possible to display a high resolution video on a liquid crystal panel by providing this liquid crystal projector with a maximum value selecting means, etc., for selecting a maximum value of cumulative summation data stored in each register of a register means. SOLUTION: A write limiting circuit 17 is activated to transfer and store accumulated data of a detector to/in registers 38a-38n by an enable signal from a comparison circuit 19. From the accumulated value data stored in these plural registers 38a-38n, a maximum value selecting circuit 39 selects the maximum value of the accumulated data, and decides a delay amount in a delay circuit 42 of a clock generator from a selector 45 via a control circuit 46 by using the phase value of this maximum value. Namely, the phase having the maximum accumulated value data selected by the maximum value selecting circuit 39 is the phase of a maximum sampling clock for sampling the video signals generated by a camera for paintings and calligraphy 11 and optimally applying them to the effective pixels in a liquid crystal panel 16 of the projector.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal projector with an image pickup camera, which can reproduce and display a video signal picked up by a high resolution image pickup camera on a liquid crystal display element having the same resolution as the image pickup camera. .

[0002]

2. Description of the Related Art Conventionally, in lectures and various presentations,
The material itself created by the speaker is imaged with a camera,
A projector with a document imaging camera for enlarging and displaying the image based on a video signal captured and generated by the camera has come to be used.

A document imaging camera (hereinafter, referred to as a document camera) used in this projector with a document imaging camera is reduced in size and weight by using a high-resolution solid-state imaging device, and the projector is also a high-resolution liquid crystal display device. It is formed using. For this reason, the information of the image in the unit of pixel dot imaged by the document camera using the high-resolution solid-state image pickup device is appropriately applied to each pixel dot unit of the liquid crystal display device of the high-resolution projector, so that the document camera It is possible to reproduce and display the high-resolution image captured by the projector as a high-resolution image on the projector.

[0004] Therefore, it is necessary to accurately adjust the phase of a sampling clock for applying a video signal generated by a document camera to each pixel dot of a liquid crystal display element. In particular, the solid-state imaging device of a document camera has 1024 × 768 pixels.
When a high-resolution element called XGA is used and a liquid crystal display element of the projector uses an element having the same XGA high resolution, video information captured by a document camera is appropriately reproduced and displayed by the projector. By that, XGA
A video with a resolution can be displayed. If the projector does not properly reproduce and display the image information of the document camera, an image having a resolution lower than the XGA resolution will be displayed.

For this reason, the liquid crystal projector is required to strictly adjust the phase of a clock for sampling video information generated by a document camera.

The phase adjustment of the sampling clock in the liquid crystal projector will be described with reference to FIG.

[0007] An analog video signal captured and generated by a document camera (not shown) is supplied to an input terminal 31. The video signal supplied to the input terminal 31 is supplied to the detection circuit 32. The detection circuit 32 includes an analog / digital converter (hereinafter, referred to as an AD converter) 33, a one-pixel delay unit 34, a subtractor 35, an absolute value unit 36, and an accumulator 37. The AD converter 33 is connected to the input terminal 31.
Is sampled by a clock signal described later and converted into a digital video signal, and a plurality of pixel data are generated by this sampling. The pixel data of the digital video signal sampled and generated by the AD converter 33 is delayed by one pixel by a one-pixel delay unit 34, and the delayed pixel data and the non-delayed pixel data are supplied to a subtractor 35. Then, subtraction processing of pixel data of one pixel before and after is performed. This subtractor 3
The output of 5 is supplied to an absolute value unit 36, and the absolute value of the subtraction value is extracted. The absolute value extracted by this absolute value device 36 is
The accumulator 37 performs cumulative addition for one screen or one horizontal period.
The data cumulatively added by the accumulator 37 is stored in a plurality of registers 38a to 38n. This register 38a
The maximum value selection circuit 39 is connected to the output side of the .about.38n.

On the other hand, a horizontal synchronizing signal is supplied to a terminal 41. The horizontal synchronization signal input to the terminal 41 is supplied to one reference of the PLL circuit 43 via the delay circuit 42. The PLL circuit 43 includes the delay circuit 4
A sampling clock signal is generated based on the horizontal synchronizing signal delayed by 2 and supplied to the AD converter 33. The sampling clock signal from the PLL circuit 43 is frequency-divided by a frequency divider 44 to generate a PLL clock.
The phase is supplied to the other reference of the circuit 43 to control the phase of the sampling clock signal. The delay circuit 42
Is supplied with a signal from the selector 45. The selector 45 controls the amount of delay in the delay circuit 42 under the control of the control circuit 46. This delay amount is determined using the output of the maximum value selection circuit 39.

The video signal sampled by the AD converter 33 is supplied from an output terminal 47 to a liquid crystal display device through various video signal processing circuits.

[0010] The sampling phase adjusting device having such a configuration makes it possible to control the phase of the sampling clock and find the optimum phase. That is, when the operation of the sampling device is started, the control circuit 46 controls the delay circuit 42 via the selector 45,
The delay amount is changed little by little, and a temporary delay amount is set. For example, a sampling clock signal having a phase t0 with a delay amount of 0 as an initial delay amount is generated. This delay circuit 42
Under the control of the control circuit 46, the delay amount can be switched to N stages, and the time corresponding to the reproduction clock cycle obtained from the horizontal synchronizing signal (or a longer time) is set at intervals of about 1 / N. The phase of the clock signal can be sequentially changed from t0 to tn by the signal from the selector 45.

When the sampling device starts up, first, the delay amount is set to the initial value phase t0 of zero, and the PLL circuit 43 generates a clock signal of the initial phase. As a result, the AD converter 33 outputs the phase t0.
The analog video signal is sampled at the timing of
It is converted to a digital video signal. The sampled and generated digital video signal is supplied to a one-pixel delay unit 3.
4, the delayed pixel data and the non-delayed pixel data are subtracted by the subtractor 35, and the absolute value of the difference is extracted by the absolute value device 36. The accumulator 37 accumulatively adds the absolute value of the difference from the absolute value device 36 for one screen or one horizontal scanning period, and stores the result in the register 38a.

Next, under the control of the control circuit 46, the amount of delay of the delay circuit 42 is changed and temporarily set to the phase t1, and the result of the detection circuit 32 is similarly stored in the register 38b. As described above, the process of sequentially changing the delay amount of the delay circuit 42 from the control circuit 46 through the selector 45
And the Nth result is stored in the register 38n.
The accumulated addition value data stored in the registers 38a to 38n is read into the maximum value selection circuit 39, and the respective registers 38a to 38n.
The accumulated addition value data of a to 38n is compared. On the basis of the data stored in each of the registers 38a to 38n, the maximum value selection circuit 39 obtains the phase at which the accumulated data becomes maximum based on the data of each register, and calculates the delay amount corresponding to the phase by the control circuit 46. Inform Thereby, the control circuit 4
6 determines that the phase when the accumulated data becomes the maximum is the optimum phase value of the sampling, and controls the selector 45 to determine the delay amount of the delay circuit 42.

That is, when the sampling device is started, the delay amount of the delay circuit 42 is temporarily set to 0, and then the delay amount of the delay circuit 42 is sequentially displaced, so that the delay amount of the delay circuit 42 is An absolute value of a difference from a video signal delayed by a pixel is detected, a delay amount at which the accumulated value is maximized is obtained, and a sampling clock signal having an optimal phase is obtained.

Using the sampling phase adjusting device having such a configuration and operation, a video signal imaged and generated by the XGA-compatible document camera is sampled, and as shown in FIG. Are controlled so that the phase points coincide with each other. If, for example, FIG.
As shown in (b), if the phase points of the video signal and the sampling clock signal do not match, the resolution of the video displayed on the projector deteriorates.

The phase adjustment of the sampling clock is performed by
When a document subject having a resolution suitable for the resolution XGA of the document camera is imaged, or when the focus adjustment of the camera is qualified, it is possible to set an appropriate phase of a clock for sampling a video signal. .

However, based on a video signal (shown in FIG. 5 (a)) generated by imaging a document subject having a resolution lower than that of the XGA with a document camera having the XGA resolution, the sampling phase adjusting device controls the sampling clock. When the phase adjustment is performed, the phase is adjusted at the rising and falling points from the white and black levels of the video signal in FIG.
The clock phase point shown in FIG. The phase point of this sampling clock is shown in FIG.
There is a difference from the sampling clock phase adjustment point based on the XGA resolution video signal shown in FIG. Therefore, precise phase adjustment of the sampling clock cannot be performed. For this reason, when a document subject having a resolution lower than that of the XGA is captured and generated by a document camera having the XGA resolution, a sampling phase adjustment device of the XGA projector adjusts the phase of the sampling clock to reproduce and display the image.
The image is displayed with the phase of the sampling clock shifted, and the image of the XGA resolution of the liquid crystal display element cannot be displayed.

Further, when the phase of the sampling clock is adjusted based on a video signal captured in a state where the focus adjustment of the XGA resolution document camera is inappropriate, the XGA resolution
This results in the same result as capturing an object having a resolution lower than the resolution. Even if the focus of the camera is adjusted again after the phase of the sampling clock is adjusted, an image having a resolution lower than the XGA resolution is reproduced and displayed on the liquid crystal projector.

[0018]

In a projector having a high-resolution imaging camera and a liquid crystal display element having the same resolution as that of the imaging camera, an image of a subject having a resolution lower than that of the imaging camera can be taken.
Alternatively, by setting the phase of a clock for sampling a video signal with a sampling phase adjustment device provided in the projector, based on a generated video signal, such as capturing an image of a subject in an inappropriate state of focus adjustment of an imaging camera, There is a problem in that an inappropriate phase is set, video information in units of dots captured by the imaging camera does not match with the dots of the projector, and a low-resolution video is reproduced and displayed.

According to the present invention, a clock for sampling a video signal is set to an optimum phase without being affected by the resolution characteristics of a subject document and the focus adjustment conditions of a camera.
It is an object of the present invention to provide a liquid crystal projector device with an imaging camera that can adapt video information in dot units captured by a camera to dot units of a liquid crystal display element of a projector.

[0020]

According to the present invention, there is provided a projector apparatus using a liquid crystal display element for reproducing and displaying a video signal captured and generated by an image capturing camera, wherein a camera means for capturing a subject and generating a video signal; Pseudo signal multiplexing means for multiplexing a pseudo signal with a video signal imaged and generated by a camera means, and a plurality of pixel data generated by sampling a video signal multiplexed with the pseudo signal by the pseudo signal multiplexing means with a predetermined clock signal A sampling unit; a detection unit configured to process pixel data from the sampling unit to extract a difference between preceding and succeeding pixel data, accumulatively add the absolute value of the difference for a predetermined period of time, and output the clock; A sampling clock including a phase varying means for generating a signal and sequentially varying a phase of the clock signal by a predetermined amount. Of the clock signal generating means and the cumulatively added data by the detecting means when the phase of the clock signal is sequentially shifted by the phase variable means, using the maximum value for each phase shift of the cumulatively added data of the pseudo signal component. Control means for controlling the phase variable means to output a clock signal output from the sampling clock generation means in a phase state corresponding to the maximum value. is there.

The pseudo signal multiplexed by the pseudo signal multiplexing means of the liquid crystal projector device with an imaging camera of the present invention is multiplexed in one or a plurality of horizontal scanning periods of a vertical blanking period of the video signal.

The pseudo signal multiplexed by the pseudo signal multiplexing means of the liquid crystal projector device with the imaging camera of the present invention is a black and white switching signal in the unit of the highest dot clock imaged by the camera means.

Further, the control means of the liquid crystal projector device with the imaging camera of the present invention is characterized in that, among the data cumulatively added by the detection means when the phase of the clock signal is sequentially shifted by the phase variable means, A write restricting means for extracting and selecting only the cumulative addition data of the signal components, and a plurality of storing the cumulative addition data of the pseudo signal component from the detecting means extracted and selected by the write restricting means for each phase displacement And maximum value selecting means for selecting the maximum value of the cumulative addition data stored in each register of the register means. The phase variable is responsive to a result selected by the maximum value selecting means. It is characterized by controlling the means.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of a liquid crystal projector device with an imaging camera according to the present invention. The same parts as those in FIG. 3 are denoted by the same reference numerals, and detailed description is omitted.

The document camera 11 of FIG. 1 and the liquid crystal panel 16 which is a liquid crystal display element for a projector have the same resolution and a high resolution having an effective number of pixels of XGA is used.

The liquid crystal projector with an imaging camera shown in FIG. 1 supplies an analog video signal imaged and generated by a document camera 11 to a signal multiplexing circuit 12, and
The horizontal and vertical synchronizing signals from 1 are supplied to a pseudo signal generating circuit 3. The pseudo signal generation circuit 13 generates a pseudo signal in which a video signal of a white level and a black level is switched for each dot clock of a pixel of a solid-state imaging device (not shown) of the document camera 11, and divides the pseudo signal into a signal multiplexing circuit. 12
Then, as shown in FIG. 2, the signal is multiplexed on a horizontal scanning line having a vertical blanking period. The analog video signal in which the pseudo signal is multiplexed is converted by the AD converter 33 into a digital video signal.

The analog video signal multiplexed with the pseudo signal supplied to the AD converter 33 is supplied to a delay circuit 42,
The signal is sampled by a sampling clock from a clock generator composed of a PLL circuit 43 and a frequency divider 44 and is converted into a digital video signal.
4 is supplied. The video signal processing circuit 14 performs processes such as color demodulation, γ correction, digital / analog conversion, and polarity inversion based on the digital video signal, and supplies the processed liquid crystal panel 16 to the liquid crystal panel 16. A timing signal generation circuit 15 is connected to the liquid crystal panel 16 and controls the driving of the liquid crystal panel based on horizontal and vertical synchronization signals from the document camera 11.

The digital video signal converted by the AD converter 33 is used to accumulate the absolute value obtained by subtraction processing by a detector comprising a one-pixel delay unit 34, a subtractor 35, an absolute value unit 36, and an accumulator 37. The data is stored in a plurality of registers 38a-3
8n.

The accumulator 37 of the detector and the register 3
8, a write restricting circuit 17 is arranged. The write restricting circuit 17 has a line count data from a line counter 18 for counting horizontal scanning lines, based on a vertical synchronizing signal of a video signal generated by the document camera 11, and a horizontal signal obtained by multiplexing the pseudo signal. A comparison circuit 19 for comparing the reference value of the scanning line with the reference value is connected. The comparison circuit 19 enables the write limiting circuit 17 when the reference value of the horizontal scanning line on which the pseudo signal is multiplexed matches the value of the horizontal scanning line counted by the line counter 18. Supply signal. Thereby, the write limiting circuit 17 stores and transfers the data accumulated by the accumulator 37 of the detector to the register 38 during the period when the enable signal is supplied from the comparison circuit 19, and While the enable signal is not supplied, the accumulation data of the accumulator 37 is not stored and transferred to the register 38.

That is, the write limiting circuit 17 reads out and transfers only the accumulated data in the horizontal scanning line period in which the pseudo signal is multiplexed from the data accumulated by the accumulator 3 of the detector, and Restriction control is performed so that the data is stored in the register 38.

The write limiting circuit 17, line counter 18, comparison circuit 19, register 38, maximum value selection circuit 39, selector 45, and control circuit 46 are formed by a microcomputer.

Although not shown, the liquid crystal panel 16 is provided with an optical means for projecting transmitted light to the liquid crystal panel 16, a lens for projecting image light transmitted through the liquid crystal panel, and a screen.

The operation of adjusting the phase of the sampling clock generated by the clock generator of the liquid crystal projector with the imaging camera having such a configuration will be described.

When a video signal is fetched from the document camera 11 and the operation of the liquid crystal projector is started, the control circuit 4
From 6, the delay circuit 42 of the clock generator is controlled via the selector 45, and a sampling clock signal of a phase t0 having a delay amount of zero is generated as an initial delay amount by gradually changing the delay amount. The delay circuit 42 can switch the delay amount to N stages under the control of the control circuit 6,
The time corresponding to the reproduction clock cycle obtained from the horizontal synchronization signal is delayed at an interval of 1 / N. Thus, the A / D converter 33 outputs 1 / N supplied from the clock generator.
The video signal is sampled with a sampling clock signal whose phase is changed at intervals of. Based on the sampling clock signal changed by 1 / N, the AD converter 3
The digital video signal generated by sampling at
The detector becomes data obtained by accumulating the subtraction absolute values for each pixel, and the line counter 18 and the comparison circuit 19 detect the period of the horizontal scanning line of the pseudo signal multiplexed in the horizontal scanning period of the vertical retrace period. , And supplies an enable signal to the write control circuit 17. This write restricting circuit 17
According to the enable signal from the comparison circuit 19, the accumulated data of the detector is transferred to and stored in the register 38.

That is, in the register 38, the accumulated value data of the pseudo signal multiplexed in the vertical blanking period with the sampling clock signal of the initial phase from the clock generator is stored in the register 38a. The accumulated value data of the pseudo signal when the 1 / N phase of the sampling clock signal is changed is stored in the register 38b, and thereafter the phase of the sampling clock signal is sequentially changed N times by 1 / N, and the N The accumulated value data of the second phase is stored in the register 38n. The maximum value of the accumulated data is selected by the maximum value selection circuit 39 from the accumulated value data stored in the plurality of registers 38a to 38n, and the selector 45 is selected via the control circuit 46 by using the phase value of the maximum value. , The delay amount of the delay circuit 42 of the clock generator is determined.

That is, the phase having the maximum accumulated value data selected by the maximum value selection circuit 39 is determined by the phase of the document camera 11.
The video signal generated in step (1) is sampled and becomes the phase of an optimal sampling clock for optimally assigning it to the effective pixels of the liquid crystal panel 16 of the projector.

That is, a pseudo signal in which the black and white level is switched in dot clock units at the highest frequency at which the document camera 11 can capture an image is multiplexed in a horizontal scanning period having a vertical blanking period of a video signal, and based on the multiplexed pseudo signal. By selecting and setting the optimal phase of the sampling clock signal, the video information corresponding to each pixel captured by the document camera 11 is output from the projector without being restricted by the resolution of the subject captured by the document camera or the state of focus adjustment of the camera. The image can be appropriately applied to each pixel of the liquid crystal panel 16, and a high-resolution image can be displayed.

In the description of the above embodiment, the pseudo signal multiplexed in the horizontal scanning period of the vertical blanking period is one horizontal scanning line. However, the pseudo signal is applied to a plurality of horizontal scanning lines in the vertical blanking period. Obviously, the multiplexing makes the phase adjustment of the sampling clock signal more optimal.

[0039]

As described above, according to the present invention, when a video signal captured by a high-resolution imaging camera is reproduced and displayed by a high-resolution liquid crystal projector, regardless of the resolution of the subject and the condition of focus adjustment of the imaging camera, The image information in dot units captured by the camera can be applied to the dot units of the liquid crystal projector, and this has the effect that a high-resolution image can be reliably displayed on the liquid crystal projector.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment of a liquid crystal projector device with an imaging camera according to the present invention.

FIG. 2 is a waveform diagram of a pseudo signal used in the liquid crystal projector device with an imaging camera according to the present invention.

FIG. 3 is a block diagram showing a circuit configuration of a conventional liquid crystal projector.

FIG. 4 is a waveform chart illustrating the operation of a conventional liquid crystal projector.

FIG. 5 is a waveform chart for explaining a problem of the conventional liquid crystal projector.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Document camera 12 ... Signal multiplexing circuit 13 ... Pseudo signal generation circuit 14 ... Video signal processing circuit 15 ... Timing signal generation circuit 16 ... Liquid crystal panel 17 ... Write restriction circuit 18 ... Line counter 19 ... Comparison circuit 33 ... Analog / digital Converter 34 One-pixel delay unit 35 Subtractor 36 Absolute value unit 37 Accumulator 38 Register 39 Maximum value selection circuit 42 Delay circuit 43 PLL circuit 44 Frequency divider 45 Selector 46 Control circuit .

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H088 EA12 HA06 MA01 MA03 5C022 AA00 5C080 AA10 BB05 DD07 DD09 EE02 FF09 GG07 GG09 GG10 GG12 JJ02 JJ04 5C082 AA13 AA27 BA02 BC03 CA85 CB01 DA76 MM01 MM10

Claims (4)

[Claims] 1. A projector device using a liquid crystal display element for reproducing and displaying a video signal captured and generated by an imaging camera, a camera means for capturing an image of a subject and generating a video signal, and a video signal captured and generated by the camera means. Pseudo-signal multiplexing means for multiplexing pseudo-signals, sampling means for sampling a video signal multiplexed with pseudo-signals by the pseudo-signal multiplexing means with a predetermined clock signal to generate a plurality of pixel data, Processing the generated pixel data to extract the difference between the preceding and following pixel data, accumulating and adding the absolute value of the difference for a predetermined period and outputting the detected signal, and generating a clock signal to be supplied to the sampling means, Sampling clock generation means including phase variable means for sequentially varying the phase of the clock signal by a predetermined amount; When the phase of the clock signal is sequentially displaced by the phase varying means, the maximum value for each phase displacement of the cumulative addition data of the pseudo signal component is used for the phase variable means, And a control unit for setting the clock signal output from the sampling clock generation unit to be output in a phase state corresponding to the maximum value. 2. The camera according to claim 1, wherein the pseudo signal multiplexed by the pseudo signal multiplexing unit is multiplexed in one or a plurality of horizontal scanning periods of a vertical blanking period of the video signal. Liquid crystal projector device. 3. The camera with an imaging camera according to claim 1, wherein the pseudo signal multiplexed by the pseudo signal multiplexing unit is a black-and-white switching signal in the unit of the highest dot clock imaged by the camera unit. Liquid crystal projector device. 4. The control means extracts and selects only the cumulative addition data of the pseudo signal component from the data cumulatively added by the detection means when the phase of the clock signal is sequentially shifted by the phase variable means. Write limiting means, a plurality of register means for respectively storing the cumulative addition data of the pseudo signal components from the detecting means extracted and selected by the write limiting means for each phase displacement, A maximum value selecting means for selecting a maximum value of the accumulated addition data stored in the register, wherein the variable phase means is controlled in response to a result selected by the maximum value selecting means. Item 4. A liquid crystal projector device with an imaging camera according to items 1 to 3.