JP4292963B2 - Imaging device - Google Patents

Description

  The present invention relates to an imaging apparatus effective for use in a video camera capable of taking a still image.

  In recent years, video cameras equipped with a still image shooting function have been released by various companies. Most of the still image pixels exceed 1 million pixels, and some of them exceed 3 million pixels. An imaging device used in these video cameras will be described.

  FIG. 10 is a diagram showing a system configuration of a conventional imaging apparatus. First, the operation during movie shooting will be described. Light incident through a lens (not shown) and a diaphragm (not shown) is photoelectrically converted by the CCD 1 and output as a video signal. For convenience of explanation, the CCD 1 is described as an interlaced CCD here. The selection means 3 selects the output of the CCD 1 at the time of moving image shooting and inputs it to the camera signal processing means 4. The camera signal processing means 4 performs a series of camera signal processing such as white balance processing, γ correction, generation of luminance signals and color difference signals, and edge enhancement on the input signal (complementary color or primary color data). The pixel number conversion means 5 converts the output of the camera signal processing means 4 into the number of pixels that can be displayed by a television system such as NTSC or PAL, and outputs it. The selection unit 8 selects the output of the pixel number conversion unit 5 and outputs it as a camera output during moving image shooting.

  Next, operations during still image shooting will be described. When a still image shooting button (not shown) is pressed, the diaphragm (not shown) is closed, and an interlaced video signal for two fields obtained as a result of photoelectric conversion by the CCD 1 is input to the memory means 2. . The memory means 2 has a capacity capable of storing video signals for two fields. The memory means 2 converts the input 2-field interlaced video signal into a 1-frame progressive video signal and outputs it. The selection means 3 selects the output of the memory means 2 and inputs it to the camera signal processing means 4 during still image shooting. The camera signal processing means 4 performs a series of camera signal processing such as white balance processing, γ correction, generation of luminance signals and color difference signals, and edge enhancement on the input signal (complementary color or primary color data). The selection means 8 selects the output of the camera signal processing means 4 and outputs it as a camera output during still image shooting.

When a progressive CCD is used as the CCD 1, the memory means 2 and the selection means 3 can be omitted as shown in FIG. However, since the output of the pixel number converting means 5 becomes a progressive video signal, when outputting an interlaced video signal, a memory means 9 for converting the progressive video signal into an interlaced video signal is required separately.
JP-A-5-336498

  The problem to be solved is that a conventional imaging device using an interlaced CCD cannot perform still image shooting using all CCD output pixels during moving image shooting. In FIG. 10, since the CCD 1 is an interlaced CCD, even if the outputs of the camera signal processing means 4 and the pixel number conversion means 5 are output simultaneously, the output of the camera signal processing means 4 is an interlaced signal, so the number of still picture vertical pixels Becomes 1/2 of the number of CCD output pixels, and the still image vertical resolution deteriorates to 1/2.

  Second, in a conventional imaging device using an interlaced CCD, if still image shooting using all CCD output pixels is performed during moving image shooting, the circuit scale, cost, and power consumption increase. For example, as shown in FIG. 12, two camera signal processing means 4 and 10 are provided, one for processing an interlaced video signal output from the CCD 1 and the other for processing a progressive video signal output from the memory means 2 for camera signal processing. The interlaced video signal output of the means 4 is output as a moving image through the pixel number converting means 5, and the progressive video signal output of the camera signal processing means 10 is output as a still image.

  Thirdly, in a conventional imaging apparatus using a progressive CCD, if still image shooting using all CCD output pixels is performed during moving image shooting, cost and power increase. In this case, a circuit configuration similar to that shown in FIG. 11 is sufficient, but in general, the progressive CCD is expensive, and if the number of pixels is the same, the driving frequency is twice that of the interlaced CCD, resulting in an increase in power consumption.

  Since the present invention is configured to process a still image during a vertical blanking period of a video signal, the most important feature is that still image shooting is possible during moving image shooting.

  The image pickup apparatus according to the present invention processes moving images and still images in a time-sharing manner, thereby enabling still image shooting using all CCD output pixels during moving image shooting using an interlaced CCD, which affects moving image processing. By taking as long a still image processing period as possible within the range, there is an advantage that the still image processing speed can be improved as compared with the case where still image processing is simply performed within the vertical blanking period.

  According to the first and second aspects of the present invention, the imaging device and the output signal of the imaging device are stored in synchronization with the first synchronization signal, and the stored contents are output in synchronization with the second synchronization signal. First and second storage means, IP conversion means for converting an interlaced video signal output from the second storage means into a progressive video signal, an output signal of the first storage means or the IP conversion means Selecting means for selecting one of the output signals, a camera signal processing means for creating a luminance signal and a color difference signal from the output signal of the selection means, and a predetermined number of pixels of the output signal of the camera signal processing means A pixel number converting means for converting to the number of pixels, a pixel number converting means for storing the output signal in synchronism with the second synchronizing signal, and outputting the stored contents in synchronism with the third synchronizing signal. Storage means, Synchronization signal generating means for outputting control signals for controlling the first to third synchronization signals and the selection means, wherein the second synchronization signal has a vertical blanking period in the first and third synchronization signals. The vertical scanning period of the synchronization signal is set to be longer than the vertical blanking period, and the vertical scanning period of the second synchronization signal is divided into first and second vertical scanning periods. The output signal of the first storage means is selected during a scanning period, the output signal of the IP conversion means is selected during the second vertical scanning period, and the pixel number conversion in the first vertical scanning period is controlled. The output signal of the third storage means storing the output signal of the means is a moving image output signal, and the output signal of the camera signal processing means in the second vertical scanning period is a still image output signal. , This allows for still image shooting during moving image shooting, to achieve a purpose of improving as much as possible still image processing speed.

  Hereinafter, an imaging apparatus according to an embodiment of the present invention will be described. FIG. 1 shows the configuration of the present invention.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of an imaging apparatus of the present invention.

  In the figure, reference numeral 1 denotes a CCD which is an image sensor, and an interlaced CCD is used in this embodiment. Reference numerals 2 and 3 denote first and second memory means for storing the video signal from the CCD 1 which are controlled by a synchronizing signal from a synchronizing signal generating means 9 which will be described later. Reference numeral 4 denotes an interlaced video signal from the second memory means 3. The IP conversion means 5 for converting from the system to the progressive system and outputting it is a selection means for switching between the output of the first memory means 2 and the output of the IP conversion means 4, and from the first memory means 2 at the time of moving image shooting. The output is selected, and the output from the IP conversion means 4 is selected during still image shooting. 6 is a camera signal processing means for performing various signal processing such as gamma correction on the video signal selected by the selection means 5, and 7 is capable of displaying the video signal from the camera signal processing means 6 on a display means (not shown). Pixel number conversion means for converting to the number of pixels, 8 is a third memory for storing the video signal from the pixel number conversion means 7, and 9 is first and second synchronization with the first and second memory means 2 and 3. A synchronizing signal generating means for outputting a signal and outputting the second and third synchronizing signals to the third memory means 8.

  The operation of the imaging apparatus of the present embodiment configured as described above will be described below.

  First, the operation at the time of moving image shooting will be described. Light incident through a lens (not shown) and a diaphragm (not shown) is photoelectrically converted by the CCD 1 and output as a video signal. Here, the CCD 1 is an interlaced CCD. The output signal of the CCD 1 is input to the first memory means 2 in synchronization with the first synchronization signal output from the synchronization signal generating means 9. Data is read from the first memory means 2 in synchronization with the second synchronization signal output from the synchronization signal generating means 9 and input to the selection means 5. The selection means 5 selects the output of the first memory means 2 and inputs it to the camera signal processing means 6 during moving image shooting. The camera signal processing means 6 performs a series of camera signal processing such as white balance processing, γ correction, generation of luminance signals and color difference signals, and edge enhancement on the input signal (complementary color or primary color data). The pixel number conversion means 7 converts the output of the camera signal processing means 6 into the number of pixels that can be displayed by a television system such as NTSC or PAL, and outputs it. The third memory means 8 inputs the output signal of the pixel number converting means 7 in synchronism with the second synchronizing signal output from the synchronizing signal generating means 9, and is also output from the synchronizing signal generating means 9. Is output in synchronization with the synchronization signal.

  Next, the operation during still image shooting will be described with reference to FIG. FIG. 2 is a diagram showing the timing at the time of still image shooting. (1) to (4) are numbers indicating fields. As shown in the figure, when a still image shooting button (not shown) is pressed at a certain timing, interlaces of four consecutive fields shot as moving images from the CCD 1 during the subsequent fields (1) to (4). Video signals A1, B1, A2, and B2 are output. At this time, when the aperture is closed as in conventional still image shooting, the CCD 1 is not exposed, the output signal is interrupted, and the moving image shooting is adversely affected. Therefore, control for closing the aperture (not shown) is not performed.

The interlaced video signals A 1, B 1, A 2 and B 2 are input to the second memory means 3 in synchronization with the first synchronization signal output from the synchronization signal generating means 9. The second memory means 3 has a capacity capable of storing video signals for four fields. In the period of the field (4), the interlaced video signals A1, B1, A2 of three consecutive fields are simultaneously outputted from the second memory means 3 in synchronism with the second synchronizing signal output from the synchronizing signal generating means 9. Is output and input to the IP conversion means 4. The IP conversion means 4 detects the movement in the screen from the signals A1 and A2, and B1 and B2 having the same spatial position. If it is determined that there is no movement, a progressive signal is created from A1 and B1, and there is movement. If it is determined, a pseudo-progressive signal is created and output from B1 and a signal B1 ^{* obtained} by interpolating B1 with a scanning line.

An operation image of the IP conversion means 4 is shown in FIG. FIG. 3A shows four consecutive fields. The image is a circular object across the screen. A difference between A1 and A2 and B1 and B2 is obtained, and a region where the absolute value of the difference exceeds a predetermined value is extracted, thereby detecting a motion region of the image. The motion region is as shown by the hatched portion in FIG. The stationary part (without hatching) of FIG. 3 (b) comprises a frame from A1 and B1 as shown in the left of FIG. 3 (c), and the moving part (with hatching) is B1 as shown in the right of FIG. A frame is constructed from B1 ^{* obtained} by vertically interpolating B1. As a result, the output of the IP conversion means 4 is obtained as a pseudo frame at the same time as B1 as shown in FIG.

  The selection means 5 selects the output of the IP conversion means 4 and inputs it to the camera signal processing means 6 during still image shooting. The camera signal processing means 6 performs a series of camera signal processing such as white balance processing, γ correction, creation of luminance and color difference signals, and edge enhancement on the input signal, and outputs it as a camera output.

  The synchronization signal generation means 9 generates the control signals for the selection means 3 as well as the write and read control signals for the first to third memory means 2, 3 and 8 as described above. Here, one field period is divided into a moving image signal processing period and a still image signal processing period, a synchronization signal generating means 9 generates a moving image / still image processing period determination signal, and the selection means 5 is switched using this determination signal. Thus, it is possible to execute the processing of the moving image and the still image in parallel. Hereinafter, the case of performing this control will be described.

  FIG. 4 shows the timing of the vertical synchronizing signal, which is an internal signal of the synchronizing signal generating means 9 at the time of moving image shooting, and the video signal. FIG. 4 illustrates the NTSC system as an example. The period of the vertical synchronizing signal is 262.5H (H: horizontal scanning period). On the other hand, since the video signal is 240H, a vertical blanking period of 22.5H is subtracted. Here, it is conceivable that the moving image processing period is 240H, the still image processing period is 22.5H, and still image processing is performed during the vertical blanking period. This is shown in FIG.

  FIG. 5 shows the timing at the time of simultaneous shooting of a moving image and a still image. As shown in the figure, 240H out of 262.5H is assigned to moving image processing and 20H is assigned to still image processing using the moving image / still image processing period discrimination signal output from the synchronization signal generating means 9. Still image data is divided into 20 lines. An example of this is shown in FIG. In the case of a still image composed of 960 lines as shown in FIG. 9A, 48 lines are processed every 20 lines, and one still image can be processed in a period of 48 fields. The still image signals divided and output from the camera signal processing means 6 are combined by a subsequent recording means (not shown) and recorded on a recording medium.

However, in the above operation, the still image is processed only by 20 lines in one field period, so that the processing time becomes longer than the case of processing only the still image. Since still image shooting cannot be performed during still image processing, the continuous shooting interval cannot be shortened, which affects system performance. Of course, the necessary processing time increases as the number of still image pixels increases, so this effect cannot be ignored when the number of still image pixels increases. Therefore, the horizontal synchronization signal period of the second synchronization signal is shortened and It is conceivable to perform synchronous conversion that lengthens the blanking period. This is shown below. FIG. 6 shows an example in which the vertical blanking period of the second synchronization signal is increased with respect to the first synchronization signal. FIG. 6 shows a case where an NTSC signal is processed with 13.5 MHz sampling. The first synchronization signal is assumed to have a general configuration of 1H = 858T (T: processing clock cycle), 1 field = 262.5H, and field frequency: 59.94 Hz. Here, if the second synchronizing signal has the same field frequency and the horizontal blanking period is shortened to 1H ^* = 770T (H ^* : horizontal scanning period), a configuration of 1 field = 292.5H ^* is considered. It is done. As a result, the vertical blanking period of the second synchronization signal can be made 30H longer than that of the first synchronization signal.

An image of the synchronous conversion is shown in FIG. The white portions in FIGS. 7A and 7B indicate the video valid period, which is horizontal 720T and vertical 240H in 13.5 MHz sampling. The gray part indicates the horizontal and vertical blanking periods. The first synchronization signal horizontal blanking period of (a) is 138T, and the vertical blanking period is 22.5H. If the horizontal blanking period is shortened to 50T and 1H ^* = 770T as in the second sync signal in (b) with the video valid period as it is, 1 field = 292.5H ^* and vertical blanking. The period can be 52.5H ^* . As a result, the moving image and still image processing timing can process 240 moving images and 50 still images in one field period as shown in FIG. Since the still image is divided by 50 lines, as shown in FIG. 9B, a still image consisting of 960 lines can be processed in 20 divisions, and the still image processing time can be shortened.

  However, since the moving image processed in synchronization with the second synchronization signal cannot be displayed on the NTSC monitor as it is, it is necessary to synchronize with the normal synchronization signal of NTSC. This is why the third memory means 8 in FIG. 1 needs to be synchronized with the third synchronization signal. In this case, the third synchronization signal may have the same configuration as the first synchronization signal shown in FIG.

  As described above, according to the present invention, a still image can be processed using a vertical blanking period in which no moving image processing is performed.

  In the above embodiment, the CCD 1 is described as a single CCD, but a plurality of CCDs may be used.

  In the above embodiment, the motion region is obtained from four consecutive fields in the processing performed by the IP conversion means 4, but the number of fields used for motion detection is not limited to four fields.

  In the above embodiment, the moving image processing period is 240H and the still image processing period is 20H or 50H. However, each processing period is not limited to this value.

  In the above-described embodiment, the description of the synchronous conversion has been described by taking 13.5 MHz sampling as an example. However, the sampling frequency is not limited to this, and the first synchronous signal and the third synchronous signal need to have the same configuration. Absent.

  As described above, according to the present invention, moving image shooting and still image shooting can be performed simultaneously. In addition, by taking advantage of the fact that still image processing is possible during the vertical blanking period, when switching to the movie shooting mode immediately after still image shooting of the conventional method that closes the aperture, it is not necessary to wait for completion of still image processing. It can also be applied to applications such as starting shooting and shortening the mode transition period.

The block diagram which shows the structure of the imaging device of this invention Timing diagram showing the timing of still image shooting Image diagram showing IP conversion operation image Timing chart showing the timing of movie shooting Timing diagram showing the timing of simultaneous video still image shooting Timing diagram showing an example of synchronous conversion Image diagram showing the image of synchronous conversion Timing diagram showing the timing of simultaneous video still image shooting using synchronous conversion Image diagram showing image of still image division processing Block diagram showing the configuration of a conventional imaging device Block diagram showing the configuration of a conventional imaging device Block diagram showing the configuration of a conventional imaging device

Explanation of symbols

1 CCD (imaging device)
2 First memory means (first storage means)
3 Second memory means (second storage means)
4 IP conversion means 5 Selection means 6 Camera signal processing means 7 Pixel number conversion means 8 Third memory means (third storage means)
9 Synchronization signal generator

Claims (2)

An image sensor, first and second storage means for storing an output signal of the image sensor in synchronization with a first synchronization signal, and outputting a stored content in synchronization with a second synchronization signal, and the second IP conversion means for converting an interlaced video signal output from the storage means into a progressive video signal, and selection means for selecting and outputting either the output signal of the first storage means or the output signal of the IP conversion means A camera signal processing unit that creates a luminance signal and a color difference signal from the output signal of the selection unit, a pixel number conversion unit that converts the number of pixels of the output signal of the camera signal processing unit into a predetermined number of pixels, and the pixel Third storage means for storing the output signal of the number conversion means in synchronization with the second synchronization signal, and outputting the stored contents in synchronization with the third synchronization signal, and the first to third synchronization signals And said selection And a synchronizing signal generating means for outputting a control signal for controlling the stage,
The second synchronization signal is set so that the vertical blanking period is longer than the vertical blanking period of the first and third synchronization signals, and the vertical scanning period of the second synchronization signal is set to the first and first synchronization signals. The selection means selects the output signal of the first storage means during the first vertical scanning period, and the output signal of the IP conversion means during the second vertical scanning period. The output signal of the third storage means storing the output signal of the pixel number conversion means in the first vertical scanning period is set as a moving image output signal, and the output signal in the second vertical scanning period is selected. An imaging apparatus characterized in that an output signal of the camera signal processing means is a still image output signal. The imaging apparatus according to claim 1, wherein vertical scanning periods of the first to third synchronization signals are all equal.

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