JP2021111926A - Imaging apparatus and control method thereof - Google Patents

Abstract

To provide an imaging apparatus and a control method thereof that can detect an appropriate luminance level in a correlated double sampling circuit even when the waveform of an imaging signal output from an imaging element fluctuates.SOLUTION: A digital video camera includes a CMOS sensor 100 that includes a plurality of pixels and outputs a charge generated by photoelectric conversion for each pixel as an imaging signal in synchronization with a transfer CLK signal, a CLK signal generation unit in CMOS which generates a transfer CLK signal and a reference CLK signal based on the transfer CLK signal, a CDS unit 103 that detects the black level and the brightness level of the imaging signal at predetermined timing, a timing detection unit 111 that detects fluctuations in the reference CLK signal, and a CPU 113 that changes the timing to detect the black level and the brightness level of the imaging signal according to the fluctuation of the reference CLK signal.SELECTED DRAWING: Figure 1

Description

The present invention relates to an imaging device such as a digital video camera and a control method thereof.

In an image pickup device such as a digital video camera that images with an image pickup element such as a CMOS sensor or a CCD sensor, the black level and brightness level of an analog signal output from the photodiode of the image pickup element are detected by a correlated double sampling circuit. .. Then, the image data is generated by converting the analog signal output from the correlated double sampling circuit into a digital signal (see Patent Document 1).

Japanese Unexamined Patent Publication No. 2012-228451

The waveform of the analog signal output from the photodiode varies, and one of the causes of such variation is waveform distortion due to temperature. In Patent Document 1, the detection timing in the correlated double sampling circuit is corrected by detecting the temperature in the vicinity of the image sensor, but the variation in the waveform is not only the temperature but also the individual variation of the image sensor. Because of this, it cannot be said that the correction of temperature alone is sufficient. As a result, the detection timing of the black level and the brightness level in the correlated double sampling circuit deviates from the proper timing, and the correct brightness level is not detected, resulting in deterioration of image quality due to poor saturation, uneven brightness, coloring, noise mixing, etc. Will occur.

An object of the present invention is to provide an image pickup apparatus capable of detecting an appropriate luminance level in a correlated double sampling circuit even if the waveform of an image pickup signal output from an image pickup device fluctuates.

The imaging device according to the present invention has a plurality of pixels, and generates an imaging element that outputs the charge generated by photoelectric conversion for each pixel as an imaging signal in synchronization with a predetermined transfer CLK signal, and the transfer CLK signal. In response to the fluctuation of the reference CLK signal, the generation means for generating the reference CLK signal based on the transfer CLK signal, the correlated double sampling circuit that detects the difference between the black level and the brightness level of the imaging signal at a predetermined timing, and the reference CLK signal. It is characterized by comprising a timing control means for changing the predetermined timing.

According to the present invention, even if the waveform of the image pickup signal output from the image pickup device fluctuates, it is possible to detect an appropriate luminance level by the correlation double sampling circuit.

It is a block diagram of the main part of the digital video camera which concerns on this embodiment. It is a circuit diagram which shows the structure of a CMOS sensor. It is a figure explaining the reading timing of the pixel signal from a CMOS sensor. It is a timing chart explaining the detection timing of the black level and the luminance level with respect to the output from a CMOS sensor. It is a figure which shows the division example of a master CLK signal and the setting example of a SHP signal, SHD signal. It is a timing chart explaining the method of setting the SHP signal and the SHD signal based on the reference CLK signal. Table data used to set the SHP and SHD signals based on the temperature of the CMOS sensor. It is a flowchart of the reading control of the image pickup signal in a digital video camera. It is a figure which shows the OB area and the effective pixel area in a CMOS sensor.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a configuration of a main part of a digital video camera which is an example of an imaging device according to the present embodiment.

The main part of the digital video camera here refers to a part related to processing from generating an analog signal by photoelectric conversion of an optical image and generating image data composed of a digital signal from the generated analog signal. Specifically, the digital video camera has, as its main parts, a CMOS sensor 100 which is an example of an image sensor, a temperature sensor 101, an analog front end part 102 (hereinafter referred to as "AFE102"), and an engine part 108. Has.

The CMOS sensor 100 converts the formed optical image into an analog signal pixel by pixel, and outputs the generated analog signal to the AFE unit 102. Here, the configuration of the CMOS sensor 100 will be described with reference to FIG. FIG. 2 is a circuit diagram of the CMOS sensor 100. The CMOS sensor 100 has a PD group 201, a vertical scanning circuit group 203, a vertical line 204, a column amplifier 205, a horizontal scanning circuit group 206, a CLK signal generation unit 207 in CMOS, and an output buffer 208.

In the PD group 201, a plurality of pixels having a photodiode 200 (hereinafter referred to as “PD_200”) that converts an amount of light into an electric charge are arranged in a matrix in the horizontal and vertical directions. Further, the PD group 201 has an FD amplifier 202 connected to each PD_200 and converting the electric charge of the PD_200 into an electric signal. The FD amplifier 202 is connected to a switch SW for the vertical scanning circuit group 203 to select a row. The PD_200 is connected to a reset potential line (not shown) for reducing the accumulated charge to zero via a switch SW.

The vertical scanning circuit group 203 vertically turns a pixel signal (charge of PD_200 converted into an electric signal by the FD amplifier 202) line by line through the FD amplifier 202 by turning on / off the switch SW connected to the FD amplifier 202. Output to line 204. The vertical line 204 is connected to the PD_200 and the column amplifier 205 for each column, and outputs the pixel output of the selected row to the column amplifier 205.

The column amplifier 205 amplifies the pixel signal output row by row to a desired level. One column amplifier 205 is connected to each of the vertical lines 204, and the pixel signals are output line by line to the horizontal scanning circuit group 206. The horizontal scanning circuit group 206 synchronizes the pixel signal for one row output from the column amplifier 205 with the transfer CLK signal output from the CLK signal generation unit 207 in the CMOS one pixel at a time, and sequentially passes through the output buffer 208. , Output to AFE unit 102. Hereinafter, the analog signal output from the output buffer 208 to the AFE unit 102 is referred to as an “imaging signal A”.

The CMOS signal generation unit 207 generates a transfer CLK signal and a reference CLK signal based on the read CLK signal transmitted from the AFE unit 102. The transfer CLK signal is sent to the horizontal scanning circuit group 206, and the reference CLK signal is sent to the engine unit 108. The output buffer 208 electrically converts or amplifies the pixel signals output from the horizontal scanning circuit group 206 pixel by pixel, and outputs them to the AFE unit 102 in synchronization with the transfer CLK signal.

Returning to the description of FIG. The temperature sensor 101 detects the temperature of the CMOS sensor 100 itself or its vicinity. The AFE unit 102 generates a timing signal for sequentially reading the pixel signals line by line from the CMOS sensor 100 based mainly on the VD signal and the HD signal, and supplies the timing signal to the CMOS sensor 100. The VD signal is a read reference signal for one frame, and is a read reference signal for one HD signal line. The AFE unit 102 converts the imaging signal A output from the CMOS sensor 100 into a digital signal and outputs it to the engine unit 108.

More specifically, the AFE unit 102 includes a CDS unit 103 (correlation double sampling circuit), an A / D conversion unit 104, a transfer unit 105, a timing control unit 106, and a read CLK signal generation unit 107. The CDS unit 103 detects and holds the difference between the luminance level and the black level according to the SHP signal indicating the timing for detecting the black level of the imaging signal A and the SHD signal indicating the timing for detecting the luminance level, and A / D. Output to the conversion unit 104. The A / D conversion unit 104 converts the luminance signal output from the CDS unit 103 into a digital signal and outputs it to the transfer unit 105.

The transfer unit 105 generates a signal (hereinafter referred to as “imaging signal D”) obtained by converting the digital signal transferred from the A / D conversion unit 104 into a predetermined format such as LVDS, and transfers the digital signal to the engine unit 108. The timing control unit 106 is set by the engine unit 108 and outputs an SHP signal, an SHD signal, and an ADCLK signal. The ADCLK signal is a clock signal for performing A / D conversion. The read CLK signal generation unit 107 generates a read CLK signal for reading a pixel signal of one pixel based on the master CLK signal output from the engine unit 108, and supplies the read CLK signal to the CMOS sensor 100.

The engine unit 108 has a CPU inside, and mainly outputs VD signals and HD signals which are read reference signals to the AFE unit 102, and performs predetermined image processing on the image pickup signal D output from the AFE unit 102. Image data is generated and output to the subsequent stage (not shown).

More specifically, the engine unit 108 includes an in-engine CLK signal generation unit 109, a PLL unit 110, a timing detection unit 111, an image processing unit 112, and a CPU_113. The in-engine CLK signal generation unit 109 generates a master CLK signal that serves as a reference signal for reading a pixel signal of one pixel, and outputs the master CLK signal to the read CLK signal generation unit 107 and the PLL unit 110 of the AFE unit 102. The PLL unit 110 is a circuit that multiplies the input master CLK signal, and is assumed to be multiplied by 16 in this embodiment.

The timing detection unit 111 compares the multiplied CLK signal input from the PLL unit 110 with the reference CLK signal input from the CMOS sensor 100, and detects the fluctuation direction and the fluctuation amount of the reference CLK signal. Then, the timing detection unit 111 sets the SHP signal, the SHD signal, and the ADCLK signal in the timing control unit 106 based on the fluctuation detection result of the reference CLK signal. The image processing unit 112 performs various image processing such as OB clamping processing and white balance correction of the image pickup signal D input from the transfer unit 105 of the AFE unit 102 to generate image data, and displays and stores the image data (both). Output to the subsequent stage such as (not shown). The CPU_113 controls not only each block in the engine unit 108 but also the CMOS sensor 100 and the AFE unit 102.

Next, reading of the image pickup signal A from the CMOS sensor 100 will be described. When the power of the digital video camera is turned on, the CPU_113 performs the initial setting of the digital video camera. As one of them, the CPU_113 performs initial setting of the timing control unit 106 in the AFE unit 102 via the timing detection unit 111. In the initial setting of the timing control unit 106, the SHP signal (timing to detect the black level of the imaging signal A), the SHD signal (timing to detect the brightness level of the imaging signal A), and the ADCLK signal (timing to perform A / D conversion). Is set. Further, the in-engine CLK signal generation unit 109 reads the master CLK signal for reading the pixel signal of one pixel and outputs it to the CLK signal generation unit 107. In the present embodiment, the master CLK signal is set to 36 MHz, but the present invention is not limited to this.

Further, the engine unit 108 outputs the VD signal and the HD signal to the AFE unit 102. The VD signal corresponds to the frame rate, and is output every 16.6 ms (milliseconds) at 60 fps, for example. On the other hand, the HD signal is output at the time interval required to read the imaging signal for one line in the horizontal direction.

Based on the VD signal and the HD signal, the AFE unit 102 generates a signal for reading the pixel signal line by line in the CMOS sensor 100 for each frame, a signal for determining the line for starting exposure, and the like, and generates a TG signal for these signals. Is output to the vertical scanning circuit group 203 of the CMOS sensor 100. The CMOS sensor 100 starts reading the pixel signal from the first row of the PD group 201 according to the frame read start signal of the TG signal.

In the vertical scanning circuit group 203, when the switch SW on the first line is turned on, the FD amplifier 202 on the first line is connected to the vertical line 204, and the charge of PD_200 is a vertical line as an electric signal via the FD amplifier 202. It is output to 204, and further output to the column amplifier 205. The column amplifier 205 amplifies the input electric signal with a predetermined gain and outputs it to the horizontal scanning circuit group 206.

FIG. 3 is a diagram illustrating a pixel signal reading timing by the CMOS sensor 100. The master CLK signal for reading the electric signal of one pixel is output from the engine unit 108 to the read CLK signal generation unit 107 in AFE_102 at a period of Tp [s]. If the master CLK signal is 36 MHz as described above, Tp is about 27.7 [ns]. The read-out CLK signal generation unit 107 generates a read-out CLK signal and outputs it to the CMOS sensor 100, and the CMOS sensor 100 actually reads out the pixel signal according to the read-out CLK signal.

In the present embodiment, the time for reading the pixel signal for one line is set to Thd [s], and the read CLK signal starts from the position A in FIG. As shown in FIG. 3, the read-out CLK signal is a waveform obtained by masking the period of the master CLK signal having a read-out time Thd [s] for one line excluding the period in which the pixel signal is actually read out. This read CLK signal is input to the CLK signal generation unit 207 in the CMOS. The CMOS signal generation unit 207 generates a transfer CLK signal and a reference CLK signal based on the read CLK signal, transmits the transfer CLK signal to the horizontal scanning circuit group 206, and transmits the reference CLK signal to the engine unit 108 at the timing. It is transmitted to the detection unit 111.

The reference CLK signal is output with a low impedance so that the same waveform as the transfer CLK signal or the rise timing is equivalent to the transfer CLK signal, and the timing detection unit 111 receives the reference CLK signal with a high impedance to cause a waveform change. I try not to. In the present embodiment, the reference CLK signal is described as the same signal as the transfer CLK signal, but the reference CLK signal may be a signal different from the transfer CLK signal as long as the correspondence between the signals is clear.

FIG. 4 is a diagram showing the detection timing of the black level and the luminance level with respect to the image pickup signal A output from the CMOS sensor 100 (relationship between the transfer CLK signal, the image pickup signal A, the SHP signal, and the SHD signal). The “Tpix period” shown in FIG. 4 is an interval for reading a pixel signal of one pixel, corresponds to a 1 CLK signal period of the master CLK signal, and corresponds to 1 CLK signal of the read CLK signal.

The CMOS signal generation unit 207 generates a transfer CLK signal and a reference CLK signal having a delay time Tdl [s] with respect to the read CLK signal, and transmits the generated transfer CLK signal to the horizontal scanning circuit group 206 as a reference CLK. Each signal is output to the timing detection unit 111. The delay time Tdl [s] changes depending on the variation in the wiring capacitance up to the horizontal scanning circuit group 206 and the temperature of the CMOS sensor 100. The horizontal scanning circuit group 206 sequentially selects the output of the column amplifier 205 pixel by pixel with reference to the rising edge of the input transfer CLK signal, and outputs the output to the output buffer 208. As a result, the imaging signal A having an analog waveform is output to the CDS unit 103.

Since the waveform of the transferred CLK signal changes due to the change in the delay time Tdl [s], the imaging signal A fluctuates in the delayed direction when the delay time Tdl [s] becomes long, and conversely, when the delay time Tdl [s] becomes short, the image is imaged. The signal A fluctuates in the faster direction. In this way, the image pickup signal A is output from the CMOS sensor 100 pixel by pixel based on the transfer CLK signal.

The CDS unit 103 detects the black level according to the SHP signal input from the timing control unit 106 at a predetermined timing, and the luminance level according to the SHD signal. The period Tp of the master CLK signal is divided into a predetermined number by the PLL unit 110, and the SHP signal and the SHD signal are set at arbitrary divided positions.

FIG. 5 is a diagram showing a division example of the master CLK signal and a setting example of the SHP signal and the SHD signal. FIG. 5 shows an example in which the master CLK signal is divided into 16 positions t0 to t15 (16 timings) at equal intervals, and the SHP signal and the SHD signal are set at arbitrary timings at positions t0 to t15. Can be done.

FIG. 5 shows an example in which the timing control unit 106 is set to output the SHP signal to the CDS unit 103 at the position t3 and the SHD signal at the position t12. Further, FIG. 4 shows an example in which the black level at the zero position of the imaging signal A is detected at the rising timing of the SHP signal and the luminance level of the imaging signal A is detected at the rising timing of the SHD signal. In some cases, the luminance level Lpix can be detected correctly.

As shown in FIG. 4, the SHP signal is set to a zero level position where there is no noise fluctuation or is small in the image pickup signal A, and the SHD signal is set to a position where the image pickup signal A is flat at the position of the peak of the waveform. Set.

The brightness level signal detected by the CDS unit 103 is A / D converted by the A / D conversion unit 104 according to the ADCLK signal set by the timing control unit 106. The brightness level signal converted into a digital signal is converted into an image pickup signal D of a predetermined transmission format such as LVDS by the transfer unit 105 and transmitted to the image processing unit 112 in the engine unit 108. Although detailed description is omitted, the image processing unit 112 performs image processing such as digital gain, white balance, and gamma correction to generate image data, and outputs the image data to a subsequent stage such as a display device or a storage device (both not shown). do. In this way, image data is generated from the pixel signals output from each pixel of the CMOS sensor 100.

By the way, the imaging signal A is an analog signal. Therefore, when the temperature of the CMOS sensor 100 becomes high, noise is likely to be added to the image pickup signal A, and the image pickup signal A shifts from the SHP signal and the SHD signal due to the fluctuation of the read CLK signal. As a result, the CDS unit 103 cannot detect the correct luminance level. Therefore, a method of setting the SHP signal and the SHD signal by the timing detection unit 111 based on the reference CLK signal will be described with reference to FIG.

6 (a) and 6 (b) are timing charts for explaining a method in which the engine unit 108 appropriately sets the SHP signal and the SHD signal based on the reference CLK signal, respectively. The PLL unit 110 divides the master CLK signal output by the in-engine CLK signal generation unit 109 into a predetermined number and outputs the master CLK signal to the timing detection unit 111. Here, the master CLK signal is divided into 16 parts, and hereinafter, the signal divided into 16 parts by the PLL unit 110 and output to the timing detection unit 111 is referred to as “PLL output”. The timing detection unit 111 detects the rising edge of the reference CLK signal with the PLL output and generates a timing detection signal.

When there is a reference CLK signal at the position shown in FIG. 6A, the timing detection signal is output at the position t5, and the positions of the SHP signal and the SHD signal are determined based on the timing detection signal. If the timing detection signal is output at position t5, the SHP signal is set to position t4 (one before) minus 1 from position t5, and the SHD signal is position t5 plus 8 (after eight). It is set at position t13.

FIG. 6B shows an example in which the rising position of the reference CLK signal is accelerated. When the timing detection signal is output at position t2, the SHP signal is set at position t1 and the SHD signal is set at position t13. By transmitting the position data of the SHP signal and the SHD signal from the timing detection unit 111 to the timing control unit 106, the SHP signal and the SHD signal can be output to the CDS unit 103 at a predetermined timing.

As described above, in the present embodiment, the positions of the SHP signal and the SHD signal (timing at which the SHP signal and the SHD signal are input to the CDS unit 103) can be changed based on the reference CLK signal corresponding to the transfer CLK signal. This makes it possible to detect the luminance level of the image pickup signal A output from the CMOS sensor 100 at an appropriate timing according to the distortion or change caused by the fluctuation of the transfer CLK signal, and as a result, the captured image. It is possible to suppress brightness fluctuations and improve the quality of the image.

By the way, the setting of the SHP signal and the SHD signal with respect to the image pickup signal A may be performed by using the table data showing the relationship between the temperature of the CMOS sensor 100 and each timing of the SHP signal and the SHD signal. FIG. 7 is a diagram showing an example of table data (timing value) used for setting the SHP signal and the SHD signal at appropriate timings based on the temperature of the CMOS sensor 100. The table data of FIG. 7 can be obtained by an experiment or the like, and is stored in the engine unit 108 (for example, a storage means such as a memory of the CPU_113). For example, in the case of the temperature T3 [° C.] of the CMOS sensor 100, the SHP signal is set to the timing Lhp-t3, and the SHD signal is set to the timing Lhd-t3. The timings Lhp-t1 to Lhp-tn and Lhd-t1 to Lhd-tn are each one of a plurality of timings (positions t0 to t15 in the case of 16 divisions in FIG. 5) divided into a predetermined number by the PLL unit 110. Corresponds to.

When using the table data, first, the engine unit 108 (CPU_113) detects the temperature of the CMOS sensor by the temperature sensor 101 when the digital video camera is started. Then, the CPU_113 selects the timing corresponding to the temperature of the CMOS sensor 100 for the SHP signal and the SHD signal with reference to the table data. Subsequently, the timing of the SHP signal and the SHD signal selected through the timing detection unit 111 is set to the initial value, and the reading of the image pickup signal A is started. Further, the timing detection unit 111 detects the timing detection signal from the reference CLK signal and sets the start position of the reference CLK signal, as described with reference to FIG. For example, the start position (initial value) of the reference CLK signal in the case of FIG. 6A is the position t5.

If the reference CLK signal fluctuates while reading the image pickup signal A, the positions of the SHP signal and the SHD signal are changed as follows. That is, when the reference CLK signal changes by + α from the timing of the initial value, the positions of the SHP signal and the SHD signal are also moved by + α. For example, when the initial value is set as shown in FIG. 6A, it is assumed that the rising timing of the reference CLK signal moves from the position t5 to the position t6 by +1. In this case, the SHP signal is changed from the position t4 to the position t5, and the SHD signal is changed from the position t13 to the position t14.

Similarly, when the reference CLK signal changes by −α from the timing of the initial value, the positions of the SHP signal and the SHD signal are also moved by −α. For example, when the initial value is set as shown in FIG. 6A, it is assumed that the rising timing of the reference CLK signal moves from the position t5 to the position t4 by -1. In this case, the SHP signal is changed from the position t4 to the position t3, and the SHD signal is changed from the position t13 to the position t12. In this way, the timing of inputting the SHP signal and the SHD signal to the CDS unit 103 is variable.

As described above, when the reference CLK signal fluctuates with respect to the initially set SHP signal and SHD signal, the timing of inputting the SHP signal and SHD signal to the CDS unit 103 can be changed. As a result, it is possible to detect the brightness level corresponding to the change in the image pickup signal A, and the image quality can be improved.

Next, the read control of the image pickup signal A in the digital video camera will be described with reference to the flowchart. FIG. 8 is a flowchart of reading control of the image pickup signal A by the digital video camera. Each process of the flowchart of FIG. 8 is realized by the CPU_113 expanding the program stored in its own ROM into its own RAM and controlling the operations of the CMOS sensor 100, the AFE unit 102, and the engine unit 108 as a whole. Will be done.

The process starts when the power of the digital video camera is turned on. In S801, the CPU_113 detects the temperature Tn [° C.] of the CMOS sensor 100 by the temperature sensor 101. In S802, the CPU_113 selects each data of the SHP signal and the SHD signal close to the temperature Tn [° C.] from the table data of FIG. In S803, the CPU_113 starts reading the pixel signal (imaging signal A) from the CMOS sensor 100. Normally, when the pixel signal reading is started, the internal temperature of the digital video camera rises. Therefore, in S802, the SHP signal and the SHD signal at the temperature Tb [° C.] which are higher than the temperature Tn [° C.] detected by the temperature sensor 101, are closest to the temperature Tn [° C.], and are present in the table data. Select each data.

In S804, the CPU_113 detects the temperature of the CMOS sensor 100 by the temperature sensor 101. In S805, CPU_113 determines whether or not the temperature detected in S804 is Tb [° C.]. When the CPU_113 determines that the temperature detected in S804 is Tb [° C.] (YES in S805), the process proceeds to S806, and when it is determined that the temperature detected in S804 is not Tb [° C.] (in S805). NO), the process is returned to S804.

In S806, the CPU_113 detects and holds the position (rising position) of the reference CLK signal by the timing detection unit 111. By holding the position of the reference CLK signal corresponding to the temperature of the CMOS sensor 100 and the selected SHP signal and SHD signal in this way, the timing of inputting the SHP signal and the SHD signal to the CDS unit 103 is set with high accuracy. It becomes possible. The CPU_113 controls to change the timings of the SHP signal and the SHD signal according to the fluctuation of the reference CLK signal detected in S806.

In S807, the CPU_113 detects the position of the reference CLK signal and the temperature of the CMOS sensor 100. In S808, the CPU_113 determines whether or not both the position of the reference CLK signal and the temperature of the CMOS sensor 100 have changed. When the CPU_113 determines that both have changed (YES in S808), the process proceeds to S809, and it is determined that both have not changed (only the position of the reference CLK signal has changed) (NO in S808). , The process is returned to S807. The reason why the determination standard of S808 is provided is that the fluctuation of the reference CLK signal is largely due to the temperature, and malfunction when the reference CLK signal fluctuates due to an external factor such as noise is prevented. However, this does not apply if there is a factor other than the temperature that causes the reference CLK signal to fluctuate.

In S809, the CPU_113 changes the timings of the SHP signal and the SHD signal at the time of reading the black level signal. The processing of S809 is executed by using the clamping processing of the black level signal. Therefore, the black level clamping process will be described. The black level clamping process is performed by the image processing unit 112.

FIG. 9 is a diagram simply showing the configuration of an effective pixel region that outputs a luminance level including color information of the CMOS sensor 100 and an optical black region (OB region (light-shielding region)) that outputs a black level after being shielded from light. be.

The vertical OB area 900 is an area in which about 10 lines are shielded in the horizontal direction, and a black level signal (VOB) is always output from the PD in the vertical OB area 900. The horizontal OB region 901 is a region that is shielded from light by about 10 rows in the vertical direction, and a black level signal (HOB) is always output from the PD in the horizontal OB region 901. An imaging signal of the subject is output from the PD arranged in the effective pixel area 902.

The black levels of VOB and HOB also fluctuate due to the influence of the transferred CLK signal, similarly to the imaging signal output from the effective pixel area 902. Therefore, the HOB clamp process is performed using the HOB clamp value obtained by the filter process in which the input HOB is passed through the IIR filter represented by the following formula 1. In the following formula 1, ‘CLHOB_n’ is the current HOB clamp value, ‘HOB_n’ is the read HOB black level value, and ‘CLHOB_n-1’ is the current previous HOB clamp value. Further, ‘β’ is a weighting coefficient, and takes a value larger than 0 and smaller than 1 (0 <β <1).

In the HOB clamp process, the black level value of the HOB read from the horizontal OB area 901 is updated at any time with the HOB clamp value obtained by the following equation 1, and the HOB clamp value after the reading of the HOB on the nth line is completed is set to the effective pixel area 902. Subtract from the nth line of. The HOB clamping process can improve vertical shading.

The larger the weighting coefficient β, the larger the ratio of the black level of the input HOB, so that the HOB clamp value converges faster when the black fluctuates, but it becomes more susceptible to noise. On the other hand, the smaller the weighting coefficient β, the slower the convergence of the HOB clamp value, but the less affected by noise.

The VOB clamp process is a process for improving the influence of the offset of the column amplifier 205, and has a VOB clamp value for each column. Similar to the HOB clamp process, the VOB clamp process is performed using the VOB clamp value obtained by the filter process in which the input VOB is passed through the IIR filter represented by the following formula 2. In addition,'CLVOB_n' is the current VOB clamp value,'VOB_n' is the black level value of the read VOB,'CLVOB_n-1' is the current VOB clamp value immediately before, 0 <weight coefficient β <1, Is. The value of the weighting coefficient β may be the same or different between the following equation 1 and the following equation 2.

In the VOB clamp process, the black level value of the VOB read from the vertical OB region 900 is updated at any time for each column with the VOB clamp value obtained by the following equation 2. Then, when the imaging signal is read from the effective pixel area 902, the VOB clamp value corresponding to the row of the read effective pixel area 902 is subtracted.

CLHOB_n = β × HOB_n + (1-β) × CLHOB_n-1 ... Equation 1
CLVOB_n = β × VOB_n + (1-β) × CLVOB_n-1 ... Equation 2

The HOB clamp process and the VOB clamp process are performed as described above, but it is necessary to read out many HOBs and VOBs until the clamp values converge. Even when the transfer CLK signal fluctuates in the configuration of the present embodiment described above, it may take time for the clamp value to converge due to the fluctuation of the black level as well. For example, when the clamping process is performed by changing the timings of the SHP signal and the SHD signal in S809, it is assumed that the clamping process is not properly executed because the clamp values have not converged.

Therefore, in S809, the HOB clamp value (CLHOB_f) and the VOB clamp value (CLVOB_f) before changing the timings of the SHP signal and the SHD signal are saved, and the SHP signal and the SHD signal are changed only when the HOB and the VOB are read out. Then, from the effective pixel area 902, the imaging signal is read out without changing the SHP signal and the SHD signal, and the clamp values (CLHOB_f, CLVOB_f) that have been saved are used for correction. Further, the same reading as in S809 is repeated with a predetermined number of frames.

The predetermined number of frames in which this repetition is performed is the number of frames until the CLHOB and CLVOB sufficiently converge after the timing of the SHP signal and the SHD signal is changed, and changes depending on the value of the weighting coefficient β in the above equations 1 and 2. That is, the larger the weighting coefficient β, the faster the convergence, so the number of frames decreases, and the smaller the weighting coefficient β, the longer it takes to converge, so the number of frames increases. The processing of S809 is performed until the clamp values converge in this way.

Returning to the description of the flowchart of FIG. When the clamp value converges in S809, the CPU_113 advances the process to S810. In S810, the CPU_113 changes the timings of the SHP signal and the SHD signal for detecting the luminance level from the image pickup signal A output from the effective pixel area 902.

If the timing of the SHP signal and the SHD signal is changed during the imaging of one frame, the brightness level may change in one image and the brightness may be uneven in the screen. It is desirable to change each timing on a frame-by-frame basis. Further, when the fluctuation of the reference CLK signal is large, if the timings of the SHP signal and the SHD signal are changed significantly discretely, there is a possibility that the change in brightness before and after the change can be remarkably visually recognized. Therefore, when the fluctuation of the reference CLK signal is large, it is desirable to continuously change the timing of the SHP signal and the SHD signal with the minimum resolution.

In S811, CPU_113 determines whether or not the power of the digital video camera has been turned off. When the CPU_113 determines that the power remains on (NO in S811), the process returns to S807, and when it determines that the power is turned off (YES in S811), the CPU_113 ends this process.

In this way, when performing the clamping process using VOB and HOB, first, only for the output signal from the OB region, the detection timing of the black level and the luminance level in the CDS unit 103 (timing of the SHP signal and the SHD signal). ) Is changed. Then, after the clamp values have converged, the detection timings of the black level and the luminance level with respect to the output signal from the effective pixel area 902 are changed. This makes it possible to suppress fluctuations in the brightness of the captured image and improve the quality of the image.

Although the present invention has been described in detail based on the preferred embodiments thereof, the present invention is not limited to these specific embodiments, and various embodiments within the scope of the gist of the present invention are also included in the present invention. included. Further, each of the above-described embodiments is merely an embodiment of the present invention, and each embodiment can be combined as appropriate. For example, in the above description, the CDS unit 103 is included in the AFE unit 102 and is arranged independently of the CMOS sensor 100, but the CDS unit 103 and the A / D conversion unit 104 are included in the CMOS sensor 100. It may be configured.

The present invention supplies a program that realizes one or more functions of the above-described embodiment to a system or device via a network or storage medium, and one or more processors in the computer of the system or device reads and executes the program. It can also be realized by the processing to be performed. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

100 CMOS sensor 101 Temperature sensor 102 AFE unit 103 CDS unit 105 Transfer unit 106 Timing control unit 108 Engine unit 111 Timing detection unit 112 Image processing unit 200 Photodiode 207 CMOS signal generator 208 Output buffer 900 Vertical OB area 901 Horizontal OB Area 902 Effective pixel area

Claims (9)

An image sensor that has a plurality of pixels and outputs the electric charge generated by photoelectric conversion for each pixel as an image pickup signal in synchronization with a predetermined transfer CLK signal.
A generation means for generating the transfer CLK signal and a reference CLK signal based on the transfer CLK signal.
A correlated double sampling circuit that detects the difference between the black level and the luminance level of the imaging signal at a predetermined timing,
An image pickup apparatus comprising: a timing control means for changing the predetermined timing according to a fluctuation of the reference CLK signal. The image pickup apparatus according to claim 1, wherein the generation means is provided in the image pickup device. The image sensor has a light-shielding region that is shielded from light and outputs a black level, and an effective pixel region that outputs a luminance level including color information.
Further provided with a processing means for performing a filtering process for converging the black level output from the light-shielding area.
When the reference CLK signal fluctuates, the timing control means changes the predetermined timing for detecting the imaging signal output from the light-shielding region according to the fluctuation of the reference CLK signal, and performs the filter processing. The imaging according to claim 1 or 2, wherein after the black level has converged, the predetermined timing for detecting the imaging signal output from the effective pixel region is changed according to the fluctuation of the reference CLK signal. Device. The imaging apparatus according to claim 3, wherein the processing means performs a clamping process for correcting a luminance level output from the effective pixel region based on a black level converged by the filter processing. A temperature detecting means for detecting the temperature of the image sensor and
Further provided with a holding means for holding a timing value for setting the predetermined timing corresponding to the temperature of the image sensor.
The timing control means sets a timing value having a temperature close to the temperature of the image sensor based on the timing value held by the holding means, and after the temperature of the image sensor reaches the close value, the reference CLK is used. The image pickup apparatus according to any one of claims 1 to 4, wherein the predetermined timing is changed according to a fluctuation of a signal. The imaging according to claim 5, wherein the timing control means changes the predetermined timing when the temperature of the image sensor changes from a temperature close to the temperature and the reference CLK signal fluctuates. Device. The imaging device according to any one of claims 1 to 6, wherein the timing control means changes the predetermined timing for each frame composed of the imaging signal. Further provided with a fluctuation detecting means for detecting the fluctuation amount and the fluctuation direction of the reference CLK signal,
The imaging according to any one of claims 1 to 6, wherein the timing control means changes the predetermined timing in the same fluctuation amount and fluctuation direction as the fluctuation amount and fluctuation direction detected by the fluctuation detection means. Device. It is a control method of the image pickup device.
Steps to generate a transfer CLK signal and a reference CLK signal based on a predetermined signal,
A step of reading out the electric charge generated by photoelectric conversion from an image sensor having a plurality of pixels in synchronization with the transfer CLK signal as an image pickup signal for each pixel, and outputting it to a correlated double sampling circuit.
A step of generating a signal indicating a timing for detecting the black level and a luminance level of the imaging signal in the correlated double sampling circuit based on the reference CLK signal, and a step of generating the signal.
A step of supplying a signal indicating the timing to the correlated double sampling circuit and detecting the black level and the luminance level of the imaging signal by the correlated double sampling circuit.
It has a step of detecting the fluctuation of the reference CLK signal and
A control method for an imaging device, characterized in that, in a step of generating a signal instructing the timing, when the reference CLK signal fluctuates, the timing is changed according to the fluctuation.

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