JP4227596B2 - Pulse generation circuit, imaging device and camera - Google Patents

Description

  The present invention relates to a pulse generation circuit that generates a pulse for driving a solid-state imaging device, and an imaging apparatus and camera including the pulse generation circuit.

  In recent years, in an imaging apparatus such as a digital still camera or a camcorder, an increase in the number of pixels of an imager (imaging element) has been advanced in order to obtain a high-quality captured image. Therefore, in order to maintain the frame rate, it is required to speed up the time for reading the signal detected by the imager. In response to this requirement, a method of dividing a signal detected by an imager into a plurality of readout channels and a method of speeding up a drive pulse for reading a signal detected by an imager have been used. In such an imaging system, a high-speed signal of 10 MHz to 40 MHz is used as a drive pulse for driving the imager and a control pulse for digitizing a pixel signal output from the imager.

  FIG. 12 is a diagram illustrating a schematic configuration of an imaging apparatus including a general imager driving circuit (timing generator). In response to a command from a CPU (Central Processing Unit) 1004, the timing generator 1003 supplies a drive pulse 1011 to the imager 1000. Analog pixel data 1005 output from the imager 1000 is input to an AD (analog-digital) converter 1001. The AD converter 1001 outputs a digital pixel signal 1006 obtained by digitizing the input analog pixel data 1005 in accordance with the AD control pulse 1008 supplied from the timing generation circuit 1003. This digital pixel signal 1006 is supplied to the video engine 1002. The video engine 1002 performs various image processing on the input digital pixel signal 1006 to generate and output image data.

  A timing generation circuit 1003 that is a driving device of a general imager 1000 includes a circuit that generates high-speed horizontal drive pulses such as horizontal transfer pulses and clamp pulses and low-speed vertical drive pulses such as vertical transfer pulses. . The shape and number of high-speed horizontal drive pulses vary depending on the type of imager to be driven, but the relative phase relationship between the plurality of horizontal drive pulses has a great influence on the characteristics of the pixel signal output from the imager.

  FIG. 13 is a schematic configuration diagram of a general CMOS solid-state imaging device, and a timing chart showing drive signals and pixel outputs. In FIG. 13, the pixels 1107 arranged two-dimensionally generate an electrical signal corresponding to the amount of incident light, a so-called pixel signal. To read out pixel signals, first, a row to be read out is selected by the vertical scanning circuit 1106, and pixel signals of pixels arranged in odd-numbered rows are read out to the line memory circuit 1104, and pixels of pixels arranged in even-numbered versions are read out. The signal is read to the line memory circuit 1105. Subsequently, the horizontal scanning circuit 1102 sequentially selects pixel signals read to the line memory circuit 1104 by a horizontal shift pulse 1100 input from outside or inside the chip, is amplified by the amplifier 1108, and is output from the output 1112.

  On the other hand, the horizontal scanning circuit 1103 sequentially selects pixel signals read to the line memory circuit 1105 by a horizontal shift pulse 1101 input from outside or inside the chip, and is amplified by an amplifier 1109 and output from an output 1113. Furthermore, one end of each of the switch 1110 and the switch 1111 is connected to each terminal of the output 1112 and the output 1113, the other ends are connected to each other, and the switches 1110 and the switch 1111 are alternately selected to be aligned and output through the output buffer 1116. A pixel signal is output from 1117. In the timing chart shown in FIG. 13, the period of the horizontal shift pulses 1100 and 1101 is about 50 ns to 100 ns, and the fluctuation of the phase relationship with the multiplexed pulses 1114 and 1115 and an AD sampling pulse (not shown) is within a few ns. Must be controlled.

  As described above, with the increase in the speed of the imager drive signal, the phase relationship between a plurality of drive pulses necessary for driving the imager must be precisely controlled. In particular, the phase relationship between a plurality of horizontal drive pulses or between a horizontal drive pulse and an AD sampling pulse is important for obtaining a high-quality pixel signal. Conventionally, in order to control the phase relationship between a plurality of drive pulses, for example, a variable delay line 1203 is provided between the imager 1200 and the timing generator 1204 as shown in FIG. And the timing generator 1209 are provided with a low-pass filter 1208 to adjust the phase, and a gate element 1213 is provided between the imager 1210 and the timing generator 1214 to adjust the phase.

  Further, for example, a method of performing phase adjustment using the propagation delay of the gate element 1203 shown in FIG. 14 is disclosed (for example, see Patent Document 1). Further, on the premise that the delay circuit is affected by the external environment, for example, a method is disclosed in which the delay setting of the variable delay circuit is changed between when the temperature is low and when the temperature is high to obtain a constant delay amount (for example, (See Patent Document 2).

Japanese Patent Laid-Open No. 9-312810 JP 2001-54027 A

  As shown in FIG. 14, when the phase adjustment is performed using the variable delay line 1203, there is a problem that the drive pulse waveform is disturbed due to the impedance mismatch between the delay line and the receiving end. On the other hand, when the phase adjustment is performed using the low-pass filter 1208, the temperature dependency is increased because the temperature characteristics of the variable resistor and the capacitor and the temperature characteristics of the threshold voltage in the buffer amplifier 1207 are affected. There is.

Further, when the phase adjustment is performed using the propagation delay of the gate element 1203 shown in FIG. 14 as in Patent Document 1, the semiconductor element variation of the gate element and the temperature dependence of the propagation delay are large. There is a problem that it is difficult to ensure stability.
In the case of Patent Document 2, detection means for detecting changes in temperature and voltage is required, and there is a problem that the operation control of imager driving becomes complicated because the delay setting of the variable delay circuit is changed depending on the detection result. .

  The present invention has been made in consideration of the above-described circumstances, and a pulse generation circuit, an imaging apparatus, and a camera that can perform phase adjustment without being affected by an external environment such as temperature and semiconductor process fluctuations as compared with the prior art. The purpose is to provide.

The present invention has been made to solve the above-described problems. In the pulse generation circuit according to the present invention, a plurality of delay elements are connected in series, and an input clock is delayed according to a control signal. Delay means for outputting after delaying by an amount, phase comparison means for detecting a phase difference between the clock and the output of the delay means, and controlling the delay amount according to the phase difference detected by the phase comparison means A delay control means for outputting the control signal to the delay means, a selection output means for selecting one output signal of the delay elements and outputting a delay clock, and a signal synchronized with the input clock. multiple comprising a timing generation circuit for generating for a flip-flop for outputting a signal in synchronization with a signal which the timing generating circuit has generated a clock that is the input A synchronization circuit, a plurality of synchronous output means said plurality of synchronizing circuit outputs a pulse signal where the signals respectively outputted to synchronize to the delay clock edges for controlling the clock signal supplied to the flip-flop And setting means .

Moreover, in the imaging device according to the present invention, the imaging device includes an imaging device, a conversion unit that performs AD conversion on a signal output from the imaging device, and the pulse generation circuit according to any one of claims 1 to 4 . The pulse generation circuit outputs the pulse signal to at least one of the image sensor and the conversion unit.

According to another aspect of the present invention, there is provided a camera comprising: the imaging apparatus according to claim 5; and an optical system that focuses light onto the imaging element.

  The pulse generation circuit, the imaging apparatus, and the camera according to the present invention can perform phase adjustment without being affected by an external environment such as temperature and semiconductor process fluctuation, as compared with the conventional case.

The preferred embodiments of the present invention will be described below with reference to the drawings.
[First embodiment]
FIG. 1 is a diagram showing a schematic configuration of a drive pulse generation device (pulse generation circuit) having a phase adjustment function using a variable delay circuit in the first embodiment of the present invention. As shown in FIG. 1, the variable delay circuit 102 generates a delay clock 104 having a desired delay amount with reference to the input master clock 101. The delay amount of the delay clock 104 is set by a delay selection signal 103 supplied from outside or inside the apparatus. On the other hand, the timing generation circuit 105 is. A signal 106 synchronized with the rising edge of the master clock 101 is generated and output. This signal 106 is the original of the drive pulse of the imager (imaging device).

  The flip-flop 107 generates a sensor drive pulse 108 having a desired delay amount by synchronizing the signal 106 synchronized with the rising edge of the master clock 101 with the rising edge of the delay clock 104.

Next, an internal configuration example of the variable delay circuit 102 illustrated in FIG. 1 will be described.
FIG. 2 is a diagram showing an internal configuration example of the variable delay circuit 102 shown in FIG. As shown in FIG. 2, the phase comparison circuit 202 of the variable delay circuit 102 compares the phase of the master clock 101 that is an input signal and the signal that has passed through the variable delay line 205. The delay control circuit 203 outputs a delay amount control signal 209 that minimizes the phase difference obtained by the phase comparison circuit 202, and supplies the delay amount control signal 209 to the delay element 204 constituting the variable delay line 205.

  The delay control signal 209 may be either a voltage value or a current value, and is controlled by the voltage value if the delay element 204 changes its delay amount according to the voltage value, and by the current value if the delay amount is changed by the current. do it. When a circuit that changes the delay amount of the delay element 204 according to the number of stages of the gate elements constituting the delay element 204 is used, a selector signal that controls the number of stages of the gate elements plays a role of the delay control signal 209.

  Finally, the delay amount of the delay element 204 constituting the variable delay line 205 is controlled so that the period of the master clock 101 as an input signal matches the delay amount of the variable delay line 205. By adjusting the delay amount of the delay element 204 constituting the variable delay line 205 in this way, the delay amount P / N obtained by dividing the period P of the master clock 101 as the input signal by the number N of the delay elements 204 is controlled. It can be a unit.

  That is, the variable delay circuit 102 extracts the output of each delay element 204 and selects the desired delay element output by the selector 206, thereby dividing the period P of the master clock 101 by the number N of the delay elements 204. The delay amount of the delay clock 104 can be controlled with a resolution of P / N increments. Since the variable delay circuit 102 shown in FIG. 2 generates a delay amount that depends on the period of the master clock 101 that is an input signal, the variable delay circuit 102 is hardly affected by ambient temperature and process fluctuations unless the period of the master clock 101 changes. It is characterized by.

Next, a more detailed configuration and operation of FIG. 1 will be described.
FIG. 3 is a diagram showing a more detailed configuration of FIG. 1 and its operation. As shown in FIG. 3, the flip-flop 109 in the timing generation circuit 105 outputs a signal A (signal 106 in FIG. 1) in synchronization with the master clock 101. A signal that the flip-flop 107 outputs the signal A in synchronization with the delay clock 104 is a sensor drive pulse 108.

  The generated sensor driving pulse 108 is synchronized with the rising edge of the delay clock 104 obtained by delaying the master clock 101 by a desired delay amount by the variable delay circuit 102 having the configuration shown in FIG. Less susceptible to fluctuations in the external environment such as fluctuations. The present embodiment is adapted to the drive pulse for driving the imager. However, the same applies by applying the variable delay circuit 102 of the present embodiment to a control signal such as an AD sampling pulse supplied to the AD converter. The effect is obtained.

  As described above, the drive pulse generator of the present embodiment can perform phase adjustment without being affected by the external environment such as temperature and semiconductor process fluctuations as compared with the conventional case. Thereby, in an imaging device using the present drive pulse generator, a high-quality pixel signal that does not depend on fluctuations in the external environment can be easily obtained.

[Second Embodiment]
Next, an example of the internal configuration of the variable delay circuit 517 (see FIG. 5 described later) provided in the drive pulse generator according to the second embodiment of the present invention will be described.
FIG. 4 is a diagram illustrating an internal configuration example of the variable delay circuit 517 in the second embodiment. As shown in FIG. 4, it differs from the variable delay circuit 102 of the first embodiment in that a plurality of output selectors are provided. The variable delay circuit 517 of this embodiment compares the phase of the input signal 401 (master clock 101 in FIG. 1) with the signal that has passed through the variable delay line 405, and a delay amount control signal that minimizes the phase difference. 409 is supplied to the delay element 404 constituting the variable delay line 405. The delay control signal 409 may be either a voltage value or a current value, and is controlled by the voltage value if the delay element 404 changes its delay amount according to the voltage value, and by the current value if the delay amount is changed by the current. do it. When a circuit that changes the delay amount of the delay element 404 according to the number of stages of the gate elements constituting the delay element 404 is used, a selector signal that controls the number of stages of the gate elements plays a role of the delay control signal 409.

  Finally, the delay amount of the delay element 404 constituting the variable delay line is controlled so that the cycle of the input signal 401 matches the delay amount of the variable delay line 405. In this way, by adjusting the delay amount of the delay element 404 constituting the variable delay line 405, a delay amount P / N obtained by dividing the period P of the input signal by the number N of delay elements can be obtained. By extracting the output of each delay element and selecting the output of the desired delay element by the selector 406, a variable delay circuit having a resolution of delay amount P / N increments obtained by dividing the period P of the input signal by the number N of delay elements Is configured. Since this variable delay circuit generates a delay amount depending on the period of the input signal 401, it is characterized by being hardly affected by ambient temperature and process fluctuations unless the period of the input signal 401 changes. The variable delay circuit 517 shown in FIG. 4 generates a plurality of delay signals 408, 411, and 414 by providing a plurality of selectors 406, 409, and 412 that select the output of each delay element 404 constituting the variable delay line 405. can do.

  FIG. 5 is a block diagram showing a drive pulse generator having a phase adjustment function using the variable delay circuit 517 in the second embodiment. As shown in FIG. 5, the delay amount of the sensor drive pulses 1 to N is determined by receiving serial communication signals 501, 502, and 503 supplied from the outside of the drive pulse generation device by the serial communication circuit 516, and a variable delay circuit in the device. 517 and synchronization circuits 507, 508, and 509 are supplied with a delay control signal and a synchronization control signal for each drive pulse, respectively. Three delay clocks (the delay signals 408, 411, and 414) output from the variable delay circuit 517 are input to the clock terminals of the flip-flops 510 to 512.

  FIG. 6 is a block diagram showing details of the drive pulse generation circuit shown in FIG. FIGS. 7A and 7B are timing charts showing the operation of the drive pulse generation circuit of FIG. FIG. 6 is a diagram showing only a part of FIG. 5 necessary for the following description.

  The synchronization circuit 509 outputs a signal A synchronized with the master clock 506. Next, it is inserted to satisfy the setup time and hold time of the D flip-flop 510 that operates at the rising edge of the delay clock 604 that can take an arbitrary delay. The serial communication circuit 516 uses either the master clock 506 or the inverted clock of the master clock 506 as the clock to be supplied to the preceding D flip-flop 602 according to the set delay amount using the exclusive OR element 603. Control to either (edge setting). That is, in this embodiment, the edge setting is set from outside the apparatus by serial communication.

  As in the present embodiment, in the preceding stage D flip-flop 602 synchronized with the delay clock 604, the synchronization can be switched by either normal rotation or inversion of the master clock 506, whereby the delay clock 604 is changed. Even if the master clock 506 has a delay amount (phase difference) of 0 ° to 360 °, synchronization with the delay clock 604 can be ensured. FIGS. 7A and 7B show that the sensor drive pulse 1 changes according to the edge setting. In addition, since the set edge settings do not depend on the external environment such as temperature fluctuations and voltage fluctuations, the delay setting does not need to be changed due to fluctuations in the external environment and should be determined uniquely with respect to the delay settings. Can do.

  As described above, according to the drive pulse generator of the present embodiment, the relative phase relationship between a plurality of sensor drive pulses having different delay amounts is less dependent on the external environment such as temperature and voltage. For example, an image pickup apparatus that drives an image pickup element using the drive pulse generator of this embodiment can obtain high-quality pixel data without being affected by fluctuations in the external environment. The drive pulse generator of this embodiment outputs a drive pulse for driving an imager (imaging device), but is not limited to this, and outputs a control signal such as an AD sampling pulse supplied to the AD converter. Even in this case, the same effect as the present embodiment can be obtained.

[Third embodiment]
The drive pulse generator according to the third embodiment of the present invention is an embodiment similar to the drive pulse generator according to the second embodiment shown in FIG. 5, but the delay setting supplied to the variable delay circuit. The difference is that a synchronization control circuit for supplying an optimum edge selection signal from the information to the synchronization circuit is provided.

  FIG. 8 is a block diagram showing a drive pulse generator having a phase adjustment function using a variable delay circuit in the third embodiment. As for the delay amount of the sensor drive pulses 1 to N, serial communication signals 701, 702, and 703 supplied from the outside of the apparatus are received by the serial communication circuit 716 and supplied to the variable delay circuit 717 and the synchronization control circuit 718 in the apparatus. The The synchronization control circuit 718 generates an optimal synchronization control signal from the delay control signal 704 supplied to the variable delay circuit 717, and supplies it to the synchronization circuits 708, 709 and 710.

  FIG. 9 is a diagram showing a detailed configuration and an edge setting example of the drive pulse generator of FIG. FIG. 9 shows only a part of the configuration of FIG. 8 in detail. The synchronization circuit 806 is inserted so that the signal A synchronized with the master clock 801 satisfies the setup time and hold time of the D flip-flop 809 that operates at the rising edge of the delay clock 802 that can take an arbitrary delay. .

  The clock supplied to the preceding D flip-flop 808 is selected as either the master clock 801 or the inverted clock 802 of the master clock 801 according to the set delay amount. In this embodiment, the edge setting is supplied from the synchronization control circuit 812 according to the delay setting as shown in FIG. The synchronization control signal automatically changes according to the delay amount set in the variable delay circuit 803, and performs control as shown in the table shown in the lower part of FIG. As in this embodiment, the preceding stage D flip-flop 808 synchronized with the delay clock 802 has a switching function of either normal rotation or inversion of the master clock 801, so that the delay clock 802 becomes the master clock 801. On the other hand, even if the delay amount (phase difference) is 0 to 360 degrees, synchronization with the delay clock 802 can be ensured.

  In addition, since the set edge settings do not depend on the external environment such as temperature fluctuations and voltage fluctuations, the delay setting does not need to be changed due to fluctuations in the external environment and should be determined uniquely with respect to the delay settings. Can do.

  According to the drive pulse generation device of the present embodiment, the relative phase relationship between a plurality of sensor drive pulses having different delay amounts is less dependent on the external environment such as temperature and voltage, and therefore has high quality regardless of the external environment. Pixel data can be obtained. Although the present embodiment is adapted to the drive pulse for driving the imager, the same effect can be obtained by applying the present invention to a control signal such as an AD sampling pulse supplied to the AD converter.

[Example 1]
Next, with reference to FIG. 10, Example 1 in the case where the drive pulse generator shown in the first to third embodiments is applied to an imaging device will be described. FIG. 10 is a block diagram showing a case where the drive pulse generator shown in the first to third embodiments is applied to a “still video camera” that is an imaging device. Note that the timing generator 8 described later includes the drive pulse generator shown in the first to third embodiments.

  In FIG. 10, 1 is a barrier that serves as a lens protect and a main switch, 2 is a lens that forms an optical image of a subject on the solid-state image sensor 4, 3 is an aperture for changing the amount of light that has passed through the lens 2, A solid-state imaging device for capturing an object imaged by the lens 2 as an image signal, 6 an A / D converter that performs analog-digital conversion of an image signal output from the solid-state imaging device 4, and 7 an A / D conversion The signal processing unit 8 performs various corrections on the image data output from the device 6 and compresses the data. The solid state image pickup device 4, the image pickup signal processing circuit 5, the A / D converter 6, and the signal processing unit 7 A timing generator for outputting a timing signal, 9 is an overall control / arithmetic unit for controlling various operations and the entire still video camera, 10 is a memory unit for temporarily storing image data, and 11 is a recording medium. Interface unit for performing recording or reading, 12 removable recording medium such as a semiconductor memory for recording or reading of the image data, 13 denotes an interface unit for communicating with an external computer or the like.

Next, the operation of the still video camera at the time of shooting in the above configuration will be described.
When the barrier 1 is opened, the main power supply is turned on, then the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 6 is turned on. Then, in order to control the exposure amount, the overall control / arithmetic unit 9 opens the diaphragm 3, and the signal output from the solid-state imaging device 4 is converted by the A / D converter 6 and then sent to the signal processing unit 7. Entered. Based on this data, exposure calculation is performed by the overall control / calculation unit 9.

The brightness is determined based on the result of the photometry, and the overall control / calculation unit 9 controls the aperture according to the result. Next, based on the signal output from the solid-state imaging device 4, the high-frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 9. Thereafter, the lens is driven to determine whether or not it is in focus. When it is determined that the lens is not in focus, the lens is driven again to perform distance measurement.
Then, after the in-focus state is confirmed, the main exposure starts.

  When the exposure is completed, the image signal output from the solid-state imaging device 4 is A / D converted by the A / D converter 6, passes through the signal processing unit 7, and is written in the memory unit by the overall control / calculation unit 9. Thereafter, the data stored in the memory unit 10 is recorded on a removable recording medium 12 such as a semiconductor memory through the recording medium control I / F unit under the control of the overall control / arithmetic unit 9. Further, the image may be processed by directly entering the computer or the like through the external I / F unit 13.

[Example 2]
Next, with reference to FIG. 11, Example 2 in the case where the drive pulse generator shown in the first to third embodiments is applied to an imaging device will be described. FIG. 11 is a block diagram showing a case where the drive pulse generator shown in the first to third embodiments is applied to a “video camera” that is an imaging device. Note that the drive pulse generator shown in the first to third embodiments transmits a control pulse to a solid-state imaging device 3 and a sample hold circuit 4 to be described later. Here, in particular, FIG. 11 does not show the drive pulse generator shown in the first to third embodiments.

  In FIG. 11, reference numeral 1 includes a focus lens 1 </ b> A for performing focus adjustment, a zoom lens 1 </ b> B for performing a zoom operation, and an imaging lens 1 </ b> C. 2 is a stop, 3 is a solid-state image sensor that photoelectrically converts an object image formed on the imaging surface to convert it into an electrical image signal, 4 is a sample-and-hold image signal output from the solid-state image sensor 3, and A sample hold circuit (S / H circuit) that amplifies the level and outputs a video signal.

  A process circuit 5 performs predetermined processing such as gamma correction, color separation, and blanking processing on the video signal output from the sample hold circuit 4, and outputs a luminance signal Y and a chroma signal C. The chroma signal C output from the process circuit 5 is subjected to white balance and color balance correction by the color signal correction circuit 21 and output as color difference signals RY and BY.

  Also, the luminance signal Y output from the process circuit 5 and the color difference signals RY and BY output from the color signal correction circuit 21 are modulated by an encoder circuit (ENC circuit) 24, and are used as standard television signals. Is output. Then, it is supplied to a monitor EVF such as a video recorder (not shown) or an electronic viewfinder.

  Next, reference numeral 6 denotes an iris control circuit, which controls the iris driving circuit 7 based on the video signal supplied from the sample and hold circuit 4 and opens the aperture 2 so that the level of the video signal becomes a predetermined value. The ig meter is automatically controlled to control the amount.

  Reference numerals 13 and 14 denote different band-limited bandpass filters (BPFs) for extracting high-frequency components necessary for performing focus detection from the video signal output from the sample and hold circuit 4. The signals output from the first band pass filter 13 (BPF 1) and the second band pass filter 14 (BPF 2) are gated by the gate circuit 15 and the focus gate frame signal, respectively, and the peak value is detected by the peak detection circuit 16. Is detected and held, and input to the logic control circuit 17.

  This signal is called a focus voltage, and the focus is adjusted by this focus voltage. Reference numeral 18 denotes a focus encoder that detects the moving position of the focus lens 1A, 19 denotes a zoom encoder that detects the focal length of the zoom lens 1B, and 20 denotes an iris encoder that detects the opening amount of the diaphragm 2. The detection values of these encoders are supplied to a logic control circuit 17 that performs system control.

  The logic control circuit 17 performs focus detection by performing focus detection on the subject based on a video signal corresponding to the set focus detection area. That is, the peak value information of the high frequency components supplied from the respective band pass filters 13 and 14 is taken in, and the focus motor 10 is supplied to the focus drive circuit 9 to drive the focus lens 1A to the position where the peak value of the high frequency components is maximized. Control signals such as a rotation direction, a rotation speed, and rotation / stop are supplied and controlled.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention.

It is a figure which shows schematic structure of the drive pulse generator (pulse generation circuit) which has a phase adjustment function using the variable delay circuit in 1st embodiment of this invention. FIG. 2 is a diagram illustrating an internal configuration example of a variable delay circuit 102 illustrated in FIG. 1. It is a figure which shows the further detailed structure and operation | movement of FIG. It is a figure which shows the internal structural example of the variable delay circuit 517 in 2nd embodiment. It is a block diagram which shows the drive pulse generator which has a phase adjustment function using the variable delay circuit 517 in 2nd embodiment. FIG. 6 is a block diagram showing details of the drive pulse generation circuit shown in FIG. 5. 7 is a timing chart showing an operation of the drive pulse generation circuit of FIG. 6. It is a block diagram which shows the drive pulse generator which has a phase adjustment function using a variable delay circuit in 3rd embodiment. It is a figure which shows the detailed structure and the example of an edge setting of the drive pulse generator of FIG. It is a block diagram which shows the case where the drive pulse generator shown in said 1st-3rd embodiment is applied to the "still video camera" which is an imaging device. It is a block diagram which shows the case where the drive pulse generator shown in said 1st-3rd embodiment is applied to the "video camera" which is an imaging device. It is a figure which shows schematic structure of the imaging device containing the drive circuit (timing generator) of a general imager. 2 is a schematic configuration diagram of a general CMOS type solid-state imaging device, and a timing chart showing drive signals and pixel outputs. It is a figure which shows the conventional phase adjustment method.

Explanation of symbols

101, 506, 706, 801... Master clocks 102, 517, 718, 803... Variable delay circuits 103, 407, 410, 413, 504, 704... Delay selection signals 104, 604, 802. Delay clock 105, 707, 805 ... Timing generation circuit 106 ... Internal signal 107, 109, 510, 511, 512, 601, 602, 711, 712, 713, 807, 808, 809 ... D flip-flop 108, 513, 514, 515, 714, 715, 716, 811, 1011, 1201, 1206, 1211 ... sensor drive pulse 401 ... input signals 202, 402 ... phase comparison circuits 203,403 ... Delay control circuits 204, 404 ... delay elements 205, 405 ... variable delay lines 206, 406, 409, 412 ... selectors 408, 411, 414 ... output signals 209, 409 ... delay control signals 501, 701 ... chip select 502, 702 ... serial clocks 503, 703 Serial data 505, 705, ... Synchronization control signals 507, 508, 509, 708, 709, 710, 806 ... Synchronization circuits 515, 717, 804 ... Serial communication circuits 603, 810, .EXOR gates 718, 812 ... synchronization control circuit

Claims (6)

A delay unit configured by connecting a plurality of delay elements in series and delaying an input clock by a delay amount according to a control signal; and
Phase comparison means for detecting a phase difference between the clock and the output of the delay means;
Delay control means for outputting the control signal for controlling the delay amount according to the phase difference detected by the phase comparison means to the delay means;
Selection output means for selecting any one output signal of the delay elements and outputting a delay clock;
A timing generation circuit for generating a signal synchronized with the input clock;
A plurality of synchronization circuits comprising flip-flops for synchronizing the signal generated by the timing generation circuit with the input clock and outputting the signal;
A plurality of synchronization output means for outputting a pulse signal obtained by synchronizing a signal output from each of the plurality of synchronization circuits with the delay clock ;
An edge setting means for controlling a clock of a signal supplied to the flip-flop .   The pulse signal is synchronized by the delay clock after the pulse signal is synchronized by selecting either one of rising edge or falling edge of the clock according to a set delay amount. 2. The pulse generation circuit according to 1. 2. A delay setting means for supplying a delay control signal to a variable delay circuit comprising the delay means, the phase comparison means, the delay control means, and the selection output means. Or the pulse generation circuit of 2. 4. The edge setting means controls a clock of a signal supplied to the flip-flop according to a delay setting of a delay control signal supplied to the variable delay circuit by the delay setting means. Pulse generation circuit. An image sensor;
Conversion means for AD converting a signal output from the image sensor;
A pulse generation circuit according to any one of claims 1 to 4,
Comprising
The image pickup apparatus, wherein the pulse generation circuit outputs the pulse signal to at least one of the image pickup device and the conversion unit. An imaging device according to claim 5;
An optical system for imaging light onto the image sensor.

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