JP2010136253A - Imaging apparatus and control method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging apparatus for facilitating a phase adjustment in switching of a frequency of a clock and making it difficult to visually recognize a pattern of beat noise. <P>SOLUTION: A digital camera includes a CCD sensor 104, a multi-output clock generating circuit 110 for generating a plurality of clocks, a timing signal generating circuit 105, and a control section 121. In accordance with a reference timing clock MCLK generated by the multi-output clock generating circuit 110, the timing signal generating circuit 105 generates a plurality of timing signals for controlling operation of the CCD sensor 104. Synchronously with a vertical synchronizing signal generated by the timing signal generating circuit 105, the control section 121 switches a frequency of the reference timing clock MCLK generated by the multi-output clock generating circuit 110 to a corresponding frequency among a plurality of preset different frequencies. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an imaging apparatus having an imaging element and a control method thereof.

  In recent years, with the increase in the number of pixels of an image sensor, the drive frequency of the image sensor has been increased. Under such circumstances, it is required to reduce radiation noise generated by increasing the drive frequency. ing. Therefore, in order to reduce radiation noise, an imaging apparatus is proposed that applies a frequency diffusion technique for reducing the oscillation accuracy of a reference clock serving as a reference for driving frequency and dispersing frequency components (Patent Document 1). reference).

In an imaging apparatus to which this frequency spreading technique is applied, a clock whose frequency is continuously changed at a predetermined cycle is generated, and the phase of the clock is reset at random timing. Thereby, it is possible to reduce beat noise that occurs when the frequency spreading cycle and the imaging device drive cycle (horizontal synchronization signal cycle) are asynchronous.
JP 2001-285726 A

  When the drive frequency of the image sensor is low, the optimum phase stable region is widened and it is not necessary to perform phase adjustment. However, when the drive frequency is high, the phase stable region is narrowed, and in order to maintain image quality, drive Optimal phase adjustment is required for each frequency.

  For example, when a CCD (Charged Coupled Devices) is used as the imaging device, a horizontal transfer pulse and a reset gate pulse for driving the CCD are generated based on a reference clock. In addition, a sample hold pulse, a sampling pulse, and the like for controlling processing of a signal output from the CCD are generated based on a reference clock. These pulses have the same frequency as the reference clock. If the phase relationship of these pulses is not optimal, charge transfer failure, reset failure, and signal processing of signals output from the CCD are caused by CCD drive, linearity failure, color mixture, noise deterioration, data latch error, etc. .

  However, in the case of an imaging device using the above-described frequency spread technology, a pulse for driving the imaging device and a signal processing pulse for controlling processing of an output signal read from the imaging device are generated based on the reference clock. Therefore, the frequency of these pulses is linked. For this reason, since the frequency continuously changes in a predetermined range around the reference clock, it is difficult to optimally adjust the phase of each pulse for all frequencies. As a result, high image quality cannot be maintained.

  An object of the present invention is to provide an imaging apparatus and a control method therefor that facilitate phase adjustment associated with switching of the clock frequency and make it difficult to visually recognize a beat noise pattern.

  In order to achieve the above object, the present invention provides a clock generation means and a timing signal generation means for generating a timing signal including a vertical synchronization signal for controlling the operation of the image sensor in accordance with the clock generated by the clock generation means. And an imaging device comprising: a control unit that switches a frequency of a clock generated by the clock generation unit in synchronization with the vertical synchronization signal.

  In addition, the present invention provides a method for controlling the imaging apparatus in order to achieve the above object.

  ADVANTAGE OF THE INVENTION According to this invention, while adjusting the phase accompanying switching of the frequency of a clock, it can make it difficult to visually recognize the pattern of beat noise.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of an imaging apparatus according to the first embodiment of the present invention. In the present embodiment, a digital camera using a solid-state imaging device made up of a CCD sensor will be described as an imaging device.

  As shown in FIG. 1, a digital camera is a CCD (Charge Coupled Device) that converts a lens 101, an aperture 102, a shutter 103, and an optical image of a subject formed on the imaging surface through these into an electrical signal and outputs the electrical signal. ) A sensor 104 is provided. The aperture 102 and the shutter 103 are driven by an exposure control circuit 118 so that a desired exposure amount can be obtained. The exposure control circuit 118 outputs a control pulse for operating the electronic shutter to the timing signal generation circuit 105 described later. An electrical signal output from the CCD sensor 104 (hereinafter referred to as a CCD output signal) is input to the imaging circuit 130.

  The imaging circuit 130 performs processing for converting the input CCD output signal into an imaging signal. The imaging circuit 130 includes a CDS (Correlated Double Sampling) circuit 106, a PGA (Programmable Gain Amplifier) circuit 107, an A / D conversion circuit 109, a clamp circuit 108, and a timing signal generation circuit 105. Each of the CDS circuit 106, the PGA circuit 107, the clamp circuit 108, and the AD conversion circuit 109 operates according to the reference timing clock MCLK generated by the multi-output clock generation circuit 110. The multi-output clock generation circuit 110 can generate clocks having a plurality of different frequencies (cycles), and generates a clock having a frequency selected by the control unit 121 described later.

  Based on the sample hold pulse from the timing signal generation circuit 105, the CDS circuit 106 performs a correlated double sampling process for removing amplifier noise and the like on the input CCD output signal, and obtained by the process. Output analog signals. The PGA circuit 107 amplifies and outputs the analog signal output from the CDS circuit 106. The A / D conversion circuit 109 samples the analog signal output from the PGA circuit 107 based on the sampling pulse from the timing signal generation circuit 105 and converts it into a digital signal. This digital signal is input to the video processing circuit 111 as an imaging signal.

  Based on the clamp pulse from the timing signal generation circuit 105, the clamp circuit 108 clamps the output of the OB (Optical Black) pixel to a reference voltage in order to reproduce the black level. The output of the clamp circuit 108 is input to the CDS circuit 106 and the PGA circuit 107.

  The timing signal generation circuit 105 generates a plurality of timing signals for controlling the operation of the CCD 104 according to the reference clock MCLK generated by the multi-output clock generation circuit 110. As timing signals for controlling the operation of the CCD 104, there are a horizontal synchronization signal HD and a vertical synchronization signal VD, a readout pulse, a transfer pulse, and an electronic shutter pulse. These signals and pulses are output to the CCD 104. Here, the electronic shutter pulse is generated based on the control pulse from the exposure control circuit 118. Further, the horizontal synchronization signal HD and the vertical synchronization signal VD are also output to a video processing circuit 111 described later in order to ensure synchronization during image processing.

  The timing signal generation circuit 105 generates a plurality of timing signals for controlling the operations of the circuits 106, 108, and 109 of the imaging circuit 130 in accordance with the reference clock MCLK. As described above, the timing signal includes a sample hold pulse for the CDS circuit 106, a clamp pulse for the clamp circuit 108, and a sampling pulse for the A / D conversion circuit 109.

  The video processing circuit 111 includes a video signal processing circuit 112 and a photometry circuit 113 that operate according to the clock generated by the video processing circuit clock 117. The video signal processing circuit 112 performs processing for converting the input imaging signal into a video signal including a luminance signal and a color signal, image correction processing, and the like. The photometric circuit 113 measures the photometric quantity based on the luminance obtained by the video signal processing circuit 112. This photometric quantity is used for exposure control. The video processing circuit 111 measures a color temperature of the subject from the input imaging signal and calculates a WB (white balance) circuit (not shown) that calculates information necessary for white balance of the video signal processing circuit 112. Have.

  The video signal obtained by the processing of the video signal processing circuit 112 is input to an LCD (liquid crystal display panel) 115. The LCD 115 is driven based on the clock generated by the LCD clock generation circuit 114 and displays the video indicated by the input video signal. The video signal obtained by the processing of the video signal processing circuit 112 is output to the outside via the external output terminal 116. EVF (Electrical View Fineder) is realized by displaying the video indicated by the video signal on the LCD 115 and on an external display device connected to the external output terminal 116.

  The CDS circuit 106, the PGA circuit 107, the timing signal generation circuit 105, the multi-output clock generation circuit 110, and the exposure control circuit 118 are controlled by a control unit 121 including a CPU, a ROM, a RAM (not shown), and the like. The control unit 121 operates in accordance with the clock generated by the CPU clock generation unit 122, and controls the entire digital camera and performs individual processing. For example, the control unit 121 performs photometry and exposure operations in response to the pressing operation of the shutter switch 124. Here, the shutter switch 124 is composed of a multistage switch including a switch SW1 and a switch SW2. When the switch SW1 is turned on in response to a pressing operation of the shutter switch 124, photometry is performed, and when the switch SW2 is turned on, an exposure operation is performed. Is called. The control unit 121 drives the strobe 125 as necessary. In addition, the control unit 121 performs control to record the captured image on the recording medium 127 and to read out the image recorded on the recording medium 127 and display it on the LCD 115.

  In this embodiment, when shooting, the EVF is activated, and the subject image captured by the lens 101 is displayed on the LCD 115 or an external device. When this EVF is activated, thinning readout using pixel thinning and pixel addition in the vertical direction is performed. At the time of actual photographing, frame reading is performed in which all pixels are divided into three fields for reading. At the time of this main photographing, beat noise reduction processing and phase adjustment processing are performed.

  The frame readout and thinning readout will be described with reference to FIGS. FIG. 2 is a diagram showing a pixel region of the CCD sensor 104 of FIG. FIG. 3 is a diagram schematically showing frame reading. FIG. 4 is a diagram schematically showing thinning readout.

  When shooting, an EVF that displays images on the LCD 115 or an external device is used. When this EVF is used, if all pixels are read out every frame, the frame rate becomes extremely low. Therefore, in order to increase the frame rate, thinning-out readout using vertical pixel skipping, pixel addition, or the like is performed. . In this thinning readout, the resolution is lowered, but the frame rate can be increased. This thinning readout is also used when shooting a moving image.

  The CCD sensor 104 is a primary color sensor and has a pixel area as shown in FIG. Here, an OB pixel that is a light shielding portion is represented by a pixel 201, and an effective pixel that is a light receiving portion is represented by a pixel 202. Further, as shown in FIG. 3, the CCD sensor 104 includes a plurality of vertical transfer paths 301, a horizontal transfer path 303, and an output stage amplifier 305.

  The frame reading is a method in which one frame is divided into three fields of a first field, a second field, and a third field to read out the pixel area of the CCD sensor 104. Here, there are 1 to 999 lines as the horizontal lines of the CCD sensor 104. Among these lines, as shown in FIG. 3A, 2, 5, 8,..., 992, 995, 998 lines are read out as the first field. Further, as shown in FIG. 3B, lines 3, 6, 9,..., 993, 996, and 999 are read as the second field. Further, as shown in FIG. 3C, lines 1, 4, 7,..., 991, 994, and 997 are read as the third field. Reading of each field is performed in the order of the first field, the second field, and the third field.

  In the thinning readout, pixel thinning and pixel addition are performed so that only a part of the pixel area of the CCD sensor shown in FIG. 2 is read out. In thinning readout, as shown in FIG. 4, out of all the lines of the CCD sensor 104, 1 line and 5 lines are added, and 10 lines and 14 lines are added. Read sequentially.

  Next, a pixel reading operation from the CCD sensor 104 will be described with reference to FIGS. FIG. 5 is a diagram showing a timing chart of the pixel reading operation from the CCD sensor 104. FIG. 6 is a timing chart showing the relationship between the electrical signal output from the CCD sensor 104 and each imaging pulse.

  The timing signal generation circuit 105 operates on the CCD sensor 104 based on the reference timing clock MCLK (reference clock for one pixel of the CCD sensor 104) output from the multi-output clock generation circuit 110. The timing signal generation circuit 105 generates a vertical synchronization signal VD, a horizontal synchronization signal HD, a readout pulse, a vertical transfer pulse, a horizontal transfer pulse, and an electronic shutter pulse based on the frequency of the reference timing clock MCLK. The period of these signals and pulses is defined based on the period (frequency) of the reference timing MCLK. 8 channels of vertical synchronizing signal VD, horizontal synchronizing signal HD, combined signals V1, V2, V3A, V3B, V4, V5A, V5B and V6 of vertical transfer pulse and readout pulse, and 2 channels of horizontal transfer pulses H1 and H2 are CCD. Output to the sensor 104. Further, an electronic shutter pulse for operating the electronic shutter by adjusting the saturation level of the CCD output signal and sweeping out the charge is output to the CCD sensor 104.

  The vertical synchronization signal VD defines a unit interval for obtaining a signal indicating an image for one field. For example, as shown in FIG. 5, thinning readout during EVF operation is 2VD period, exposure period during main photographing is 1VD period (the CCD sensor during driving is in thinning mode), and frame readout during main photographing is The period is 3VD. In addition, after the completion of the main photographing, it is assumed to return to the thinning readout at the time of EVF. Further, when frame reading is performed, one frame is divided into three fields for reading, so that one vertical sync signal VD constitutes one image.

  Further, in each readout of frame readout and thinning readout, the horizontal synchronization signal HD defines a unit section indicating a horizontal line of an image. Each of the channels V1A, V3A, V3B, V5A, and V5B indicates one of three values of H (High), M (Middle), and L (Low), and each of the channels V2, V4, and V6 has two values of M and L. One of the values shall be indicated. Here, a pulse at a level from M to H is a read pulse, and a pulse from M to L is a vertical transfer pulse.

  The electronic shutter pulse is a pulse whose DC voltage value is set to a value for adjusting the saturation level of the CCD output signal, and the DC voltage value of the electronic shutter pulse increases the saturation level of the CCD output signal at the time of actual photographing. As lowered. Further, the DC voltage is superimposed with a pulse for instructing the operation of sweeping out the electric charge accumulated in the CCD sensor 104, that is, the operation of the electronic shutter.

  In the thinning readout during the EVF operation and during the exposure period, the period B and the period C in which the operation of the electronic shutter is stopped become the exposure period of each field, and the electric charges photoelectrically converted in the photodiode portion by the readout pulses 504 and 506 Are moved to the vertical transfer register. Then, the charges transferred to the vertical transfer register are transferred via the vertical transfer path 301 for each line by the vertical transfer pulse 503. Although not shown in FIG. 5, each line is transferred to the horizontal transfer path 303 for each pixel by the horizontal transfer pulses H1 and H2 in a cycle in which the horizontal synchronization signal HD is one cycle. The charge of each pixel is output to the CDS circuit 106 as an electrical signal, that is, a CCD output signal, through the output stage amplifier 305.

  At the time of actual photographing, first, the DC voltage value of the electronic shutter pulse is lowered, and the saturation level of the CCD output signal is raised. The exposure period at the time of actual photographing is a period from the stop of the operation of the electronic shutter to the closing of the shutter 103, that is, a period D. At the time of actual photographing, a high-speed sweeping period 501 for removing dark signal components and smear components accumulated in the vertical transfer path 301 is provided before the reading operation of each field. In this period 501, a vertical transfer pulse having a higher frequency than that during normal transfer is output. That is, high-speed sweeping is performed.

  After the high-speed sweeping is completed, the electric charge photoelectrically converted in the photodiode portion is moved to the vertical transfer register by the readout pulse for each field (505 for the first field, 502 for the second field, and 507 for the third field). . The electric charge is transferred via the vertical transfer path 301 for each line by the vertical transfer pulse 503. With respect to this high-speed sweeping, each line is transferred to the horizontal transfer path 303 pixel by pixel by the horizontal transfer pulses H1 and H2 in a cycle in which the horizontal synchronization signal HD is one cycle, as in thinning readout. The charge of each pixel is output to the CDS circuit 106 as an electrical signal (CCD output signal) through the output stage amplifier 305.

  As shown in FIG. 6, the CCD output signal (electric signal output from the CCD 104) is established by the phase relationship between the horizontal transfer pulses H1 and H2 and the reset gate pulse RG. The CCD output signal includes a reset unit 609, a feed-through unit 610, and a signal unit 611, and has a negative polarity.

  When the CCD output signal is input to the CDS circuit 106, correlated double sampling is performed on the feedthrough unit 610 by the pulse SHBLK of the sample hold pulse. The signal unit 611 is subjected to correlated double sampling by a sample hold pulse pulse SHDATA. Then, the analog signal subjected to the correlated double sampling is amplified to a predetermined multiple signal in the PGA circuit 107. The amplified analog signal is converted into a digital signal by the AD conversion circuit 109 by the sampling pulse CLK.

  The horizontal transfer pulses H1 and H2, the reset gate pulse RG, the sample hold pulse pulse SHBLK, the pulse SHDATA, and the sampling pulse CLK are called imaging pulses.

  These imaging pulses are all generated with reference to the reference timing clock MCLK, and the frequency of each imaging pulse is the same as the frequency of the reference timing clock MCLK. Each phase of the imaging pulse is adjusted with reference to the reference timing clock MCLK, for example, at a timing obtained by equally dividing the reference timing clock MCLK into 48 divisions.

  Here, when the driving frequency (imaging pulse frequency) of the imaging circuit 130 is low, the optimum phase stable region is widened. However, when the driving frequency (imaging pulse frequency) is high, the phase stable region is narrowed and driven. It is necessary to adjust the phase for each frequency. Therefore, with respect to a high driving frequency, the phase of each of the imaging pulses is set to a phase that provides the best S / N ratio. If this phase is not properly set, horizontal transfer pulses H1 and H2 may cause transfer failure, reset gate pulse RG may have color mixing due to reset failure, sample hold pulse may have poor linearity, color mixing, and deterioration of random noise. Get up. Further, with respect to the sampling pulse CLK, data latch error, deterioration of kickback noise to the analog portion, and the like occur.

  Next, beat noise that appears when the reference timing clock MCLK and the clock LCD interfere with each other will be described with reference to FIGS. FIG. 7 is a diagram schematically showing a state in which beat noise appears in an image obtained by actual photographing (an image obtained by frame reading). FIG. 8 is a diagram in which the components of the imaging clock, LCD clock, and beat noise are developed on the frequency axis.

  For example, assume that the multi-output clock generation circuit 110 outputs a reference timing clock MCLK having a frequency of 36 MHz. In this case, the CCD sensor 104 and the imaging circuit 130 are operated by the imaging pulse generated by the timing signal generation circuit 105 in accordance with the 36 MHz reference timing clock MCLK. That is, the CCD sensor 104 and the imaging circuit 130 operate at a frequency of 36 MHz. Further, when the LCD clock generation circuit 114 outputs a clock (clock LCD) having a frequency of 30 MHz, the LCD 115 operates at a driving frequency of 30 MHz.

  When the reference timing clock MCLK and the clock LCD interfere with each other, the CDS circuit 106 performs correlated double sampling on the 30 MHz clock LCD at a frequency of 36 MHz. Therefore, for example, as shown in FIG. 7, beat noise of 6 MHz, which is a difference between the frequencies, appears in the image. Since each field has an interlace configuration, beat noise appears in a visually recognizable form as shown in FIG. Although FIG. 7 shows a part cut out from an image, beat noise is actually generated in a similar pattern over the entire pixel area of the CCD sensor 104. Since this beat noise has a frequency component of 6 MHz, it becomes a beat noise of 6 clock cycles (36 MHz / 6 MHz), that is, 6 pixel cycles with respect to the reference timing clock MCLK of 36 MHz.

  Further, as shown in FIG. 8, the spectrum of beat noise is determined by the spectrum of the reference timing clock MCLK and the LCD clock. Therefore, it is desirable that the beat noise generated in a pattern that is easily visible to the human eye as shown in FIG. . Therefore, in the present embodiment, beat noise reduction processing is performed to make it difficult to visually recognize the beat noise pattern.

  The beat noise reduction process will be described with reference to FIGS. FIG. 9 is a diagram schematically showing an image in which the beat noise pattern is difficult to visually recognize by the beat noise reduction processing in the first embodiment of the present invention. FIG. 10 is a diagram showing each drive frequency and beat noise frequency and each spectrum when it is difficult to visually recognize the beat noise pattern. FIG. 11 is a diagram showing drive frequencies and beat noise frequencies and respective spectra when a beat noise pattern is easily visible.

  The beat noise reduction method of the present embodiment switches the drive frequency of the imaging circuit 130 (the frequency of the reference timing clock MCLK) in each of the first to third fields, that is, in synchronization with the vertical synchronization signal VD. is there. Here, each of the first to third fields is associated in advance with a frequency at which the beat noise pattern is difficult to visually recognize. Information indicating the driving frequency associated with each field is stored in a ROM (not shown) provided in the control unit 121.

  For example, the first field is associated with a drive frequency of 32 MHz, the second field is associated with a drive frequency of 35 MHz, and the third field is associated with a drive frequency of 33 MHz. Switching to the drive frequency corresponding to each field is performed. Is called. That is, the driving frequency corresponding to each field is selected, and the frequency of the reference timing clock MCLK is switched to the selected driving frequency.

  In this case, the frequency components of beat noise in each field are 2 MHz (32 MHz-30 MHz), 5 MHz (35 MHz-30 MHz), and 3 MHz (33 MHz-30 MHz). That is, beat noise occurs in the first field at 16 pixel cycles (32 MHz / 2 MHz), the second field at 7 pixel cycles (35 MHz / 5 MHz), and the third field at 11 pixel cycles (33 MHz / 3 MHz). Appear. However, since the pixel cycle in which beat noise appears in each field changes, the pattern of the beat noise that appears is difficult to visually recognize.

  Further, by switching the driving frequency of the imaging circuit 130 in each of the first to third fields, the driving frequencies are dispersed as shown in FIG. 10, and the spectrum of each driving frequency becomes weak. As a result, the beat noise spectrum for each field also becomes weak, and it is difficult to visually recognize the beat noise pattern that appears in the image obtained by the actual photographing.

  Here, even when the drive frequency is switched, a beat noise pattern that is easy to visually recognize, for example, a pattern as shown in FIG. 11 may occur. In this case, the driving frequency is 36 MHz for the first field, the driving frequency is 45 MHz for the second field, and the driving frequency is 40 MHz for the third field. In this case, the frequency components of beat noise in each field are 6 MHz (36 MHz-30 MHz), 15 MHz (45 MHz-30 MHz), 10 MHz (40 MHz-30 MHz). That is, beats are generated at a pixel period of 6 pixel periods (36 MHz / 6 MHz) in the first field, 3 pixel periods (45 MHz / 15 MHz) in the second field, and 4 pixel periods (40 MHz / 10 MHz) in the third field. Noise appears. As a result, although the spectrum of the frequency component of beat noise is dispersed, the beat noise pattern becomes an easily visible pattern, and the effect of reducing beat noise cannot be sufficiently obtained.

  As described above, it is very important to preset the driving frequency for each of the first to third fields so that the beat noise pattern is difficult to visually recognize.

  Further, when the drive frequency is switched in each of the first to third fields, a phase adjustment process is performed for each drive frequency. This phase adjustment processing includes setting the phase of the imaging pulse and setting the generation timing of the imaging pulse. When the CCD sensor 104 is driven at each driving frequency, the setting of the phase of the imaging pulse for making the operation time of the CCD sensor 104 in the field the same is calculated in advance so that the S / H ratio is the best for each driving frequency. The phase of the imaging pulse is set. Specifically, phase information indicating the phase of the imaging pulse calculated in advance so that the S / H ratio is the best for each drive frequency is stored in a ROM (not shown) in the control unit 121. When setting the phase of the imaging pulse, the phase of the imaging pulse corresponding to the drive frequency is set in the timing signal generation circuit 151 with reference to the phase information stored in the ROM.

  The imaging pulse generation timing is set so that when the CCD sensor 104 is driven at each drive frequency, the operation time of the CCD sensor 104 in each field is the same. Is set. Specifically, the operation time of the CCD sensor 104 is a time composed of an exposure time, a readout time, and a vertical transfer time. The generation timing (generation period) of the corresponding imaging pulse is set according to the drive frequency so that the exposure time, readout time, and vertical transfer time for each drive frequency are the same. This is because switching between drive frequencies may cause a difference between the exposure time, read time, and vertical transfer time for each drive frequency.

  Here, the adjustment of the vertical transfer time will be described with reference to FIG. FIG. 12 is a timing chart based on the horizontal synchronization signal HD in the second field in the period A of FIG.

For example, when paying attention to the vertical transfer pulse V1, the transfer time is set to the time t (usec) defined by the number of clocks of the reference timing clock MCLK, and the number of clocks corresponding to the time t is set to a (clock). in this case,
t = a × 1/32
The relationship is established.

  That is, assuming that the transfer time t (usec), the drive frequency f (MHz), and the transfer clock number x (clock), these are expressed by the following relational expression.

t = x × 1 / f
When the transfer time t for each field (drive frequency) is the same, the transfer clock number x at which the transfer time t of each field is the same with respect to the drive frequency f of each field is based on the relational expression. Calculated. Further, in the same manner, the number of clocks for making the same transfer time and read time of each vertical transfer pulse with respect to the drive frequency of each field are calculated.

  The number of clocks that make the exposure time, readout time, and vertical transfer time the same for each drive frequency is stored in the ROM in the control unit 121 as generation timing information that defines the generation timing of the corresponding imaging pulse. When setting the generation timing, the generation timing corresponding to the drive frequency is set in the timing signal generation circuit 151 with reference to the generation timing information stored in the ROM.

  Next, a photographing operation including a beat noise reduction process will be described with reference to FIG. FIG. 13 is a flowchart showing a control procedure of the photographing operation including beat noise reduction processing by the control unit 121 of FIG.

  At the time of shooting, as shown in FIG. 13, the control unit 121 activates the EVF (step S101). Here, the reference timing clock MCLK when the EVF is activated is output from the multi-output clock generation circuit 110. Then, the control unit 121 waits for the switch SW2 to be turned on according to the operation of the shutter switch 124 by the user (step S102). Here, when the switch SW2 is turned on, the control unit 121 performs exposure for actual photographing (step S103).

  Next, the control unit 121 starts reading from the first, second, and third fields. First, the control unit 121 switches to the driving frequency for the first field (step S104). Here, the control unit 121 controls the multi-output clock generation circuit 110 so as to output the reference timing clock MCLK having the same frequency as the drive frequency set for the first field. Then, the control unit 121 refers to the phase information and generation timing information stored in the ROM, and sets the phase and generation timing of the imaging pulse corresponding to the driving frequency of the first field in the timing generation circuit 105 (step) S105). Here, the phases of the imaging pulses, that is, horizontal transfer pulses H1 and H2, reset gate pulse RG, sample hold pulse SHBLK and pulse SHDATA, and sampling pulse CLK are set. Further, in order to make the operation time of the CCD 104 the same for the driving frequencies of the first to third fields, the number of clocks of the exposure time, the reading time, and the vertical transfer time for the driving frequency of the first field are set.

  Next, the control unit 121 controls the timing generation circuit 105 to generate an imaging pulse for reading the first field (step S106). With this control, the timing generation circuit 105 generates each imaging pulse based on the phase and generation timing set by the control unit 121. Then, the CCD sensor 104 and the imaging circuit 130 operate according to each imaging pulse, and the CCD output signal in the first field is read out.

  Next, the control unit 121 switches to the driving frequency of the second field (step S107). Here, the multi-output clock generation circuit 110 is controlled so as to output the reference timing clock MCLK having the same frequency as the drive frequency set for the second field. Then, the control unit 121 refers to the phase information and the generation timing information stored in the ROM, and sets the phase and generation timing of the imaging pulse corresponding to the driving frequency of the second field in the timing generation circuit 105 (step) S108).

  Next, the control unit 121 controls the timing generation circuit 105 to generate an imaging pulse for reading the second field (step S109). By this control, each imaging pulse based on the phase and generation timing set from the timing generation circuit 105 is generated, and the CCD sensor 104 and the imaging circuit 130 operate according to each imaging pulse. As a result, the CCD output signal in the second field is read out.

  Next, the control unit 121 switches to the driving frequency of the third field (step S110). Here, the multi-output clock generation circuit 110 is controlled so as to output the reference timing clock MCLK having the same frequency as the driving frequency set for the third field. Then, the control unit 121 refers to the phase information and the generation timing information stored in the ROM, and sets the phase and generation timing of the imaging pulse corresponding to the driving frequency of the third field in the timing generation circuit 105 (step) S111).

  Next, the control unit 121 controls the timing generation circuit 105 so as to generate an imaging pulse for reading out the third field (step S112). By this control, each imaging pulse based on the phase and the number of clocks set from the timing generation circuit 105 is generated, and the CCD sensor 104 and the imaging circuit 130 operate according to each imaging pulse. Thereby, the CCD output signal in the third field is read out.

  When the images of the first to third fields constituting one frame are thus captured, the control unit 121 ends the main photographing operation (step S113). Subsequently, the control unit 121 switches to the driving frequency when the EVF is activated (step S114). Here, the multi-output clock generation circuit 110 is controlled so as to output the reference timing clock MCLK when the EVF is activated. And the control part 121 returns to said step S101, and operates EVF.

  According to the present embodiment, by setting a driving frequency that makes it difficult to visually recognize a beat noise pattern for each field constituting one frame and switching to a driving frequency corresponding to each field, The pattern can be made difficult to visually recognize.

  In addition, since the drive frequency for each field is a preset frequency, the number of clocks that define the generation timing for making the phase of the imaging pulse for each drive frequency and the operation time of the CCD 104 the same is prepared in advance. Can do. As a result, it is possible to easily adjust the phase of the imaging pulse for each drive frequency.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 14 is a diagram schematically illustrating an image that has been subjected to beat noise reduction processing at the time of thinning readout in the imaging apparatus according to the second embodiment of the present invention. FIG. 15 is a timing chart based on the field vertical synchronizing signal VD including the exposure period B of FIG. FIG. 16 is a flowchart showing a thinning readout control procedure during EVF by the control unit of the imaging apparatus according to the second embodiment of the present invention. FIG. 17 is a diagram schematically showing beat noise appearing in an image read by thinning readout.

  The present embodiment has the same configuration as the first embodiment, and the same reference numerals as those of the first embodiment are used in the description of the present embodiment.

  In the present embodiment, beat noise reduction processing is performed at the time of thinning-out reading as in the case of frame reading. The thinning readout is as described with reference to FIG. 5 in the first embodiment, and the description thereof is omitted. In thinning-out reading, a predetermined unit section for obtaining a signal indicating an image for one field is defined by the vertical synchronization signal VD. Therefore, when the drive frequency of the imaging circuit 130 is switched in accordance with the timing of the vertical synchronization signal VD, the beat pattern changes for each screen.

  Here, it is assumed that the 36 MHz reference main clock MCLK is output from the multi-output clock generation circuit 110 and the 30 MHz clock LCD is output from the LCD clock generation circuit 114. In this case, the imaging circuit 130 operates at a driving frequency of 36 MHz, and the LCD 115 operates at a frequency of 30 MHz. When the reference main clock MCLK and the clock LCD interfere with each other, beat noise having a differential frequency component of 6 MHz appears in the image of each field read by thinning readout. For example, in the first, second, and third fields, bead noise appears in a pattern as shown in FIGS. 17 (a), (b), and (c). In the first field, since the frequency component of beat noise is 6 MHz, the beat noise appears in 6 clock cycles (36 MHz / 6 MHz), that is, 6 pixel cycles with respect to the reference timing clock MCLK. Also, in the second and third fields, the beat noise frequency component does not change, so beat noise appears in the same pattern. That is, in each field, the appearance of beat noise is repeated with the same pattern, and this beat noise pattern is easily visible.

  Therefore, in the present embodiment, the driving frequency of the image pickup circuit 130 is switched in three consecutive fields, and the switching of the driving frequency is repeatedly performed at a period in which the three fields are one cycle. The drive frequency to be switched for each field is set in advance to a frequency at which the appearing beat noise pattern is difficult to visually recognize.

  For example, a driving frequency of 35 MHz is set for the first field, 33 MHz for the second field, and 32 MHz for the third field. The frequency components of beat noise for each field are 5 MHz (35 MHz-30 MHz), 3 MHz (33 MHz-30 MHz), and 2 MHz (32 MHz-30 MHz). That is, in the first field, beat noise occurs in a cycle of 7 pixels (35 MHz / 5 MHz), in the second field, 11 pixel cycles (33 MHz / 3 MHz), and in the third field, a cycle of 2 pixels (32 MHz / 2 MHz). Appears. In the fourth field, since the drive frequency of the field is the same as the drive frequency of the first field, beat noise appears in a cycle of 7 pixels (35 MHz / 5 MHz).

  Thus, the present embodiment weakens the bead noise spectrum by switching the driving frequency for each of the three fields. This point is the same as in the first embodiment. However, since the beat noise pattern changes for each field (one screen), it is necessary to make it difficult to visually recognize the beat noise pattern appearing in each field when the continuous field (screen) is visually recognized. This is different from the embodiment.

  In the present embodiment, the driving frequency is switched for three fields, but the driving frequency is set for four or more fields so that the beat noise pattern is less noticeable. May be switched.

  Next, the setting of the imaging pulse generation timing for making the operation time of the CCD 104 the same in the thinning readout will be described with reference to FIG.

  First, the setting for making the exposure time the same will be described. For example, as shown in FIG. 15, it is assumed that the drive frequency for the field including the exposure period B in FIG. 5 is f (MHz) and the exposure period B is time t (usec). Further, the time from when the last electronic shutter pulse in the horizontal synchronization signal HD per line is output until the horizontal synchronization signal HD becomes L (Low) is a time corresponding to b (clock). To do. Further, the number of lines from the last electronic shutter pulse output to the next electronic shutter pulse output (the number of horizontal synchronization signals HD) is c (Line). The output period of the horizontal synchronization signal HD per line is y (clock / Line). In this case, the time t is expressed by the following relational expression.

t = b × 1 / f + c × y × 1 / f
Here, regarding the field including the exposure period C shown in FIG. 5, when the exposure period C is set to be the same as the time t, that is, the same as the exposure period B, the time b and the number of lines are set according to the drive frequency f. c, The output period y of the horizontal synchronization signal HD may be calculated. However, in this case, it is realistic to perform adjustment by adding a dummy clock or a dummy line so as not to affect other times such as a read time and a transfer time.

  In order to make the operating time of the CCD sensor 104 the same, it is preferable to adjust the operating time of the CCD sensor 104 with respect to the field having the highest driving frequency with reference to the field having the lowest driving frequency. This is because the field with a high driving frequency has a short period of one clock, and therefore fine adjustment can be performed effectively.

  Since the setting for making the vertical transfer time and the read time the same is the same as that in the first embodiment, the description thereof is omitted here.

  In this way, the variables (the time b, the number of lines c, the output period y of the horizontal synchronization signal HD, etc.) defining the generation timing for making the operation time of the CCD sensor 104 the same are calculated in advance. Information is stored in the ROM of the control unit 121.

  Further, the ROM of the control unit 121 stores information indicating the driving frequency for each field in thinning readout and phase information indicating the phase of the imaging pulse for each driving frequency.

  Next, the thinning readout control during EVF operation by the control unit 121 will be described with reference to FIG.

  When the EVF is activated, as shown in FIG. 16, the control unit 121 first switches to the driving frequency for the first field (step S201). Here, the control unit 121 controls the multi-output clock generation circuit 110 so as to output the reference timing clock MCLK having the same frequency as the drive frequency set for the first field. Then, the control unit 121 refers to the phase information and generation timing information stored in the ROM, and sets the phase and generation timing of the imaging pulse corresponding to the drive frequency of the first field in the timing generation circuit 105 ( Step S202). Here, the phases of the imaging pulses, that is, horizontal transfer pulses H1 and H2, reset gate pulse RG, sample hold pulse SHBLK and pulse SHDATA, and sampling pulse CLK are set. Also, generation timings for defining the exposure time, read time, and vertical transfer time for the drive frequency of the first field are set.

  Next, the control unit 121 controls the timing generation circuit 105 so as to generate an imaging pulse for reading the first field (step S203). With this control, each imaging pulse based on the phase and generation timing set by the control unit 121 is generated from the timing generation circuit 105, and the CCD sensor 104 and the imaging circuit 130 operate according to each imaging pulse. As a result, the CCD output signal of the first field is read out.

  Next, the control unit 121 performs switching to the driving frequency of the second field (step S204). Here, the multi-output clock generation circuit 110 is controlled so as to output the reference timing clock MCLK having the same frequency as the drive frequency set for the second field. Then, the control unit 121 refers to the phase information and generation timing information stored in the ROM, and sets the phase and generation timing of the imaging pulse corresponding to the driving frequency of the second field in the timing generation circuit 105 ( Step S205).

  Next, the control unit 121 controls the timing generation circuit 105 to generate an imaging pulse for reading the second field (step S206). By this control, each imaging pulse is generated based on the phase and generation timing set from the timing generation circuit 105, and the CCD sensor 104 and the imaging circuit 130 operate according to each imaging pulse. As a result, the CCD output signal of the second field is read out.

  Next, the control unit 121 performs switching to the driving frequency of the third field (step S207). Here, the multi-output clock generation circuit 110 is controlled so as to output the reference timing clock MCLK having the same frequency as the driving frequency set for the third field. Then, the control unit 121 refers to the phase information and generation timing information stored in the ROM, and sets the phase and generation timing of the imaging pulse corresponding to the driving frequency of the third field in the timing generation circuit 105 ( Step S208).

  Next, the control unit 121 controls the timing generation circuit 105 to generate an imaging pulse for reading out the third field (step S209). By this control, each imaging pulse is generated based on the phase and generation timing set from the timing generation circuit 105, and the CCD sensor 104 and the imaging circuit 130 operate according to each imaging pulse. As a result, the CCD output signal of the third field is read out.

  Next, the control unit 121 determines whether or not to read from the fourth field (step S210). If it is determined that reading from the fourth field is to be performed, the control unit 121 sets the fourth field as the first field and returns to step 201. On the other hand, the case where it is determined that reading from the fourth field is not performed is, for example, a case where another operation mode in which the EVF is not operated is selected. In this case, the control unit 121 shifts to control for executing the selected operation mode.

  Thus, it is possible to make it difficult to visually recognize the beat noise pattern even when the EVF is activated.

  In the present embodiment, the beat noise reduction process in the thinning readout when the EVF is activated has been described. However, the same beat noise reduction process can be applied to the case where the thinning readout is performed during moving image recording. In this case, the bead noise generated when viewing the recorded image can be weakened, and the beat noise or its pattern can be made difficult to visually recognize.

1 is a block diagram illustrating a configuration of an imaging apparatus according to a first embodiment of the present invention. It is a figure which shows the pixel area | region of the CCD sensor 104 of FIG. It is a figure which shows frame reading typically. It is a figure which shows thinning-out reading typically. 6 is a timing chart of a pixel reading operation from the CCD sensor 104. FIG. 6 is a timing chart showing the relationship between an electrical signal output from the CCD sensor 104 and each imaging pulse. It is a figure which shows typically the state in which beat noise appeared in the image obtained by this imaging | photography (image obtained by frame reading). It is the figure which expanded the component of the imaging clock, LCD clock, and beat noise on the frequency axis. It is a figure which shows typically the image which made it difficult to visually recognize the pattern of beat noise by the beat noise reduction process in the 1st Embodiment of this invention. It is a figure which shows each drive frequency in case it is difficult to visually recognize the pattern of beat noise, the frequency of beat noise, and each spectrum. It is a figure which shows each drive frequency when the pattern of beat noise is easy to visually recognize, the frequency of beat noise, and each spectrum. 6 is a timing chart based on a horizontal synchronization signal HD in a second field in a period A in FIG. 5. It is a flowchart which shows the control procedure of the imaging | photography operation | movement containing the beat noise reduction process by the control part 121 of FIG. It is a figure which shows typically the image in which the beat noise reduction process at the time of thinning-out reading was performed in the imaging device which concerns on the 2nd Embodiment of this invention. 6 is a timing chart based on a field vertical synchronization signal VD including an exposure period B in FIG. It is a flowchart which shows the control procedure of the thinning-out reading at the time of EVF by the control part of the imaging device which concerns on the 2nd Embodiment of this invention. It is a figure which shows typically the beat noise which appears in the image read by the thinning-out reading.

Explanation of symbols

104 CCD sensor 105 Timing signal generation circuit 106 CDS circuit 107 PGA circuit 108 Clamp circuit 109 AD conversion circuit 110 Multi-output clock generation circuit 111 Video processing circuit 130 Imaging circuit

Claims (6)

Clock generation means;
Timing signal generating means for generating a timing signal including a vertical synchronizing signal for controlling the image sensor in accordance with the clock generated by the clock generating means;
An imaging apparatus comprising: control means for switching a frequency of a clock generated by the clock generation means in synchronization with the vertical synchronization signal. Different frequencies are set in association with a plurality of fields constituting one frame,
The control unit switches the frequency of the clock generated by the clock generation unit to a frequency associated with the field to be read when the image is divided and read from the image sensor into the plurality of fields. The imaging device according to claim 1.   The imaging apparatus according to claim 2, wherein the control unit repeats the switching of the frequency in a cycle in which the plurality of continuous fields are one cycle when sequentially reading the plurality of continuous fields. Processing means for performing processing for converting the output signal of the imaging element into an imaging signal;
The timing signal generating means generates a timing signal for controlling the operation of the processing means,
The control means sets the phase of the timing signal for controlling the operation of the image sensor and the phase of the timing signal for controlling the operation of the processing means for each frequency in the timing signal generating means. The imaging apparatus according to any one of claims 1 to 3, wherein   The control means sets, in the timing signal generation means, a generation timing for making the operation time of the image sensor the same for each frequency with respect to the timing signal for controlling the operation of the image sensor. The imaging device according to any one of claims 1 to 4. A method for controlling an imaging apparatus having an imaging element and a clock generation means,
Generating a timing signal including a vertical synchronization signal for controlling the imaging device according to the clock generated by the clock generation means;
And a step of switching a frequency of a clock generated by the clock generation means in synchronization with the vertical synchronization signal.

Images