JP2005079881A - Digital camera apparatus, method for correcting image display deviation, computer program, and computer-readable recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid using of an unnecessary memory for preventing a phenomenon in which images for 2 frames of different timing are mixed and displayed in the same display image due to asynchronous clocks, and to prevent the phenomenon by simple control. <P>SOLUTION: A picture input means 100 has its timing controlled based on a first clock means 107, and inputs a picture from CCD in real time. An image display means 114 has its timing controlled based on a second clock means 111 asynchronous with the first clock means 107, and displays the input image in real time. A detection means detects deviation between the period of image input by the means 100 and the period of image display by the means 114 (steps S410 and S420). When the deviation detected by the detection means exceeds a prescribed range, a deviation adjusting means suppresses the deviation by changing the period of the image input means or the image display means (steps S430, S440 and S450). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a digital camera device in which an image input timing and an image display timing are controlled by an asynchronous clock, an image display displacement correction method, a computer program, and a computer-readable recording medium.

  In an apparatus in which an image is input / output by an asynchronous clock, the timing of the frame gradually shifts because the 1 frame period on the input side and the output side do not match due to variations in the oscillator. There is a problem in that images taken at different timings are displayed at the top and bottom. In order to solve this problem, for example, in Patent Document 1, a buffer for temporarily storing an image has a triple buffer configuration.

JP-A-6-105290

  However, in the conventional example, the buffer for temporarily storing the image is configured as a triple buffer, so that a problem that the required memory size becomes large, the control of buffer switching becomes complicated, and the burden of software becomes large. There was a problem of becoming.

  The digital camera device of the present invention has an image input means for inputting the image from the CCD in real time and a second clock means asynchronous with the first clock means, the timing of which is controlled based on the first clock means. Based on the image display means for displaying the input image in real time, the detection means for detecting a shift in the image input period by the image input means and the image display period by the image display means, and the detection When the deviation detected by the means exceeds a predetermined range, there is provided a deviation adjusting means for changing the period of the image input means or the image display means to suppress the deviation.

  According to the image display misalignment correction method of the present invention, the timing is controlled based on the first clock means, the image input processing for inputting the image from the CCD in real time, and the second clock which is asynchronous with the first clock means. Detection that detects a deviation between an image display process in which the timing is controlled based on a clock means and the input image is displayed in real time, an image input period in the image input process, and an image display period in the image display process When the deviation detected by the processing and the detection process exceeds a predetermined range, either the image input period in the image input process or the image display period in the image display process is changed to suppress the deviation. And an adjustment process.

According to the computer program of the present invention, the timing is controlled based on the first clock means, the image input processing for inputting the image from the CCD in real time, and the second clock means asynchronous with the first clock means. An image display process in which the timing is controlled on the basis of the input image and the input image is displayed in real time; a detection process of detecting a shift between an image input period in the image input process and an image display period in the image display process;
A shift adjustment process for suppressing a shift by changing either the image input cycle in the image input process or the image display cycle in the image display process when the shift detected by the detection process exceeds a predetermined range; It is characterized by having a computer execute.

  The computer-readable recording medium of the present invention is characterized by recording the computer program described above.

  As described above, according to the present invention, since the shift of the input / output frame period caused by the asynchronous clock is detected, and the means for correcting the detected shift is provided, images of two frames having different timings can be obtained. The extra memory provided to prevent the phenomenon of being mixed and displayed in the same display image can be omitted, and the disadvantage that different images are displayed on the upper and lower parts of the screen in the same frame period can be simplified. It can be prevented by control.

Exemplary embodiments of a digital camera device, an image display misalignment correction method, a computer program, and a computer-readable recording medium according to the present invention will be described below in detail with reference to the accompanying drawings.
[First Embodiment]
FIG. 1 is a block diagram showing a schematic configuration of a digital camera apparatus according to the first embodiment of the present invention.
In FIG. 1, reference numeral 100 denotes a camera unit, which includes a lens group 101, a CCD 102, a CDS 103, an ADC 104, a digital image processing unit 105, a TG (timing generator) 106, and a TG oscillator 107.

  The optical image input from the lens group 101 is converted into an electrical signal by the CCD 102, subjected to noise removal processing by correlated double sampling in the CDS 103, and then converted from an analog signal to a digital signal by the ADC 104. Digital image processing is applied. The TG 106 is a timing generator that generates a signal for controlling the processing timing of the CCD 102, the CDS 103, and the ADC 104 based on the clock output of the TG oscillator 107.

  A CPU 110 controls each device based on an input from the key SW 112 to control the camera unit 100 and display data on the TFT liquid crystal display unit 114. In addition to the so-called microprocessor, the CPU 100 is a so-called SOC (system on chip) in which logic such as a memory controller for controlling an external memory such as the program memory 116 and the work memory 115 is incorporated.

  The work memory 115 is a work memory that is connected by a memory bus and used as a work area of the CPU 110, and is composed of SRAM, SDRAM, or the like. The program memory 116 is a memory that is connected by a memory bus and stores a control program for controlling the device and font data, and includes a flash memory, a mask ROM, and the like. Reference numeral 117 denotes a CF card which is a storage means connected via a memory bus with a dedicated connector.

  Reference numeral 118 denotes a buffer memory composed of an SDRAM or the like for storing two frames of images sent from the camera unit 100 in real time and displaying them on the TFT liquid crystal display unit 114 in real time. Reference numeral 113 denotes a display control circuit that receives RGB signals and synchronization signals from the CPU 110 and generates and outputs signals for displaying an image on the TFT liquid crystal display unit 114.

  Reference numeral 114 denotes a TFT-type liquid crystal display having a VGA (video graphics array) size. Reference numeral 112 denotes a key SW for detecting various control SWs such as a shutter SW and a mode SW. Reference numeral 111 denotes an oscillator that generates a clock that is a basic operation of the CPU 110, the memory bus, the liquid crystal display control circuit 113, and the like.

  FIG. 2 and FIG. 3 are timing explanatory diagrams showing examples of read / write timings to the display buffer 118 when an image from the camera unit 100 is displayed on the liquid crystal display unit 114 in real time in the present embodiment.

  The CCDVD signal is a signal generated by counting the number of pixels in the horizontal direction and the number of lines in the vertical direction of the CCD 102 by the TG 106 based on the clock from the oscillator 107, and controls the start timing of one frame image from the CCD 102. This is a vertical synchronizing signal with a period of / 30 seconds. The CCDWR represents the timing at which the image captured from the CCD 102 is written into the display buffer 118 through the CPU 110.

  The image data sent continuously is alternately stored in the two-frame buffer of the display buffer 118 in synchronization with the CCDVD signal. In FIG. 2, a portion where the CCDWR does not change is an invalid area such as a portion called an optical black of the CCD 102, which is a period during which no data is written in the buffer.

  The LCDVD signal is a signal generated by the CPU 110 based on the clock from the oscillator 111 and is a 1/60 second period vertical synchronization signal that controls the timing for displaying an image on the TFT liquid crystal display unit 114. LCDRD represents the timing for reading data from the display buffer 118 for liquid crystal display. The TFT liquid crystal display of this embodiment is displayed by a method called an interlaced format, and is divided into two fields every other line.

  Each field is sequentially read from the same buffer in the order of f0 and f1 in synchronization with the LCDVD signal to form display data for one frame, and is alternately read from two display buffers for each frame. In FIG. 2, the portion in which LCDRD does not change is called a vertical blanking period. During this period, the display does not change, and data is not read from the buffer.

  Since the CCDVD signal has a 1/30 second period and the LCD signal has a 1/60 second period, the relationship between the CCDWR timing and the LCDRD timing is kept constant as long as it is controlled by a completely synchronized clock. Therefore, the LCD display data can always be read from a buffer different from the buffer in which the data from the CCD is written.

  However, when the CCDVD signal and the LCDVD signal are generated based on different oscillators, even if the error is slight, it is slightly shifted. FIG. 2 and FIG. 3 show the state. FIG. 2 shows an example in which the CCDVD cycle is shorter, and FIG. 3 shows an example in which the CCDVD cycle is longer. Note that the figure is considerably deformed for the convenience of explanation, and does not coincide with the actual timing.

  FIG. 2 (a) is a diagram for explaining a problem that occurs when input / output to the buffer is continued with out-of-synchronization, and the timings of CCDVD and LCDVD coincide with each other at the left end. CCDWR and LCDRD are performed on the same Buf_1 at the mark *.

  Normally, in this state, the reading of the LCDRD is followed by the writing of the CCDWR, and it still does not appear as a malfunction, but the order of writing to the buffer and the order of reading from the buffer are reversed because of the case where the upside down function is implemented. If there is, the frame data becomes old frame data until the middle of reading, and becomes new frame data from the middle, resulting in a shift at the top and bottom of the screen. Also, even if the writing and reading directions are the same, if the deviation increases as it is, new frame data will appear until the middle of reading, and old frame data will appear halfway, resulting in a deviation at the top and bottom of the screen. .

  FIG. 2B is an explanatory diagram of timing when the above-described problem is solved by the present embodiment. For each LCDVD signal interrupt (timing indicated by the arrow in the figure) at the start of the LCDRD f1 field, the deviation amount is determined by reading the line number of the counter in the vertical direction of the TG generating the CCDVD. To detect.

  When this value is larger than the predetermined number of lines, the register for indicating the upper limit of the line count number for generating the next CCDVD is increased, thereby delaying the writing timing from the CCD in the next field to the buffer. The shift amount of the predetermined number of lines needs to be set shorter than the time corresponding to the vertical blanking period of the LCD.

  In FIG. 2B, it is detected that the deviation is larger than the prescribed deviation at the timing of the third arrow, and control is performed to delay the timing of writing the next CCD to Buf_1.

  FIG. 3 shows the reverse case of FIG. 2, and (c) shows that input / output to the same buffer is performed at the mark * when the display is continued without correcting the deviation, and at the timing of the arrow in FIG. 3 (d). It is detected whether the counter of the number of lines of the CCD is smaller than the predetermined number of lines, and if it is smaller than the predetermined number of lines, the register indicating the upper limit of the line count number for generating the next CCDVD is decreased. As a result, the write timing from the CCD in the next field to the buffer is advanced. The deviation amount of the predetermined number of lines needs to be set shorter than the time corresponding to the invalid area of the CCD.

  In FIG. 3D, it is detected that the deviation is larger than the prescribed deviation at the timing of the second arrow, and control is performed so as to advance the timing of writing the next CCD to Buf_2.

FIG. 4 is a flowchart showing a processing procedure at the time of interruption due to generation of an LCDVD signal.
In the first step S400, it is determined whether the fD field start VD interrupt or the f0 field start VD interrupt. If it is f0, the interrupt process is terminated without doing anything. On the other hand, if it is f1, it will progress to step S410 and it will be determined whether the number of CCD lines is smaller than predetermined N1 line. If the result of this determination is negative, the process proceeds to step S430 to delay the generation of the next VD signal, and a numerical value that is 2 lines larger than the standard is set as the number of MAX lines of the CCD.

  On the other hand, if it is determined in step S400 that the number of CCD lines is equal to or greater than the predetermined N1 line, the process proceeds to step S420, where it is determined whether the number of CCD lines is greater than the predetermined N2 line. In order to speed up the occurrence of this, the process proceeds to step S450, and a numerical value smaller by 2 lines than the standard is set as the number of MAX lines of the CCD. The detection means is constituted by the steps S410 and S420.

  If it is determined in step S42 that the number of CCD lines is not less than a predetermined N1 line and not more than a predetermined N2 line, the process proceeds to step S440, and a standard numerical value is set as the number of MAX lines of the CCD. Steps S430, S440, and S450 constitute an adjusting unit.

[Second Embodiment]
In the first embodiment described above, the shift between CCDVD and LCDVD is corrected by adjusting the cycle of CCDVD. However, in the present embodiment, the shift of the shift is made by adjusting the cycle of LCDVD. Make corrections.

  FIG. 5 and FIG. 6 are timing explanatory diagrams showing timing examples of reading and writing to the display buffer 118 when an image from the camera unit 100 is displayed on the liquid crystal display unit 114 in real time in the present embodiment. FIG. 5E is the same as FIG. 2A of the first embodiment. (F) eliminates the problem in FIG. 5 (e) according to the present embodiment.

  In the present embodiment, the amount of deviation is detected by reading the number of the counter in the vertical direction of the TG generating the CCDVD at the timing indicated by the arrow in FIG. When this value is larger than the predetermined number of lines, the display timing of the next field is advanced by decreasing the register indicating the upper limit of the line count number for generating the next LCDVD. The shift amount of the predetermined number of lines needs to be set shorter than the time corresponding to the vertical blanking period of the LCD. In (f) of FIG. 5, it is detected that the deviation is larger than the prescribed deviation at the timing of the second arrow, and control is performed so as to advance the next display timing.

FIG. 6G is the same as FIG. 3C of the first embodiment. (H) of FIG. 6 eliminates the problem in (g) by this embodiment.
It is detected whether the CCD line number counter is smaller than the predetermined number of lines at the timing of the arrow in FIG. 6H, and if it is smaller than the predetermined number of lines, the line for generating the next LCDVD is detected. The display timing of the next field is delayed by increasing the register indicating the upper limit of the count number. The deviation amount of the predetermined number of lines needs to be set shorter than the time corresponding to the invalid area of the CCD.

  In FIG. 6 (h), it is detected that the deviation is larger than the prescribed deviation at the timing of the third arrow, and the next display timing is controlled to be delayed.

[Third Embodiment]
In the first embodiment described above, the amount of shift between the LCD and CCD cycles is detected by checking the CCD line count at the LCDVD interrupt timing, but in this embodiment, the CCDVD interrupt count is detected. The period deviation is detected by checking the current field and line count number of the LCD at the timing.

FIG. 7 is a flowchart showing a processing procedure at the time of interruption due to CCDVD signal generation.
When the process is started, in the first step S700, it is checked whether the current reading field of the LCD is f0 or f1. If the result of this check is f0, the process proceeds to step S710, and if it is f1, the process branches to step S720.

  In step S710, the current LCD read line count is checked, and if it is greater than a predetermined N4, a numerical value that is two lines smaller than the standard is set in step S750 in order to advance the generation timing of the next CCDVD signal. . If it is equal to or less than the predetermined N4, a standard numerical value is set as the number of MAX lines of the CCD in step S740.

  On the other hand, if the process branches to step S720, the current LCD read line count number is checked, and if it is smaller than the predetermined line count number N3, in order to delay the generation timing of the next CCDVD signal, in step S730, the CCD MAX Set the number of lines 2 numbers larger than the standard. If it is equal to or greater than the predetermined N3, a standard numerical value is set as the number of MAX lines of the CCD in step S740.

It is a block diagram which shows the structure of the digital camera apparatus which concerns on the 1st Embodiment of this invention. It is a figure which shows the timing of the input-output signal which concerns on the 1st Embodiment of this invention. It is a figure which shows the timing of the input-output signal which concerns on the 1st Embodiment of this invention. It is a flowchart which shows the process at the time of the vertical-synchronization interruption of LCD which concerns on the 1st Embodiment of this invention. It is a figure which shows the timing of the input-output signal of the digital camera apparatus which concerns on the 2nd Embodiment of this invention. It is a figure which shows the timing of the input-output signal of the digital camera apparatus which concerns on the 2nd Embodiment of this invention. 12 is a flowchart illustrating processing at the time of CCD vertical synchronization interrupt in the digital camera device according to the third embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Camera part 106 Timing generator 107 CCD input timing oscillator 110 CPU
111 Oscillator for CPU operation and LCD display timing 114 TFT liquid crystal display 118 Display buffer

Claims (12)

Image input means for controlling the timing based on the first clock means and inputting an image from the CCD in real time;
Image display means for controlling the timing based on a second clock means asynchronous with the first clock means and displaying the input image in real time;
Detecting means for detecting a deviation between an image input period by the image input means and an image display period by the image display means;
A digital camera apparatus comprising: a shift adjustment unit that suppresses a shift by changing a cycle of the image input unit or the image display unit when the shift detected by the detection unit exceeds a predetermined range. .   The detection means is activated in synchronization with a cycle of the image display means, and detects a shift of an image display cycle by reading a line number of an image input by the image input means. The digital camera device according to 1.   The detection unit is activated in synchronization with a cycle of the image input unit, and detects a shift in an image display cycle by reading a line number of an image displayed by the image display unit. Item 4. The digital camera device according to Item 1.   The digital camera apparatus according to claim 1, wherein the adjustment unit adjusts a shift of an image display cycle by changing a cycle of the image input unit.   The digital camera apparatus according to claim 1, wherein the adjustment unit adjusts a shift in an image display cycle by changing a cycle of the image display unit. An image input process for controlling the timing based on the first clock means and inputting an image from the CCD in real time;
Image display processing in which timing is controlled based on second clock means asynchronous with the first clock means, and the input image is displayed in real time;
A detection process for detecting a shift between an image input period in the image input process and an image display period in the image display process;
A shift adjustment process for suppressing a shift by changing either the image input cycle in the image input process or the image display cycle in the image display process when the shift detected by the detection process exceeds a predetermined range; An image display misalignment correction method comprising:   The detection processing starts processing in synchronization with an image display cycle in the image display processing, and detects a shift in the image display cycle by reading a line number of the image during the image input processing. Item 7. The image display misalignment correction method according to Item 6.   The detection processing starts processing in synchronization with the image input cycle in the image input processing, and detects a shift in the image display cycle by reading a line number of the image during the image display processing. The image display misalignment correction method according to claim 6.   The image display deviation correction method according to claim 6, wherein the adjustment process adjusts a deviation of an image display period by changing an image input period in the image input process.   The image display deviation correction method according to claim 6, wherein the adjustment process adjusts a deviation of an image display period by changing an image display period in the image display process. An image input process for controlling the timing based on the first clock means and inputting an image from the CCD in real time;
An image display process in which the timing is controlled based on a second clock means asynchronous with the first clock means, and the input image is displayed in real time;
A detection process for detecting a shift between an image input period in the image input process and an image display period in the image display process;
A shift adjustment process for suppressing a shift by changing either the image input cycle in the image input process or the image display cycle in the image display process when the shift detected by the detection process exceeds a predetermined range; A computer program for causing a computer to execute.   A computer-readable recording medium having recorded thereon the computer program according to claim 11.

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