JP4984630B2 - Video signal converter - Google Patents

Description

  The present invention relates to a video signal converter for converting an asynchronous video signal such as NTSC, and more particularly to a technique for converting the format of image data obtained from the video signal.

  Conventionally, in an information processing terminal such as a personal computer or a car navigation system, a video display processor has been used as an image processing device responsible for video output. According to this video display processor, a video signal such as NTSC or PAL is captured and displayed on a monitor, and an OSD (On Screen Display) function for drawing an image of various setting values by overlapping the video. Can be easily realized (see Patent Documents 1 to 3).

  In the video display processor described above, an input video signal conforming to NTSC or the like input from the outside is decoded and, for example, ITU-R BT. After generating image data in a format conforming to 601, this is converted into ITU-R BT. The format is converted into image data compliant with 656, and the video display processor has a built-in video signal converter.

By the way, when performing the above-described format conversion, it is necessary to synchronize the operation of the video signal conversion apparatus with the synchronization signal of the input video signal. This will be described with reference to FIG.
The luminance data Y and color difference data Cb, Cr shown in the upper part of FIG. 7 are ITU-R BT. 601 is image data in a format conforming to 601. ITU-R BT. According to 601, the image data is configured as two series of parallel data of luminance data Y and color difference data Cb, Cr, the frequency of the luminance data Y is defined as 13.5 MHz, and the frequency of the color difference data Cb, Cr is the luminance. It is defined as 6.75 MHz corresponding to half the frequency of data Y.

  By defining the frequencies of the luminance and color difference components in this way, one set of color difference data (for example, Cb1 and Cr1 in FIG. 7) is associated with the two luminance data (for example, Y1 and Y2 in FIG. 7). Therefore, the luminance data Y is switched for each pixel, and the color difference data Cb and Cr are switched once every two pixels. Such setting of each frequency is based on human visual characteristics. That is, human vision is sensitive to luminance, but insensitive to color differences, and it is not necessary to switch color differences pixel by pixel.

The image data DA shown in the middle of FIG. 7 is ITU-R BT. 656-compliant format image data, and the ITU-R BT. This is data obtained by normal format conversion of image data compliant with 601. As shown in this example, the converted image data DA is configured as serial data of luminance data Y and color difference data Cb, Cr, and the frequency is defined as 27 MHz corresponding to twice the frequency of luminance data Y. Yes.
The image data DB shown in the figure is an example when the format conversion is not normally performed, which will be described later.

  As described above, when the frequency of each image data satisfies the standard value, the ITU-R BT. The parallel image data compliant with 601 is ITU-R BT. The format is correctly converted into serial image data conforming to 656. Therefore, the video signal conversion apparatus responsible for format conversion needs to operate synchronously with the synchronization signal of the input video signal.

FIG. 8 shows an example of the configuration of a video signal conversion apparatus that operates in synchronization with the above-described input video signal synchronization signal.
In FIG. 8, luminance data Y, color difference data Cb, Cr, and synchronization signal S are ITU-R BT. This is obtained by decoding the input video signal according to 601. This video signal conversion apparatus includes a PLL (Phase Locked Loop) 801 that generates a clock CLK synchronized with a synchronization signal S, and a FIFO (First-In First) that stores parallel image data including luminance data Y and color difference data Cb and Cr. -Out) 802 and a format conversion circuit 803 that converts the format of the image data.

The operation of this conventional apparatus will be briefly described. Parallel image data including luminance data Y and color difference data Cb and Cr is temporarily stored in the FIFO 802. The format conversion circuit 803 reads the parallel image data stored in the FIFO 802 at the timing of the clock CLK, thereby synchronizing the format conversion operation with the input video signal, and converting the parallel image data into the ITU-R BT. Convert to serial image data in accordance with 656.
JP 2005-257886 A JP 2004-147285 A JP 2005-215252 A

  However, according to the conventional device shown in FIG. 8 described above, a PLL for synchronizing the format conversion operation with the input video signal is required, so that the circuit scale increases correspondingly and the power consumption due to this increases. There is a problem of increasing.

  Further, if the format of the image data of the input video signal is directly converted based on the internal clock without using the PLL, depending on the source of the input video signal, the horizontal section of the display space corresponding to the horizontal scan line (hereinafter, Since a slight difference may occur in each cycle), format conversion may not be performed normally. In other words, if a difference occurs in the cycle of each line of the input video signal, this difference is not reflected in the format conversion operation. Therefore, the import of parallel image data failed during the format conversion, and part of the converted image data May be lost, or conversely, unnecessary data may be added.

  The image data DB shown in FIG. 7 represents an example in which the image data Cb2 is missing when format conversion is performed without using a PLL. In this example, the luminance data Y3 is moved up and arranged in the portion where the color difference data Cb2 is missing, and the subsequent order of the luminance data Y and the color difference data Cb and Cr is advanced. For this reason, the phenomenon that the output timing of the luminance data Y after the format conversion and the color difference data Cb, Cr is reversed occurs, and the image of the line where the phenomenon occurs is disturbed.

  The present invention has been made in view of the above circumstances, and can convert the format of image data based on an asynchronous video signal without requiring a PLL. Even if a difference occurs in the period of each line of the video signal, the image can be converted. An object of the present invention is to provide a video signal conversion apparatus that can prevent disturbance of the image.

The video signal conversion apparatus according to the present invention counts the data storage means for storing the image data obtained by decoding the video signal, the first clock number corresponding to the horizontal section of the display space by the video signal, Error acquisition means for acquiring an error of the first clock number with respect to a standard value, and data reading means for reading out the pixel data stored in the storage means for the number of clocks corresponding to the standard value for each line of the display space Format conversion means for converting the format of the image data read from the storage means, and the period of one screen of the video signal and the second clock number corresponding to the entire area of the display space are matched . timing generating means for generating a third display timing of the image data by adjusting the number of clocks corresponding to the non-display region in front Symbol display space Wherein the error acquisition means acquires the error of the first clock speed for the standard value for each line, and accumulating the said error over all lines of the display area in the display space, said timing generating means, said The video signal conversion device adjusts the third clock according to the error accumulated by the error acquisition means .

For example, the timing generating unit, and adjusts the number of clocks of the lead lines of the non-display area in accordance with the clock number of the error corresponding to the horizontal section in the display area. For example, the timing generation unit adjusts the number of clocks of the last line in the non-display area according to an error in the number of clocks corresponding to a horizontal section in the non-display area. For example, the one screen is either a frame or a field.

  According to the present invention, since the display timing is adjusted according to the error in the number of clocks of each line in the display space by the video signal, the format conversion of the image data of the asynchronous video signal can be performed without requiring a PLL. Even if a difference occurs in the period of each line of the video signal, image disturbance can be prevented.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a configuration of an image processing apparatus 200 according to the present embodiment. The image processing apparatus 200 has a function of capturing an image input of an analog video signal AIN or a digital video signal DIN that is an asynchronous video signal such as NTSC and displaying an image in accordance with a display resolution (XGA, SVGA, etc.) An OSD (On Screen Display) image based on a drawing command issued by the CPU 100 and a function for displaying video input on the backdrop surface (hereinafter referred to as “backdrop function”). It has a drawing function (hereinafter referred to as “OSD function”).

In FIG. 1, a CPU interface module 201 mediates data transfer with an external CPU 100. The video memory interface module 202 mediates data transfer with the external video memory 300.
The video decoder unit 203 is a characteristic part of the image processing apparatus 200 and decodes the analog video signal AIN (composite signal) to generate a digital video signal (component signal) of a predetermined format. The image processing apparatus 200 includes two sets of video decoder units 203, which can support two analog video signal inputs. The image processing apparatus 200 has a feature in a signal conversion function when the video decoder unit 203 generates a digital video signal, and details thereof will be described later.

  The video capture controller 204 captures the digital video signal decoded by the video decoder unit 203 and stores it in the video memory 300 as image data of a capture plane. The capture plane controller 205 reads the image data of the capture plane from the video memory 300 and supplies it to the pixel data controller 208.

  The drawing processor unit 206 generates OSD image data based on a drawing command issued from the CPU 100 and stores it in the video memory 300 as image data of the OSD plane. That is, the drawing processor unit 206 draws a straight line or a rectangle as an OSD image in the video memory 300, or performs predetermined processing on the drawn data. The drawing commands issued by the CPU 100 include, for example, a LINE command for drawing a line, a FILL command for painting a rectangular boundary area, and a COPY command for block transfer of data from the video memory to the video memory. However, the type of drawing command is not limited to this. Note that the CPU 100 can also draw directly in the video memory 300 without using a drawing command.

The OSD plane controller 207 reads out OSD plane image data from the video memory 300 and supplies it to the pixel data controller 208.
The pixel data controller 208 synthesizes the image data of the capture plane, the image data of the OSD plane, and the image data of the backdrop surface into image data of one screen and outputs the digital video signal. When combining the image data, the front-rear relationship of each plane on the monitor is adjusted according to the priority order of each plane, or α blending processing (translucent processing) is performed on each plane as necessary. .

In the pixel data controller 208, for example, a total of four planes including two capture planes and two OSD planes and one backdrop plane can be combined. However, the number of each plane is not limited to this and is arbitrary.
Note that the term “plane” indicates that all the configurations necessary to display one rectangular image data in a predetermined size at a predetermined location on the external display device are included, or on the external display device. The supplied image data itself is also shown.

  The DA converter (DAC) 209 converts the digital video signal output from the pixel data controller 208 into an analog signal and supplies it to an external monitor (not shown). When the monitor has a digital input terminal, the digital video signal DOUT output from the pixel data controller 208 is directly supplied to the digital input terminal of the monitor. The CRT controller 210 is for controlling the display scan timing, and generates and outputs a synchronizing signal SOUT for horizontal scanning and vertical scanning. The clock generator 211 generates an operation clock for each block constituting the image processing apparatus 200.

  In the example shown in FIG. 1, the digital video signal output from the video decoder unit 203 is supplied to the pixel data controller 208. As a result, it is possible to display the video based on the digital video signal output from the video decoder unit 203 as it is on the backdrop surface. The image processing apparatus 200 also has an input function of a digital video signal DIN, and this digital video signal DIN is given to the pixel data controller 208 and the video capture unit 204. As a result, like the above-described analog video signal AIN, the digital video signal DIN can be used as it is for display on the backdrop surface, or it can be captured and displayed on the capture plane.

FIG. 2 shows a configuration of the video decoder unit 203 according to the characteristic part of the image processing apparatus.
As shown in the figure, the video decoder unit 203 includes a decoder 203A and a video signal converter 203B. Among these, the decoder 203A is an ITU-R BT. The analog video signal AIN (composite signal) is decoded according to 601. By decoding this, the luminance data Y and the color difference data Cb, Cr are generated, and the horizontal blank signal / HBLANK, vertical blank signal / VBLANK, Each signal of the valid signal VALID and the field signal FIELD is generated.

  Here, the luminance data Y and the color difference data Cb, Cr are ITU-R BT. 601 (YCbCr4: 2: 2), and the frequency of the luminance data Y is 13.5 MHz and the frequency of the color difference data Cb and Cr is 6.75 MHz as shown in FIG. is there. The luminance data Y and the color difference data Cb and Cr are output in parallel from the decoder 203A. The horizontal blank signal / HBLANK is a signal representing a horizontal non-display period in the display space, and is extracted from a horizontal synchronization signal included in the analog video signal AIN. The horizontal blank signal / HBLANK determines the start timing of one line in the display control of the monitor by the image processing apparatus 200.

  The vertical blank signal / VBLANK is a signal representing a vertical non-display period in the display space, and is extracted from the vertical synchronization signal included in the analog video signal AIN. The valid signal VALID is a signal indicating a period during which the luminance data Y and the color difference data Cb and Cr are valid, and is generated by detecting a luminance signal included in the analog video signal AIN, for example. The field signal FIELD is a signal indicating whether the luminance data Y and the color difference data Cb and Cr are image data in the first field or the second field when the analog video signal AIN is an interlaced signal.

  The video signal conversion unit 203B is realized by the video signal conversion device according to the present invention, and includes a write control circuit 2031, a FIFO (First-In First-Out) 2032, a format conversion unit 2033, a clock error acquisition unit 2034, and a read control unit. 2035 and a display timing generation unit 2036. However, the video signal converter 203B may include a decoder 203A.

  Here, the FIFO 2032 temporarily stores parallel image data including the luminance data Y and the color difference data Cb and Cr output from the decoder 203A (data storage means), and is configured by, for example, a dual port RAM. The writing control unit 2031 controls writing of the parallel image data to the FIFO 2032 based on the horizontal blank signal / HBLANK, the vertical blank signal / VBLANK, and the valid signal VALID.

  The clock error acquisition unit 2034 counts the number of clocks (first clock number) corresponding to the horizontal section of the display space by the analog video signal AIN, and acquires an error of the clock number with respect to a predetermined standard value (error acquisition means) ). The read control unit 2035 reads out the ITU-R BT. 601 (YCbCr4: 2: 2) is pixel data (data reading means) for reading out pixel data by a fixed number of clocks corresponding to the standard value.

The format conversion unit 2033 converts the parallel image data read from the FIFO 2032 into ITU-R BT. The format is converted to 27 MHz serial image data conforming to 656 (format conversion means). The display timing generation unit 2036 generates image data display timing by adjusting the number of clocks (third clock number) corresponding to the non-display area in the display space according to the error (timing generation unit).
Note that the display timing generated by the display timing generation unit 2036 is also supplied to the CRT controller 210 shown in FIG. 1, and is used to generate a display scan timing of a monitor (not shown).

  Here, with reference to FIG. 3, the “display space”, “horizontal section”, “display area”, and “non-display area” described above will be described. The example shown in FIG. 3 represents a display space by the analog video signal AIN in the NTSC format. According to this NTSC format, the number of clocks corresponding to the horizontal section is 1716, and the number of lines corresponding to the vertical section is 263 (first number). 1 field) or 262 (second field).

  Further, according to the NTSC format, the horizontal section of the display space is composed of a non-display area for 276 clocks and a display area for 1440 clocks, and the vertical section has a non-display area for 19 lines and 243 lines. (First field) or a display area for 242 lines (second field). The start position of each horizontal line in the display space is based on the falling edge of the horizontal blank signal / HBLANK.

Next, the operation of the image processing apparatus 200 will be described focusing on the video signal conversion unit 203B of the video decoder unit 203 described above.
First, the operation principle of the video signal conversion unit 203B will be described with reference to FIG. 4 and FIG.
Schematically, the video signal conversion unit 203B operates in such a manner that all image data satisfying the standard (ITU-R BT.601) before conversion is sequentially taken into the FIFO, and the format of the image data is converted. As described below, the image data is read out from the FIFO at the generated timing to satisfy the converted standard (ITU-R BT.656). Convert to image data.

  FIG. 4 shows the waveform of the horizontal blank signal / HBLANK output from the decoder 203A. As shown in the figure, the horizontal blank signal / HBLANK is at a low level in the non-display period corresponding to the non-display area in FIG. 3, and is at a high level in the display period corresponding to the display area in FIG. The horizontal blank signal / HBLANK is extracted from the analog video signal AIN by the decoder 203A shown in FIG. 2, and the cycle corresponds to the cycle of each line of the analog video signal AIN.

  Here, when a difference occurs between an operation clock of an external device (not shown) that outputs the analog video signal AIN and an operation clock of the image processing apparatus 200, and a difference occurs in the cycle of each line of the analog video signal AIN, The period of the horizontal blank signal / HBLANK output from the decoder 203A is not constant. In the example shown in FIG. 4, the number of clocks of line 0 is a prescribed 1716 (standard value conforming to the NTSC format), but for line 1, the number of clocks in the non-display period is one clock than the standard value. The number of clocks of the line 1 is reduced to 1715. For the other lines 2 and 3, the number of clocks deviates from the standard value.

When the cycle of the horizontal blank signal / HBLANK varies as described above, the image processing apparatus 200 cannot satisfy the specified number of clocks during format conversion, and the number of clocks of one cycle of the horizontal blank signal / HBLANK is reduced. An error is generated with respect to the standard value, and the image is disturbed. Therefore, in the present embodiment, the length of one period of the horizontal blank signal / H BLANK is counted, and the display timing of the image data is adjusted using the error of the count value (error with respect to the standard value) and the analog video signal Synchronize with AIN.

  FIG. 5A exemplifies an error in the number of clocks of each line due to the fluctuation of the period of the horizontal blank signal / HBLANK described above, and the number of clocks in the entire display space is one screen (frame or frame) of the analog video signal AIN. Field). In this example, the number of clocks of lines 1, 4, 8, and 11 is 1715, which is not less than one standard clock 1716, and the error in the number of clocks in each line is −1 (= 1715). -1716). In this example, lines 0 to 9 correspond to display areas and lines 10 to 12 correspond to non-display areas. However, this is merely an example for explanation, and the present invention is not limited to this. Further, the error in the number of clocks in each line is merely an example, and an error of 2 clocks or more may occur in one line.

  In this embodiment, by forcibly setting the number of clocks of lines 1, 4, and 8 belonging to the display area shown in FIG. 5A to 1716 (standard value), as shown in FIG. Supplement the number of clocks corresponding to the total error. Then, the replenished clock number is subtracted from the clock number in the non-display area. As a result, the number of clocks in the entire display area is set to a standard value, and the number of clocks corresponding to the entire area of the display space is adjusted to the cycle of one screen (frame or field) of the analog video signal AIN.

  In the example of FIG. 5B, the number of clocks added to supplement the error generated in the display area is subtracted from the number of clocks of the first line (line 10) of the non-display area to complement the error generated in the non-display area. By subtracting the number of clocks added to the number of clocks of the last line (line 12) in the non-display area, the total number of clocks is matched with the period of one screen (frame or field) of the analog video signal AIN.

  In this manner, the video signal conversion unit 203B forcibly sets the display timing in the display area to the standard value, and adjusts the increase / decrease in the number of clocks generated thereby by the display timing in the non-display area. Therefore, if image data in the display area is not missing, the image data in the display area can be displayed at a correct display timing according to the standard. Although the display timing of the non-display area is not guaranteed, the non-display area does not appear on the monitor in the first place. Therefore, even if the display timing of the non-display area deviates from the standard value, the image on the monitor does not appear. The operation principle of the video signal conversion unit 203B has been described above.

Next, the operation of the image processing apparatus based on the above principle will be specifically described.
2, the decoder 203A decodes an analog video signal AIN input from the outside, and outputs ITU-R BT. 601 (YCbCr4: 2: 2) compliant image data composed of luminance data Y and color difference data Cb, Cr, and horizontal blank signal / HBLANK, vertical blank signal / VBLANK, valid signal VALID, and field signal FIELD Generate and output. The writing control unit 2031 in the video signal conversion unit 203B sequentially writes the luminance data Y and the color difference data Cb and Cr in the FIFO 2032 based on the horizontal blank signal / HBLANK, the vertical blank signal / VBLANK, and the valid signal VALID.

Here, the image data writing operation to the FIFO 2032 will be described in detail with reference to FIGS. 6A and 6B.
FIG. 6A shows the horizontal blank signal / HBLANK when the number of clocks corresponding to the cycle (one line) of the horizontal blank signal / HBLANK is the standard value 1716, the luminance data Y and the color difference data Cb and Cr, and the valid The relationship with the signal VALID is shown. In this case, the frequencies of the luminance data Y and the color difference data Cb, Cr are standard values, and the period of the valid signal VALID is also constant correspondingly. In this case, the writing control unit 2031 writes the luminance data Y and the color difference data Cb and Cr in the FIFO 2032 during a period when the valid signal VALID is at a high level (that is, a period in which the data is valid).

  On the other hand, FIG. 6B shows the horizontal blank signal / HBLANK when the number of clocks corresponding to the period (one line) of the horizontal blank signal / HBLANK is 1715, which is one clock less than the standard value 1716, and the luminance. The relationship between the data Y and the color difference data Cb and Cr and the valid signal VALID is shown. In this example, since the number of clocks for one line is decreased by one clock, the periods of the luminance data Y718, Y719 and the color difference data Cr359, Cb360 are compressed. As a result, the valid signals corresponding to the luminance data Y718, Y719, Y720 are compressed. The VALID section is continuously maintained at the high level.

  Also in this case, the writing control unit 2031 writes the luminance data Y and the color difference data Cb and Cr in the FIFO 2032 during the period when the valid signal VALID is at the high level. In this example, the periods of the luminance data Y718, Y719 and the color difference data Cr359, Cb360 are compressed. During this period, the valid signal VALID is maintained at a high level, so the luminance data Y718, Y719 and the color difference data Cr359, Cb 360 is normally written in the FIFO 2032. Eventually, the writing of each image data to the FIFO 2032 is normally performed even if the cycle of the horizontal blank signal / HBLANK varies.

  On the other hand, as described with reference to FIGS. 4 and 5, the clock error acquisition unit 2034 counts the number of clocks corresponding to the horizontal section (that is, line) of the display space by the analog video signal AIN and An error in the number of clocks is acquired for each line. Then, the error in the number of clocks acquired for each line in the display area is accumulated over all lines in the display area. The readout control unit 2035 reads out a predetermined number of parallel image data of luminance data Y and color difference data Cb, Cr corresponding to a prescribed number of clocks (1440) from the FIFO 2032 for each line of the display area.

  The display timing generation unit 2036 hides only the number of clocks corresponding to the above error so that the period of one screen (frame or field) of the analog video signal AIN matches the number of clocks corresponding to the entire area of the display space. The display timing of the image data is generated by adjusting the number of clocks corresponding to the area. For example, the display timing generation unit 2036 adjusts the clock number of the first line in the non-display area in accordance with the error in the clock number corresponding to the horizontal section in the display area. Further, the clock number of the last line in the non-display area is adjusted according to the error in the clock number corresponding to the horizontal section in the non-display area.

The format conversion unit 2033 converts the parallel image data read from the FIFO 2032 into ITU-R BT. The format is converted into serial image data of 27 MHz conforming to 656. At this time, the format conversion unit 2033 generates a synchronization code corresponding to the horizontal and vertical synchronization signals using the display timing generated by the display timing generation unit 2036, and embeds this in the serial image data.
In the image processing apparatus 200, the serial image data whose format has been converted as described above is subjected to processing by the capture function and the backdrop function among the OSD function, the capture function, and the backdrop function.

Hereinafter, operations related to the capture function and the back drop function for processing the serial image data whose format has been converted will be described.
(1) Operation related to the capture function In FIG. 1, the capture function is used to display the video input input as the analog video signal AIN in accordance with the display resolution. In this case, the video decoder unit 203 first decodes the analog video signal AIN that is a composite signal and converts it into a digital video signal that is a component signal. The video capture controller 204 captures the digital video signal decoded by the video decoder unit 203 according to the display resolution, and stores the image data obtained by the capture in the video memory 300.

  The capture plane controller 205 reads the image data stored in the video memory 300 as capture plane image data in accordance with the display scan timing, and outputs this to the pixel data controller 208. As described above, the pixel data controller 208 combines the image data on the backdrop surface, the image data on the capture plane, and the image data on the OSD plane into a single image data and outputs it to the monitor.

(2) Operation Related to Backdrop Function In FIG. 1, the pixel data controller 208 selects either the digital video signal DIN or the digital video signal output from the analog video decoder 203 and displays it on the backdrop surface. .
Since the image processing apparatus 200 can process two capture planes and two OSD planes, for example, the images of the two capture planes are displayed side by side on the backdrop surface and overlapped with each other. It is also possible to display two OSD images.

For reference, the operation related to the OSD function will be briefly described.
In FIG. 1, the CPU 100 sequentially issues drawing commands for drawing an OSD image, and writes them in a command port in the drawing processor unit 206. When data necessary for executing the drawing command is written to the command port, the drawing command processing circuit in the drawing processor unit 206 reads the drawing command from the command port and executes it. As a result, OSD image data is generated and stored in the video memory 300.

  The OSD plane controller 207 reads the OSD image data stored in the video memory 300 in accordance with the display scan timing, and supplies this to the pixel data controller 208 as OSD plane image data. As a result, the OSD image is displayed on the monitor so as to overlap the captured video.

As mentioned above, although embodiment of this invention was explained in full detail, the concrete structure is not restricted to this embodiment, The design change etc. of the range which does not deviate from the summary of this invention are included.
For example, in the video signal conversion unit 203B described above, an error in the number of clocks in each line in the display area is accumulated to adjust the count value of the first line in the non-display area. It is good also as what adjusts by.

In addition, although the error in the number of clocks in each line in the non-display area is adjusted in the last line in the non-display area, this adjustment may be omitted as necessary.
Furthermore, in the above-described embodiment, ITU-R BT. 601-compliant ITU-R BT. The case of converting the format to image data conforming to 656 has been described as an example, but the present invention can also be applied to format conversion other than these standards.

1 is a block diagram illustrating a configuration of an image processing apparatus according to an embodiment of the present invention. It is a block diagram which shows the detailed structure of the video decoder unit which concerns on embodiment of this invention. It is explanatory drawing for demonstrating the display space which concerns on embodiment of this invention. It is explanatory drawing for demonstrating the operation principle (when the period of a horizontal blank signal is fluctuate | varied) of the video signal conversion part which concerns on embodiment of this invention. It is explanatory drawing for demonstrating the operation principle (when the error of the clock number in each line is not supplemented) of the video signal conversion part which concerns on embodiment of this invention. It is explanatory drawing for demonstrating the operation | movement principle (when the error of the clock number in each line is supplemented) of the video signal conversion part which concerns on embodiment of this invention. It is explanatory drawing for demonstrating concretely the operation | movement (when the period of a horizontal blank signal is normal) of the video signal conversion part which concerns on embodiment of this invention. It is explanatory drawing for demonstrating concretely the operation | movement (when the period of a horizontal blank signal is fluctuate | varied) of the video signal conversion part which concerns on embodiment of this invention. It is a figure for demonstrating the problem by the video signal converter concerning a prior art. It is a block diagram which shows the structural example of the video signal converter concerning a prior art.

Explanation of symbols

100; CPU, 200; Image processing apparatus, 201; CPU interface module, 202; Video memory interface module, 203; Video decoder unit, 204; Video capture controller, 205; Capture plane controller, 206; Drawing processor unit, 207; Plane controller, 208; Pixel data controller, 209; DA converter, 210; CRT controller, 211; Clock generator, 300; Video memory, 203A; Decoder, 203B; Video signal converter (video signal converter), 2031; Control unit, 2032; FIFO, 2033 format conversion unit, 2034; Clock error acquisition unit, 2035; Read control unit, 2036; Display timing Generating unit.

Claims (4)

Data storage means for storing image data obtained by decoding a video signal;
Error acquisition means for counting a first clock number corresponding to a horizontal section of a display space by the video signal and acquiring an error of the first clock number with respect to a predetermined standard value;
Data reading means for reading out the pixel data stored in the storage means by the number of clocks corresponding to the standard value for each line of the display space;
Format conversion means for converting the format of the image data read from the storage means;
Wherein to one screen period and matching the second clock count corresponding to the entire area of the display space of the video signal, the image by adjusting the third number of clocks corresponding to the non-display region in front Symbol display space Timing generation means for generating data display timing ,
The error acquisition means acquires the error of the first clock number with respect to the standard value for each line, accumulates the error over all lines of the display area in the display space,
The video signal conversion apparatus , wherein the timing generation unit adjusts the third clock according to the error accumulated by the error acquisition unit . It said timing generating means, said display area claim 1 Symbol placement of the video signal conversion device and adjusts the clock number of the lead lines of the non-display area in accordance with the clock number of the error corresponding to the horizontal section of . Said timing generating means, according to claim 1 or 2 or 1, wherein the adjusting the number of clocks of the last line of the non-display region in accordance with the clock number of the error corresponding to the horizontal section in the non-display region The video signal converter according to the item. The one screen, the video signal conversion device according to any one of claims 1 to 3, characterized in that either the frame or field.

Images