JP6021556B2 - Image processing device - Google Patents

Description

  The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus that generates two types of output image data having different numbers of pixels from input image data.

  At present, digital still cameras and digital video cameras are widely used, and opportunities for displaying captured images on a display device such as a display of a television or a personal computer are increasing. In recent years, an imaging device called full HD (horizontal 1920 pixels × vertical 1080 pixels) capable of capturing and recording a high-definition image having a larger number of pixels than the conventional one has also appeared.

  When outputting a captured moving image to an external display device or the like, it is necessary to perform display pixel number conversion separately from recording pixel number conversion processing. Conventionally, each image data constituting a moving image is temporarily stored in a memory, and the recording pixel number conversion circuit and the display pixel number conversion circuit separately access the memory to perform pixel number conversion.

  In addition, in order to perform highly accurate interpolation processing by the pixel number conversion processing, a memory for temporarily storing image data is required. Patent Document 1 describes a configuration for performing pixel number conversion processing using FIFO (First-In First-Out).

JP 2010256604 A

  In the configuration in which the recording pixel number conversion circuit and the output pixel number conversion circuit separately access the memory, there is a problem that the access to the memory is increased, and a higher-speed memory is required.

  If the number of pixels of the moving image to be shot and the number of pixels of the display device are determined, the capacity of the FIFO memory necessary for the interpolation process can be known in advance, and therefore, the minimum necessary FIFO memory may be prepared.

  However, in recent years, it has become necessary to display images with various resolutions on display devices with various display pixels. In addition, the resolution of images to be handled is becoming increasingly multi-pixel. For this reason, it is difficult to convert and output the number of pixels according to such a display device having various numbers of pixels only by providing a FIFO having a predetermined capacity.

  An object of the present invention is to solve such a problem and to provide an image processing apparatus that executes image data processing for recording and output while suppressing access to a memory.

An image processing apparatus according to the present invention includes a memory, processing means for writing moving image data to the memory, read control means for reading the moving image data from the memory, and compressing the moving image data read by the read control means. A compression unit; a conversion unit that takes in the moving image data read by the reading control unit and converts the number of pixels; an external output unit that outputs the moving image data output from the conversion unit to the outside; and the conversion unit An external synchronization signal that controls the output timing of the external output means is generated and output to the conversion means, and a read synchronization signal that controls the read timing of the read control means that is synchronized with the external synchronization signal is generated. and a synchronous control means for outputting said read control means Te, the read control means, wherein in response to the read synchronization signal For the moving image data read out from the memory to said compression means and said converting means and outputting together.

According to the present invention, moving image data read from a memory can be shared for output pixel number conversion and compression, and a memory bandwidth can be saved.

It is a schematic block diagram of one Example of this invention. It is a schematic block diagram of a read control unit and a resolution conversion unit. It is a schematic block diagram of a synchronous control part. 4 is a timing chart of a reference synchronization signal, a read synchronization signal, a STOP signal, and an external synchronization signal.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a schematic block diagram of an image recording apparatus incorporating an embodiment of an image processing apparatus according to the present invention. In FIG. 1, 101 is an imaging unit, 102 is a development processing unit, 103 is an image signal processing unit, 104 is a memory, and 105 is a read control unit. Reference numeral 106 denotes a resolution conversion unit, 107 a synchronization control unit, 108 a CPU, 109 a user operation unit, 110 an external output unit, 111 a compression unit, and 112 a recording unit.

  The imaging unit 101 captures an image of a subject and outputs moving image data. In this embodiment, the imaging unit 101 outputs moving image data of 60 frames / second, with one frame having 1920 horizontal pixels × 1080 vertical pixels. The development processing unit 102 converts the moving image data captured by the imaging unit 101 into moving image data in a predetermined standard format. The image signal processing unit 103 subjects the moving image data from the development processing unit 102 to image processing such as color balance adjustment and gamma correction well-known in the imaging apparatus, and outputs the processed data to the memory 104. The memory 104 can store image data for at least one frame from the image signal processing unit 103.

  The pixel number conversion unit 106 notifies the synchronization control unit 107 as a STOP signal whether input of image data can be received. The synchronization control unit 107 generates a read synchronization signal that defines the timing of reading image data from the memory 104 by the read control unit 105 in accordance with the notification of the STOP signal, and supplies the read synchronization signal to the read control unit 105. The read control unit 105 reads image data from the memory 104 based on the read synchronization signal supplied from the synchronization control unit 107.

  The pixel number conversion unit 106 takes in the image data from the read control unit 105 and converts the number of pixels in each frame into a specified number of pixels. The synchronization control unit 107 generates and supplies an external synchronization signal that defines the output timing of the image data after pixel number conversion from the pixel number conversion unit 106 to the external output unit 110 to the pixel number conversion unit 106. The pixel number conversion unit 106 outputs the image data after the pixel number conversion to the external output unit 110 in accordance with the external synchronization signal from the synchronization control unit 107. The external output unit 110 forms the output image data from the pixel number conversion unit 106 into a format that can be externally output, and outputs it.

  The user can instruct the CPU 108 of the resolution (number of pixels) of the external output through the user operation unit 109. The CPU 108 sets the synchronization control unit 107 and the pixel number conversion unit 106 based on the resolution information designated by the user using the user operation unit 109.

  The compression unit 111 shares and receives the image data supplied from the read control unit 105 to the pixel number conversion unit 106, compresses the data, and stores it in the recording unit 112. The image data input timing of the compression unit 111 may be performed in synchronization with the frame period, and timing in units of pixels is not required. Thereby, the input image data can be shared with the pixel number conversion unit 106.

  The external output unit 110 can capture resolution (number of pixels) information of a display device connected to the external output unit 110 and notify the CPU 108 of the information.

  FIG. 2 is a block diagram showing a schematic configuration of the read control unit 105 and the pixel number conversion unit 106.

  The read control unit 105 includes a line memory 201, a line memory 202, and a bank control unit 203. The bank control unit 203 controls writing / reading of the line memories 201 and 202 in accordance with the read synchronization signal supplied from the synchronization control unit 107. The pixel number conversion unit 106 includes a resizing unit 204, a timing control unit 205, a line memory 206, a line memory 207, and a bank control unit 208. The bank control unit 208 controls writing / reading of the line memories 206 and 207 according to the external synchronization signal supplied from the synchronization control unit 107. The timing control unit 205 controls the resizing unit 204 based on the information acquired from the bank control unit 203 and the bank control unit 208 and simultaneously notifies the synchronization control unit 107 of a STOP signal. The resizing unit 204 performs resolution conversion under the control of the timing control unit 205. Each of the line memories 201, 202, 206, and 207 has a capacity capable of storing a luminance signal for one line (1920 pixels) and two types of color difference signals.

  A flow of control by the readout control unit 105, the pixel number conversion unit 106, and the synchronization control unit 107 will be described.

  The synchronization control unit 107 issues a read synchronization signal to the read control unit 105. Image data is read from the memory 104 and stored in the line memory 201 and the line memory 202. The bank control unit 203 notifies the timing control unit 205 that there is image data in the line memory 201 and the line memory 202.

  The timing control unit 205 notifies the synchronization control unit 107 as a STOP signal that there is data in the line memory 201 and the line memory 202 and further reading is impossible. The synchronization control unit 107 stops issuing the read synchronization signal to the read control unit 105 according to the STOP signal.

  On the other hand, the timing control unit 205 determines that there is image data in either the line memory 201 or the line memory 202 and the line memories 206 and 207 are empty, and issues an operation instruction to the resizing unit 204. The resizing unit 204 reads image data from the line memory 201 or the line memory 202, converts the number of pixels, and outputs the image data to the line memory 206 or the line memory 207.

  The bank control unit 203 notifies the timing control unit 205 that the line memory 201 or the line memory 202 has become empty as a result of the image data being read by the resizing unit 204. The timing control unit 205 notifies the synchronization control unit 107 of the cancellation of the STOP signal. The synchronization control unit 107 resumes issuing the read synchronization signal to the read control unit 105.

  On the other hand, the bank control unit 208 notifies the timing control unit 205 when the line memory 206 and the line memory 207 are full of data. When the line memory 206 and the line memory 207 are full of data, the timing control unit 205 stops the operation instruction to the resizing unit 204.

  The above processing is repeated until the line memory 201, line memory 202, line memory 206, and line memory 207 are full.

  The timing control unit 205 issues a STOP signal to the synchronization control unit 107, whereby the state in which reading from the memory 104 is stopped is held. The synchronization control unit 107 issues an external synchronization signal to the bank control unit 208. The bank control unit 208 reads out image data from the line memory 206 or the line memory 207 in accordance with the external synchronization signal, and outputs the image data to the external output unit 110. When either the line memory 206 or the line memory 207 becomes empty, the timing control unit 205 issues an operation instruction to the resizing unit 204.

  The resizing unit 204 reads the image data from the line memory 201 or the line memory 202, performs pixel number conversion, and outputs the converted image data to the line memory 206 or the line memory 207. The bank control unit 203 notifies the timing control unit 205 when the line memory 201 or the line memory 202 becomes empty because the resizing unit 204 has read out the image data. The timing control unit 205 notifies the synchronization control unit 107 of the cancellation of the STOP signal. The synchronization control unit 107 resumes issuing the read synchronization signal to the read control unit 105.

  The synchronization control unit 107 controls each unit so as to repeat the above processing.

As an individual operation, the read control unit 105 reads data from the memory 104 until the line memory 201 and the line memory 202 are full. The resizing unit 204 performs resolution conversion when there is image data in either the line memory 201 or the line memory 202 and both the line memory 206 and the line memory 207 are not full. The bank control unit 208 reads out image data from the line memory 206 or the line memory 207 according to the external synchronization signal, and outputs the image data to the external output unit 110.
FIG. 3 shows two configuration examples of the synchronization control unit 107. In the configuration example illustrated in FIG. 3A, the synchronization control unit 107 includes a reference synchronization signal generation unit 301, an external synchronization signal generation unit 302, and a read synchronization signal generation unit 303. The reference synchronization signal generation unit 301 issues a reference synchronization signal to the external synchronization signal generation unit 302 and the read synchronization signal generation unit 303 periodically at a frame period. The external synchronization signal generator 302 and the read synchronization signal generator 303 are reset by the reference synchronization signal. As a result, the external synchronization signal generated by the external synchronization signal generator 302 and the read synchronization signal generated by the read synchronization signal generator 303 are time-synchronized in units of frames, and the frame period is kept the same. The external synchronization signal generator 302 generates an external synchronization signal for outputting image data externally. The read synchronization signal generator 303 generates a read synchronization signal in accordance with the STOP signal.

  In the configuration example illustrated in FIG. 3B, the synchronization control unit 107 includes an external synchronization signal generation unit 304 and a read synchronization signal generation unit 305. The difference from the configuration shown in FIG. 3A is that the external synchronization signal generation unit 304 also functions as the reference synchronization signal generation unit 301. The external synchronization signal generation unit 304 and the read synchronization signal generation unit 305 have the same frame period.

  FIG. 4 is a timing chart showing the relationship between the reference synchronization signal, the read synchronization signal, the STOP signal, and the external synchronization signal. FIG. 4A shows a timing chart in the case of performing the same number of pixel number conversion (maintaining the number of pixels). FIG. 4B is a timing chart in the case where the number of pixels is reduced by half.

  An example shown in FIG. 4A will be described. When the readout synchronization signal is not controlled by the STOP signal, the readout synchronization signal is reset by the reference synchronization signal, read out at regular intervals, and pauses until the next reference synchronization signal. As can be seen from the above description, the STOP signal is a signal dependent on the external synchronization signal, and the read synchronization signal is adjusted by the STOP signal at equal intervals with the external synchronization signal.

  An example shown in FIG. 4B will be described. Since it is necessary to convert the number of pixels by a half, the readout synchronization signal needs to be at a half interval with respect to the external synchronization signal. When the read control signal is not controlled by the STOP signal, the read control signal is reset by the reference synchronization signal, read at a constant interval, and pauses until the next reference synchronization signal. As can be seen from the above description, the STOP signal is a signal that depends on the external synchronization signal, and the read synchronization signal is adjusted to one-half the interval of the external synchronization signal by the STOP signal.

  In this embodiment, when creating image data for recording and display having different numbers of pixels from input image data, memory access for conversion of the number of pixels for display and memory access for conversion of the number of pixels for recording are performed. Can share. This saves DRAM bandwidth.

Claims (6)

Memory,
Processing means for writing video data to the memory;
Read control means for reading the moving image data from the memory;
Compression means for compressing the moving image data read by the read control means;
Conversion means for capturing moving image data read by the read control means and converting the number of pixels;
External output means for outputting the video data output from the conversion means to the outside;
A read synchronization signal for controlling the read timing of the read control means, which generates an external synchronization signal for controlling the output timing of the conversion means to the external output means, outputs it to the conversion means, and is synchronized with the external synchronization signal Synchronization control means for generating and outputting to the read control means ,
The read control unit, an image processing apparatus and outputs together for the moving image data read out from said memory in response to the read synchronization signal and said compression means and said converting means. The synchronization control means, from said conversion means in accordance with the signal indicating that it is possible to input the video data, according to claim 1, characterized in that outputting the read synchronizing signal to the read control unit image Processing equipment. The synchronization control means outputs the read synchronization signal to the read control means so that the conversion means does not read the moving picture data from the memory when the moving picture data cannot be input. The image processing apparatus according to claim 2, wherein the image processing apparatus is stopped. The synchronization control means;
A reference synchronization signal generating means for generating a reference synchronization signal;
External synchronization signal generating means for generating the external synchronization signal according to the reference synchronization signal;
In accordance with the reference synchronization signal and a signal indicating that the input of moving image data from the conversion means can be accepted, the read synchronization signal and the external synchronization are provided with a read synchronization signal generating means for generating the read synchronization signal The image processing apparatus according to claim 2 , wherein the read synchronization signal and the external synchronization signal are generated so that the timing of the signal is synchronized in frame units. The synchronization control means;
An external synchronization signal generating means for generating an external synchronization signal;
In accordance with the external synchronization signal and a signal indicating that it is possible to accept input of moving image data from the conversion means, the read synchronization signal generating means for generating the read synchronization signal ,
The image processing according to claim 2 , wherein the read synchronization signal and the external synchronization signal are generated such that timing synchronization between the read synchronization signal and the external synchronization signal is performed in frame units. apparatus. Comprising imaging means,
The processing means processes the moving image data output from the imaging means and writes it to the memory
The image processing apparatus according to claim 1.

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