JP7129219B2 - Imaging device - Google Patents

Description

Embodiments of the present invention relate to imaging devices.

The HDMI (registered trademark) (high-definition multimedia interface) standard, which is a video output standard, requires support for video formats other than high-definition, such as 480p, in order to comply with the standard. In other words, even a camera that captures 1080p video must be equipped with a circuit for converting to 480p in order to comply with the HDMI standard.
As a method for converting the video format of 1080p to 480p, for example, there is a method of extracting the resolution of 720×480 from 1080p to 480p as it is. However, the angle of view is smaller than that of 1080p, and accordingly more line memories are required.
On the other hand, there is also a method of extracting and resizing the angle of view with the maximum number of vertical pixels from 1080p, that is, resolution such as 1620×1080. However, since a dedicated resizing circuit is required and a memory for the resizing circuit is also required, there is a problem that the circuit scale becomes large.

JP-A-10-322571

An object of the present embodiment is to achieve standard compliance at low cost and on a small scale.

An imaging device according to this embodiment includes an image sensor and a processing unit. The image sensor includes pixels arranged in rows and columns. The processing unit reads a video signal group corresponding to a pixel group conforming to a first video standard from the image sensor, and part of the video signal group corresponding to the pixels of the cutout region included in the pixel group, The data is written into the memory while being thinned so as to conform to the second video standard different from the first video standard.

FIG. 1 is a block diagram showing an imaging device. FIG. 2 is a diagram showing the concept of conversion processing. FIG. 3 is a block diagram showing an example of a hardware configuration that implements conversion processing. FIG. 4 is a conceptual diagram showing read synchronization processing. FIG. 5 is a sequence showing an example of controlling thinning write using a write address signal. FIG. 6 is a sequence showing an example of controlling thinned writing using a write enable signal. FIG. 7 is a diagram showing the concept of converting from 2160p (4K) to 480p. FIG. 8 is a diagram showing the concept of converting from 4320p (8K) to 480p.

An imaging apparatus according to this embodiment will be described below with reference to the drawings. In the following embodiments, it is assumed that parts denoted by the same reference numerals perform the same operations, and overlapping descriptions will be omitted as appropriate.

The imaging device according to the present embodiment is assumed to be installed in, for example, an industrial inspection camera, measurement camera, surveillance camera, or microscope camera. good. Further, although it is assumed that the image capturing apparatus according to the present embodiment captures moving images, it may also capture still images.

An imaging apparatus according to this embodiment will be described with reference to the block diagram of FIG.
The imaging device 1 according to this embodiment includes an image sensor 11 , a processor 13 and a memory 15 .

The image sensor 11 is, for example, an imaging device such as a CCD (Charge-Coupled Device) sensor, a CMOS (Complementary Metal-Oxide Semiconductor) sensor, or the like. The image sensor 11 includes a plurality of pixels arranged in a matrix and generating electrical signals upon receiving input light. The image sensor 11 generates a video signal for each pixel by amplifying an electrical signal corresponding to the pixel. The video signal here is assumed to be a signal including a luminance (Y) signal and color difference (Pb, Pr) signals, but may be an RGB signal.

The processor 13 receives the video signal from the image sensor 11, controls at least one of writing the video signal to the memory 15 and reading the video signal, and adapts the video signal from the first video standard to the second video standard. Execute conversion processing to convert to a video signal. Also, the converted video signal is output to an external display or the like to display the video.
Note that the processor 13 may perform general signal processing such as gain adjustment, analog-to-digital conversion, color balance adjustment, gamma correction, and filter processing on the video signal.

The first video standard indicates, for example, a 1080p progressive video signal. 1080p has an effective pixel count of 1920×1080 pixels, a pixel clock frequency of 148.5 MHz, and a horizontal frequency of 67.433 kHz.
The second video standard is a standard different from the first video standard, and here indicates a 480p progressive video signal having a smaller number of pixels than the number of pixels of the first video standard. 480p has an effective pixel count of 720×480 pixels, a pixel clock frequency of 27 MHz, and a horizontal frequency of 31.369 kHz.

In this embodiment, conversion processing of a video signal when the first video standard is 1080p and the second video standard is 480p will be described as an example. Note that the conversion process of this embodiment is not limited to this, and can be applied to other video standards such as 720p, 576p, and 288p as long as the number of pixels of the first video standard is greater than the number of pixels of the second video standard. is.

The memory 15 is, for example, a dual-port RAM (Random Access Memory) capable of simultaneous reading and writing, and receives and stores video signals from the processor 13 .

The image sensor 11, the processor 13, and the memory 15 may be mounted in the camera as a unit, or may be separate units. When the image sensor 11, the processor 13, and the memory 15 are integrally mounted on the camera, for example, the camera alone performs from imaging to output of an image signal conforming to the second video standard.
On the other hand, when the image sensor 11, the processor 13, and the memory 15 are configured separately, for example, from a camera including the image sensor 11, the processor 13 and the memory 15 are sent via a communication interface mounted on the camera. A video signal may be transmitted by wire or wirelessly.

Next, details of the processor 13 according to the present embodiment will be described.
Processor 13 includes write control function 131 , read control function 133 , and generation function 135 .

The conversion processing in the processor 13 described above can be realized by controlling the writing of the video signal, the reading control of the video signal, or both the writing control and the reading control of the video signal to the memory 15 .

When the conversion process is performed by write control, the write control function 131 selects the clipping area set for the pixel group from the video signal group corresponding to the pixel group conforming to the first video standard (1080p). Part of the video signal group corresponding to the pixels is written into the memory 15 while being thinned out so as to conform to the second video standard (480p). Thinning to conform to the second video standard is also called thinning processing.
When the conversion process is performed under read control, the write control function 131 writes the video signal group corresponding to the pixel group conforming to the first video standard (1080p) to the memory 15 .

When the conversion process is performed by write control, the read control function 133 reads part of the video signal group that has been thinned and written to the memory 15 so as to conform to the second video standard (480p).
When the conversion process is performed by readout control, the readout control function 133 thins out a part of the video signal group corresponding to the pixels in the cutout area from the memory 15 so as to conform to the second video standard (480p). read while

The generating function 135 generates a write address signal (write address signal) indicating an address for writing the video signal to the memory 15, a write enable signal for controlling writing, and a read address signal indicating an address for reading the video signal from the memory 15. (read address signal) and a read enable signal for controlling reading.

Next, the concept of conversion processing according to this embodiment will be described with reference to FIG.
The left diagram of FIG. 2 shows pixels of 1080p. For convenience of illustration, the number of pixels in the horizontal direction (the number of pixels in the horizontal direction of the image) of 1080p is assumed to be 15 pixels, and the number of pixels in the vertical direction (the number of lines in the vertical direction of the image) of 1080p is assumed to be 9 lines. In practice, it is assumed that the number of pixels in the horizontal direction is 1920 pixels and the number of lines in the vertical direction is 1080 lines, that is, 1920×1080 pixels are processed.

The processor 13 sets a portion of the 1080p pixel area as the clipping area 201 . The size of the clipping area 201 is set to an integral multiple of the number of horizontal pixels and the number of vertical lines of the second video standard (480p). In the present embodiment, a pixel area of 1440×960 pixels, which is twice 480p vertically and horizontally, is set as the cutout area 201 . In the example of FIG. 2, the cutout area 201 is assumed to be set in the central portion of the 1080p pixel area, but may be set in any area of the 1080p pixel area.

Subsequently, the processor 13 executes thinning processing by extracting video signals corresponding to the pixels of the integral multiples of the cutout region 201 and the pixels of the integral multiples of the lines. In FIG. 2, the cutout area 201 is set to have a size of 720×480 pixels of 480p, which is twice the width and height, so pixels are extracted every two pixels and every two lines. That is, the processor 13 uses two pixels as one unit, extracts one pixel out of the two pixels, takes two lines as one unit, extracts one line out of the two lines, and extracts a line corresponding to the extracted pixel. The video signal to be used may be written in the memory 15 . Here, thinning processing is performed to extract odd-numbered pixels and odd-numbered lines (hereinafter referred to as odd-numbered pixels and odd-numbered lines). That is, of the 1920 pixels belonging to one horizontal line, odd-numbered pixels such as the 1st pixel, the 3rd pixel, . . . , the 1919th pixel are extracted, and By extracting odd-numbered lines such as the 1st line, the 3rd line, . As a result, as shown in the left diagram of FIG. 2, in odd-numbered lines, odd-numbered pixels indicated by white are extracted, and even-numbered pixels indicated by hatching are not extracted.

The right figure in FIG. 2 is a conceptual diagram after conversion from 1080p to 480p. Among the pixels included in the cutout region 201, the extracted pixels are odd-numbered pixels and odd-numbered lines. That is, since pixels are extracted every other horizontal pixel and every other vertical line out of 1440×960 pixels, 720×480 pixels, which is the number of effective pixels of 480p, can be generated as the output area 202 . Since the angle of view of the clipping area 201 is an area of 1440×960 pixels, the angle of view of the output area 202 can be made larger than simply clipping 720×480 pixels of the 480p video standard.

It should be noted that the thinning process may be executed after setting the clipping area 201 first. Also, the case where odd-numbered pixels and odd-numbered lines are read out as a thinning process for every two pixels and every two lines has been described, but even-numbered pixels and even-numbered lines may be read out, or even-odd pixels and lines may be read. can be different. Further, in one line, thinning may be performed such that odd pixels are extracted from the first two-pixel unit, and even-numbered pixels are extracted from the second two-pixel unit. Even in the case of an even number, the thinning process can be realized by the same process as in the case of the odd number.

Next, an example of a hardware configuration for realizing specific conversion processing will be described with reference to the block diagram of FIG.
FIG. 3 is an example of a hardware configuration showing input/output of main signals to/from the memory 15 regarding conversion processing.

The imaging device 1 shown in FIG. 3 includes a memory 15 , a first address generation circuit 301 , a second address generation circuit 303 and a synchronization signal generation circuit 305 . The first address generation circuit 301 implements the write control function 131 . The second address generation circuit 303 implements the read control function 133 . The first address generation circuit 301 , the second address generation circuit 303 and the synchronization signal generation circuit 305 implement the generation function 135 of the processor 13 .

A first address generation circuit 301 generates a write address signal (w_add) and a write enable signal (w_en).
A second address generation circuit 303 generates a read address signal (r_add) and a read enable signal (r_en).
The sync signal generation circuit 305 receives the 480p sync signal and generates a sync signal for horizontally and vertically synchronizing the 1080p address and the 480p address. Specifically, it generates a horizontal synchronization signal H1 and a vertical synchronization signal V1 of addresses for 1080p pixels, and a horizontal synchronization signal H2 and a vertical synchronization signal V2 of addresses for 480p pixels. Here, it is assumed that at least V1 and V2 are synchronized.

The thinning process may be performed under read control, write control, or both write control and read control.

(First embodiment)
First, an example in which the thinning process is performed by read control will be described.
When the 1080p video signal is written to the memory 15, the memory 15 receives the 1080p video signal from the image sensor 11, the first pixel clock signal (CLK1) related to 1080p, and the first address generation circuit 301. A write address signal (w_add) and a write enable signal (w_en) from are inputted.

The first address generation circuit 301 receives a first pixel clock signal and a signal of an address (H1, V1) relating to a 1080p pixel as a synchronization signal from a synchronization signal generation circuit 305 . The first address generation circuit 301 generates a write address signal and a write enable signal while counting (incrementing) the address according to the first pixel clock signal based on the synchronization signal. The write address signal is a signal indicating a unique address defined by horizontal H and vertical V values for each 1080p pixel. The write enable signal is a signal for controlling writing processing to the memory 15 of the video signal. For example, when the write enable signal is in the "High" state (ON state), write processing is performed. Further, hereinafter, "the write enable signal is in an ON state" may be read as "the write enable signal is valid".

Here, since all pixels of 1080p are written to the memory 15, video signals corresponding to each pixel of 1920×1080 specified by the write address signal are written while the write enable signal is valid.

On the other hand, when the video signal is read from the memory 15, the second pixel clock signal (CLK2) of 480p and the read address signal (r_add) and read enable signal from the second address generation circuit 303 are supplied to the memory 15. (r_en) is input.

The second address generation circuit 303 receives the second pixel clock signal and the synchronization signal from the synchronization signal generation circuit 305, the address (H2, V2) for the 480p pixels, and the pixel area (1440×960 pixels) of the cutout area 201. ) is input. The read address signal is a signal indicating a unique address defined by values in the horizontal direction H2 and the vertical direction V2 for each pixel of 480p. The read enable signal is a signal that controls reading of the video signal from the memory 15 . For example, when the read enable signal is in the "High" state (ON state), read processing is performed. In other words, reading from the memory 15 is performed when the read enable signal is valid. Here, the read enable signal becomes effective when the read address signal designates the address of the odd-numbered pixels and the odd-numbered lines included in the cutout region 201 .

That is, while the read enable signal is valid, video signals corresponding to odd-numbered pixel and odd-numbered line addresses within the cutout region 201 specified by the read address signal are read according to the clock frequency of 480p. In other words, pixels are read out from the memory 15 every two pixels and every two lines in the cutout region 201 (also referred to as thinning-out readout). A size of 720×480 pixels is read out.

Next, read synchronization processing will be described with reference to the conceptual diagram of FIG.
FIG. 4 is a timing chart regarding the horizontal synchronizing signal H1, the vertical synchronizing signal V1, and the horizontal synchronizing signal H2 and the vertical synchronizing signal V2.
Regarding the output of the read video signal to a display or the like, the output of the video signal is assumed to have the same frame rate for 1080p and 480p. Therefore, the addresses are synchronized between the write process and the read process so that the so-called "overtaking phenomenon" does not occur.
As shown in FIG. 4, in the horizontal direction, the video signal is written into the memory 15 by the horizontal synchronizing signal H1 of the 1080p standard, while the video signal is read from the memory 15 by the horizontal synchronizing signal H2 of the 480p standard. In the vertical direction, the vertical synchronization signal V1 of the 1080p standard and the vertical synchronization signal V2 of the 480p standard are synchronized so as to synchronize switching of one frame.
As a result, the read video signal is output according to the drawing timing of 480p.

(Second embodiment)
Next, a case where the thinning process is performed by write control will be described.
When writing the 1080p video signal to the memory 15, the memory 15 receives the 1080p video signal from the image sensor 11, the first pixel clock signal for 1080p, and the write signal from the first address generation circuit 301. An address signal and a write enable signal are input.

A first pixel clock signal and a synchronization signal from a synchronization signal generation circuit 305 are input to the first address generation circuit 301 . Here, the synchronization signal includes a signal specifying the address of the odd-numbered pixels and odd-numbered lines included in the cutout region 201 . Therefore, the first address generation circuit 301 generates a write address signal and a write enable signal so that only video signals corresponding to odd-numbered pixels and odd-numbered lines of 1080p are written to the memory 15, that is, thinned writing is performed. do.
As a result, a video signal of 960×540 pixels corresponding to 1080p odd pixels and odd lines is written in the memory 15 .

On the other hand, when the video signal is read from the memory 15 , the second pixel clock signal of 480p and the read address signal and read enable signal from the second address generation circuit 303 are input to the memory 15 .

Here, since the video signal has already been thinned on the write processing side, it is not necessary to perform thinning readout on the read processing side. Therefore, the second address generation circuit 303 generates a read address signal and a read enable signal for reading 720×480 pixels of 480p. Note that extracting a video signal with a pixel size of 480p from the video signal that has been thinned out is synonymous with thinning out a pixel size of 480p from the pixel region of the cutout region 201 . Therefore, both have the same angle of view.
As a result, even when thinned write is executed, similarly to when thinned read is executed, conversion from 1080p to 480p can be performed while maintaining the angle of view of the cropped region.

Next, an example of thinning write control will be described with reference to FIGS. 5 and 6. FIG.
A case in which thinning write is controlled using a write address signal will be described with reference to the sequence in FIG. In the example of FIG. 5, a time-series sequence of a 1080p clock signal (CLK1), a write enable signal (w_en), a video signal, a write address signal (w_add), and a write video signal is shown from top to bottom.

When the write enable signal is valid (here, when it becomes "H"), the processor 13 transfers the video signal acquired from the image sensor 11 to the address specified by the write address signal in accordance with the clock signal "CLK1". Write in correspondence.

Here, since it is assumed that write processing is performed for odd lines, the address "A1" of the write address signal and the video signal "S1" are written to the memory 15 as the write video signal at the first address.

Next, the addresses of the second video signal "S2" corresponding to the pixels to be thinned out and the third video signal "S3" to be written next are set to the same address "A2". That is, the addresses are incremented by one every two clocks except for the first address.

As a result, the video signal “S2” is overwritten with the next video signal “S3”, and the video signal “S3” is associated with the address “A2” as the write video signal and written in the memory 15 . Similarly, by setting the addresses of the video signals "S4" and "S5" to the same address "A3", the video signal "S4" is overwritten with the next video signal "S5", and the video signal "S4" is overwritten with the next video signal "S5". S5” is associated as a write video signal and written in the memory 15 .

In the even-numbered lines to be thinned out, since write processing is not performed for all pixels of the lines, the write enable signal is set to be invalid (the signal value is set to "L" in FIG. 5). All you have to do is
As a result, the video signals to be written become "S1", "S3", and "S5", and thinning writing is executed by performing the above-described processing on the odd lines.

Next, an example of controlling thinning write using a write enable signal will be described with reference to the sequence in FIG.
The types of each signal shown in FIG. 6 are the same as in FIG. In FIG. 6, the write enable signal is set to be valid at the timing of the odd-numbered line and the odd-numbered pixel in accordance with the clock signal "CLK1". The write address signal is set to increment the address every two clocks from the beginning.

Specifically, the write enable signal is enabled at every other timing of the clock signal "CLK1". As a result, the video signals "S1", "S3" and "S5" are determined to be the addresses "A1", "A2" and "A3", respectively.

In the thinning write described above, the image sensor 11 side does not perform any special processing, and the image signal for the entire pixel area flows from the image sensor 11 into the memory 15, and the processor 13 controls the thinning write.
Note that the process is not limited to this, and partial readout processing may be performed from the image sensor 11 when writing the video signal to the memory 15 . For example, the processor 13 may set odd-numbered pixels and odd-numbered lines for partial readout from the image sensor 11, and perform partial-readout processing on video signals corresponding to the odd-numbered pixels and odd-numbered lines. For example, partial readout processing is performed to output only electrical signals from pixels corresponding to pixel position information of odd-numbered pixels and odd-numbered lines. Note that a general method may be used for partial readout processing in the image sensor 115, and the description thereof is omitted here.

By reading the video signal corresponding to the pixels in the cutout region 201 as it is, the video signal written in the memory 15 can be thinned out, and the video signal can be converted from 1080p to 480p.

Next, a case of performing both write control and read control will be described.
For example, in write control, by executing the write control function 131 , the processor 13 performs thinning write such that only the odd lines of all the lines of 1080p are written to the memory 15 . On the other hand, in the readout control, the readout control function 133 is executed so that the processor 13 reads out only the odd-numbered pixels of the lines written in the memory 15, that is, the odd-numbered lines, thereby converting the video signal from 1080p to 480p. In this way, thinning processing may be shared.

Conversely, in write control, the processor 13 writes only odd-numbered pixels of 1080p to the memory 15 by executing the write control function 131 . In readout control, the processor 13 may share thinning processing by executing the readout control function 133 so that only the odd lines of the pixels written in the memory 15 are read out.

Then, in the case of ultra-high resolutions such as so-called 4K (2160p) and 8K (4320p), it is possible to convert from 2160p or 4320p to 480p as well.

FIG. 7 shows the concept of conversion from 4K resolution to 480p.
As shown in FIG. 7, from 3840 pixels in the horizontal direction and 2160 pixels in the vertical direction, the cutout region 201 is 2880×2880×4, which is an integral multiple of the number of horizontal pixels and the number of vertical lines of 480p. 1920 pixels are set.
The processor 13 thins out the pixels in the pixel area of the cutout area 201 every four pixels and every four lines, and writes part of the video signal group corresponding to the cutout area into the memory 15 . That is, the processor 13 uses four pixels as one unit, extracts one pixel out of the four pixels, takes four lines as one unit, extracts one line out of the four lines, and extracts a line corresponding to the extracted pixel. The video signal to be processed may be written in the memory 15 .

Next, FIG. 8 shows the concept of conversion from 8K to 480p.
As shown in FIG. 8, from 7680 pixels in the horizontal direction and 4320 pixels in the vertical direction, the cutout region 201 is 5760×, which is an integer multiple of the number of horizontal pixels and the number of vertical lines of 480p, which is 8 times the vertical and horizontal directions. 3840 pixels are set.
Therefore, the processor 13 thins out the pixels in the pixel area of the cutout area 201 every 8 pixels and 8 lines, and writes part of the video signal group corresponding to the cutout area into the memory 15 . That is, the processor 13 uses 8 pixels as one unit, extracts one pixel from among the eight pixels, takes eight lines as one unit, extracts one line from among the eight lines, and extracts one line from among the eight lines. The video signal to be processed may be written in the memory 15 .

In this embodiment, the case where the video signals of the first video standard and the second video standard are progressive signals has been described, but conversion processing can be similarly realized in the case of interlaced signals. That is, the imaging apparatus 1 according to the present embodiment can convert a 1080i video signal into a 480i video signal. In addition, the processor 13 may perform filter processing or the like on the video signal before thinning in order to spatially smooth the video. By applying filtering, it is possible to prevent the occurrence of aliasing noise and improve the image quality after conversion.

According to the present embodiment described above, a pixel region corresponding to an integral multiple of the pixel region of the second video standard is cut out from the pixel region of the first video standard as a cut-out region, and the cut-out region is the integral multiple of the pixel region. A video signal corresponding to each pixel and each line of the integral multiple is extracted.
As a result, when converting the video signal from the first video standard to the second video standard, the same circuit scale as in the case of extracting the pixel area of the second video standard as it is, and the angle of view is increased. can do. In other words, standard compliance can be achieved at low cost and on a small scale. Moreover, since conversion processing can be implemented in a small-scale logic circuit, power consumption can be reduced.

Each of the circuits described above may be an Application Specific Integrated Circuit (ASIC), a Field Programmable Logic Device (FPGA), or other complex programmable logic incorporating these dedicated hardware circuits. It may be implemented by a Complex Programmable Logic Device (CPLD) or a Simple Programmable Logic Device (SPLD).
Alternatively, the processing related to each circuit may be integrated into a CPU, and the CPU may execute each processing.

While several embodiments of the invention have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, as well as the scope of the invention described in the claims and equivalents thereof.

1 imaging device 11 image sensor 13 processor 15 memory 131 write control function 133 read control function 135 generation function 201 clipping area 202 output area 301 first address generation circuit 303 second address generation circuit 305 synchronization signal generation circuit

Claims (9)

an image sensor including a group of pixels arranged in a matrix;
A video signal group corresponding to a pixel group conforming to a first video standard is read out from the image sensor, and a part of the video signal group corresponding to the pixels of the cutout region included in the pixel group is read by the first video signal group. a processing unit that writes to a memory while thinning so as to comply with a second video standard that is different from the video standard;
imaging device. an image sensor including a group of pixels arranged in a matrix;
A video signal group corresponding to a pixel group conforming to the first video standard is read from the image sensor, the video signal group is written to a memory, and the pixel group is read from the memory. a processing unit that reads a part of the video signal group while thinning out so as to comply with a second video standard different from the first video standard;
imaging device. 3. The processing unit according to claim 1, wherein the number of horizontal pixels and the number of vertical lines in the clipping area are integral multiples of the number of horizontal pixels and the number of vertical lines of the second video standard. The imaging device described. 3. The imaging apparatus according to claim 1 , wherein said processing unit extracts a video signal corresponding to each integral multiple of the number of pixels in the horizontal direction and the number of lines in the vertical direction of said second video standard. The first video standard is 1920 pixels x 1080 pixels,
The second video standard is 720 pixels x 480 pixels,
2. The imaging device according to claim 1, wherein the area to be written in said memory is 960 pixels by 540 pixels. The first video standard is 1920 pixels x 1080 pixels,
The second video standard is 720 pixels x 480 pixels,
The clipping area corresponds to 1440 pixels x 960 pixels,
The imaging apparatus according to any one of claims 1 to 4 , wherein the processing section thins out part of the video signal group every two pixels and every two lines. The first video standard is 3840 pixels x 2160 pixels,
The second video standard is 720 pixels x 480 pixels,
The clipping area corresponds to 2880 pixels x 1920 pixels,
The imaging apparatus according to any one of claims 1 to 4 , wherein the processing section thins out a part of the video signal group every four pixels and every four lines. The first video standard is 7680 pixels x 4320 pixels,
The second video standard is 720 pixels x 480 pixels,
The clipping area corresponds to 5760 pixels x 3840 pixels,
The imaging apparatus according to any one of claims 1 to 4 , wherein the processing section thins out a part of the video signal group every eight pixels and every eight lines. The imaging apparatus according to any one of claims 1 to 8, wherein the video signal group is a progressive signal.

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