JP2006005596A - Semiconductor integrated circuit device and imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology to secure frame rates at still picture photography of high resolution and monitoring while reducing line memory capacity and suppressing a circuit scale, in a semiconductor integrated circuit device and an imaging device capable of photographing both a still picture and a moving picture. <P>SOLUTION: An LSI 100A controls switching between operations in still picture photography mode and monitoring mode by an operation mode switching register 9. In still picture photography, the output signal of an imaging element 1 is temporarily stored in an SDRAM 11 and then the frames are divided horizontally into N and read out to line memories 12 and 13, and a camera signal processing circuit 5 and an electronic zooming processing circuit 6 perform signal processing and output the signal. In the monitoring mode, on the other hand, a sub-sampling circuit 4 is used to resize the output signal of the imaging element 1 to 1/N according to the number of horizontal pixels needed for monitoring and the signal is subjected to video signal processing and outputted in real time. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device and an imaging device for capturing both still images and moving images, and particularly to a technique for performing imaging using a multi-pixel imaging device and a memory for storing video signals.

As an imaging apparatus capable of capturing both a still image and a moving image, there is a technique described in Patent Document 1, for example. The technique described in Patent Document 1 includes a light receiving unit, a vertical transfer unit, and a horizontal transfer unit in an imaging device, and the vertical transfer unit mixes and outputs charge signals obtained by upper and lower light receiving units adjacent to each other in the vertical direction. The horizontal transfer unit mixes and outputs the charge information of at least two upper and lower pixels adjacent to each other in the vertical direction transferred from the vertical transfer unit, and reduces the drive frequency of the image sensor. A moving image and a high-quality still image can be obtained.
JP 2000-295531 A

  When realizing high resolution in an imaging device that can shoot both still images and moving images, signal processing is required for high-resolution video signals when shooting still images. During monitoring, it is required to ensure the frame rate, that is, the signal output rate from the image sensor. However, in the conventional imaging device circuit configuration as shown in FIG. 7 which the inventor of the present invention has studied as a prerequisite technology of the invention, the capacity of the line memory required for video signal processing increases with the increase in resolution. It will be. An increase in the line memory capacity leads to an increase in the scale of a semiconductor integrated circuit device including the line memory, and an increase in chip area and power consumption becomes a problem.

  The present invention has been made in view of the above-described problems, and a purpose thereof is a semiconductor integrated circuit device for enabling both still images and moving images to be taken, and an imaging device including the semiconductor integrated circuit device. Provides a technology that can achieve both signal processing for high-resolution video signals during still image shooting and securing the frame rate during monitoring, while reducing the circuit memory capacity and reducing the circuit scale than before. That is.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In order to achieve the above object, a semiconductor integrated circuit device of the present invention includes a memory circuit (frame memory) that stores a signal (video signal) output from an image sensor, and a signal read from the memory circuit or the image sensor. An image signal processing circuit for generating a video signal based on an output of the line memory, the line memory having at least one line for delaying a signal output from the image sensor, A sub-sampling circuit for resizing the output signal so that the number of pixels in the horizontal direction of one frame is H (1 / N) × H (N is an integer of 1 or more); Means for switching operation during monitoring (operation mode switching register), and the capacity per line of the line memory is (1 / N) × H. The capacity is enough to hold the corresponding video information and process the video signal.

  According to another aspect of the present invention, there is provided an image pickup apparatus including the semiconductor integrated circuit device having the above-described configuration, and having an image pickup element and an image pickup element driving circuit for driving the image pickup element. The image pickup apparatus according to the present invention includes an A / D circuit for A / D converting the output signal of the image pickup element and inputting the signal to the sub-sampling circuit, a display device for monitoring output, and an external storage for storing the output signal. The structure which further has an apparatus etc. may be sufficient.

  The frame memory is composed of, for example, SDRAM (Synchronous DRAM). The frame memory portion may be configured separately from the semiconductor integrated circuit device. The video signal processing circuit includes, for example, a camera signal processing circuit and an electronic zoom processing circuit. The capacity that can hold video information corresponding to (1 / N) × H is, in other words, 1 / N compared to the capacity that holds all video information corresponding to H in one line, or The capacity is 1 / L (1 <L <N).

  The angle-of-view adjustment by monitoring is normally performed using a display device such as an LCD (Liquid Crystal Display) monitor having a smaller number of pixels than the output of the image sensor, and in this case, output of a high-resolution video signal is not required. The present invention is premised on a system in which the number of horizontal pixels in the monitoring output of the display device is 1 / N with respect to the number of horizontal pixels H of a still image photographed, that is, created through the imaging device.

  In the present invention, at the time of monitoring, a sampling process is performed by the sub-sampling circuit before a video signal process is performed on a high-resolution video signal output from the image sensor, whereby a horizontal direction of one frame of the video signal is obtained. Resizing is performed so that the number of pixels becomes 1 / N in accordance with the number of horizontal pixels in the monitoring output. Thus, using a line memory having a capacity corresponding to (1 / N) × H per line, the video signal is processed in real time without temporarily storing the video signal in the frame memory. be able to. By such technical means, signal processing for the output signal of the image sensor can be executed in real time with a small number of additions to the conventional image pickup apparatus circuit configuration using SDRAM.

  On the other hand, since it is not required to secure the frame rate during still image shooting, the video signal is temporarily stored in the frame memory before the video signal processing, and the frame of the stored video signal is divided into N areas in the horizontal direction. , The video signal processing is performed by the video signal processing circuit in N times. The video signal stored in the frame memory is divided into N in the horizontal direction from the line memory by a memory circuit control unit (memory control) that controls the frame memory so as to read data from the frame memory for each frame division area. The video signal processing is performed on the read video signal and the video signal thus read is written again to the frame memory. The video signal processing circuit sequentially processes the video signal divided into N areas and recombines it with the original data when writing to the frame memory. Since the data for one line of the signal is the amount of (1 / N) × H, the video signal of one frame is stored in a line memory having a capacity corresponding to (1 / N) × H per line. Can be processed.

  In addition, when the image signal processing circuit is divided into the N areas during still image shooting and the signal processing is performed by the video signal processing circuit, when the enlargement ratio in the electronic zoom processing is M, the signal stored in the memory circuit is The frame is cut out to be (1 / M) × H in the horizontal direction, and the cut out area is overlapped (partially overlapped) in the horizontal direction of the frame corresponding to the N to maintain the signal continuity. In such a manner, signal processing is performed by dividing and reading out. As the video signal processing, the electronic zoom processing is continuous processing in the horizontal direction of the frame, and a coefficient that continuously changes in the horizontal direction is used in calculating the electronic zoom output signal. For this reason, a register for holding the coefficient is provided in the electronic zoom processing circuit so that a part of the read area in the N divisions from the frame memory is partially overlapped and used for calculation of the electronic zoom output signal at the division boundary. The stored coefficient is held in the coefficient holding register and is reflected at the time of electronic zoom processing for the next readout area. Thereby, the continuity at the boundary of the division is reproduced.

  The semiconductor integrated circuit device and the imaging device of the present invention can perform video signal processing on video signals corresponding to the number of pixels in the horizontal direction necessary for monitoring by switching between still image shooting operation and monitoring operation. With a line memory of a minute capacity, both high-resolution still image shooting and securing of the frame rate during monitoring are realized.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, in a semiconductor integrated circuit device capable of taking both still images and moving images and an imaging device including the same, a line memory with a capacity reduced compared to the conventional one can suppress the circuit scale. On the other hand, it is possible to realize both signal processing for a high-resolution video signal during still image shooting and securing of a frame rate during monitoring.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  1 to 5 are diagrams for explaining the imaging device according to the first embodiment of the present invention and the semiconductor integrated circuit device (LSI) according to the first embodiment of the present invention. FIG. 6 is a diagram for explaining the imaging device according to the second embodiment of the present invention and the semiconductor integrated circuit device according to the second embodiment of the present invention. FIG. 7 is a block diagram showing a configuration of an image pickup apparatus examined by the present inventor as a prerequisite technology of the present invention for comparison with the embodiment of the present invention, and the basics when an SDRAM is used as a component. 1 shows a typical imaging device circuit configuration.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of an imaging apparatus according to Embodiment 1 of the present invention. The imaging apparatus includes the semiconductor integrated circuit device 100A according to the first embodiment of the present invention.

  The imaging apparatus according to the first embodiment includes an LSI 100A, an imaging element 1, an imaging element driving circuit 2, an A / D circuit 3, and other LCD monitors (not shown) that incorporate processing functions capable of capturing both still images and moving images. Monitoring display device (hereinafter referred to as a display device), an external storage device for storing photographing data, and the like. Regarding the display device and the external storage device, a configuration integrated with the imaging device or a configuration connected as a separate device may be used. The LSI 100A includes a sub-sampling circuit 4, a camera signal processing circuit 5, an electronic zoom processing circuit 6, an image compression circuit 7, an output IF (interface) 8, an operation mode switching register 9, a memory control 10, an SDRAM 11, and a first line memory 12. , A second line memory 13, and SW (switches) 14 and 15.

  The imaging apparatus switches the operation of the imaging element driving circuit 2, the sub-sampling circuit 4, the first switch 14, and the second switch 15 by the operation mode switching register 9, so that the monitoring mode and the still image shooting are performed as the operation mode. Switch between modes. In the monitoring mode, a monitoring process, that is, a process of outputting an image while securing a predetermined frame rate from the image sensor 1 to the display device is performed. In the still image shooting mode, processing for processing a high-resolution video signal for still image shooting is performed. The first line memory 12 and the second line memory 13 for video signal processing have a capacity for performing signal processing on the number of horizontal pixels necessary for monitoring when processing a frame of the video signal.

  The image pickup device 1 is a multi-pixel image pickup device that performs photoelectric conversion of input light using a horizontal / vertical photoelectric conversion device and outputs a video signal. The image sensor drive circuit 2 is a drive circuit that drives the image sensor 1. The A / D circuit 3 performs analog / digital conversion (sampling) on an analog video signal output from the image sensor 1 and inputs output data to the sub-sampling circuit 4 of the LSI 100A.

  The sub-sampling circuit 4 samples the video signal data input from the image sensor 1 through the A / D circuit 3 and resizes it to 1 / N (N is an integer equal to or greater than 1) based on control according to the operation mode. I do. During the resizing process, the sub-sampling circuit 4 stops the operation of the clock supplied to the video signal processing circuit in units of N pixels, and puts the data to be put on this clock on the addition average value for each N pixels of the output signal from the image sensor 1. Perform the replacement process. These values N are values that correspond to each other throughout this specification. Details of this sampling process will be described later.

  As a video signal processing circuit, a camera signal processing circuit 5 and an electronic zoom processing circuit 6 are provided. The camera signal processing circuit 5 performs camera signal processing on the video signal data. The electronic zoom processing circuit 6 performs electronic zoom processing on the video signal data. Each of the processing circuits 5 and 6 performs signal processing on the data stored in the corresponding line memories 12 and 13.

  The first line memory 12 is a memory used for camera signal processing in the camera signal processing circuit 5. The second line memory 13 is a memory used for electronic zoom processing in the electronic zoom processing circuit 6. Each of the line memories 12 and 13 stores frame data read out from the SDRAM 11 through the memory control 10 for corresponding processing.

  The image compression circuit 7 performs processing for compressing and outputting the video data from the SDRAM 11 by a predetermined image compression method. The output IF 8 is an interface that outputs video (including still images and moving images) data to the outside of the LSI 100A. For example, the display device is connected to the output IF 8.

  The memory control 10 is a memory circuit control unit that controls access such as read / write of video data to the SDRAM 11. In particular, the memory control 10 controls the SDRAM 11 so that data is read from the SDRAM 11 for each division range in a frame division process to be described later. The SDRAM 11 is a frame memory for storing video data from the image sensor 1, and has a capacity capable of storing image data for two full-size frames with reference to a frame output from the image sensor 1. Video data input from the sub-sampling circuit 4 through the switch 14 is written in the SDRAM 11 in units of frames, or data after signal processing in the video signal processing circuit is input through the switch 15 and written therein. In addition, the frame data is divided and read from the SDRAM 11 to the video signal processing circuit and its line memories 12 and 13, or is read to the output IF 8 through the image compression circuit 7.

  Next, regarding the operations of the imaging apparatus and the LSI 100A, the monitoring operation, that is, the monitoring mode used when the angle of view for still image shooting is first described. At the time of monitoring, the imaging apparatus, particularly the LSI 100A, uses the operation mode switching register 9 to set the switch 14 to directly input the video signal data after the subsampling process in the subsampling circuit 4 to the camera signal processing circuit 5, In addition, the switch 15 is set to output the output signal of the electronic zoom signal processing circuit 6 to the output IF 8 as it is.

  In this imaging apparatus and LSI 100A, the number of pixels in the horizontal direction of the frame of the video signal necessary for monitoring is (1 / N) × H with respect to the number of pixels H in the horizontal direction of the frame of the still image taken during still image shooting. It is a premise to do. Under this premise, at the time of monitoring, the video signal output from the image sensor 1 is resized by the sub-sampling circuit 4 to (1 / N) × H in the horizontal direction of the frame. As a result, the number of pixels in the horizontal direction of the processing target frame becomes 1 / N. Therefore, the capacities of the line memory 12 necessary for the camera signal processing and the line memory 13 necessary for the electronic zoom processing are the image pickup device circuit configuration shown in FIG. Therefore, the capacity of 1 / N is sufficient as compared with the capacity of each line memory 12C, 13C required. The output signal after the signal processing by the camera signal processing circuit 5 or the like is output from the output IF 8 to the display device. With the above operation, signal processing for monitoring can be executed in real time while securing a predetermined frame rate. The imaging element driving circuit 2 controls the sampling in the frame vertical direction.

  The capacity of the line memories 12 and 13 may be a capacity corresponding to (1 / N) × H with respect to the number of pixels H in the horizontal direction of the frame per line, or more (1 / The capacitance may be L) × H (1 <L <N).

  FIG. 7 is an example of a basic imaging device circuit configuration for processing both high-resolution still image shooting and monitoring. In this case, the line memories 12C and 13C are images output from the imaging device 1C. Corresponding to the number of horizontal pixels H of the signal frame, each line has a capacity for holding all video information (pixel information) corresponding to the H. The output signal after the video signal processing by the camera signal processing circuit 5C or the like is stored in the SDRAM 11C during still image shooting, and is output as it is from the output IF 8C during monitoring.

  Next, referring to the explanatory diagram of the sub-sampling process in the imaging apparatus and the LSI 100A of the first embodiment shown in FIG. 2, the sampling rate of the sub-sampling circuit 4 is 1/2 (that is, the N Is described using an example in the case of 2). (1) in FIG. 2 shows the output of the image sensor 1. (2) shows the output after separation of the two components with respect to the output of the image sensor 1. (3) further shows the output after interpolation. (4) shows the output after calculating the average value. (5) shows the sampling output of the sub-sampling circuit 4.

  As shown in (1), the complementary color CCD (charge coupled device) and primary color CCD output assumed as the image pickup device 1 are output in two lines alternately (each series of A and B in the figure). The two components are separated as shown in (2), and sampling is performed later for each separated component. When sampling for resizing to 1 / N in the sub-sampling circuit 4, simply outputting one pixel for every N pixels results in loss of continuity of the signal, causing moiré. The average value of surrounding pixels is output as sampling data. Here, as shown in (3), as an interpolation complement process, the average value of the data of the same component adjacent in the part where each component is missing is interpolated with respect to the separated two components. For example, the average value “A2 ′” is complemented between the pixel values A1 and A3. And using this, as shown in (4), the average value of surrounding pixels is calculated according to the sampling rate in resizing. For example, an average value “A1” ”of four pixel values {A1, A2 ′, A3, A4 ′} is calculated in response to the sampling rate being ½. This further increases the effect of preventing the occurrence of moire. Then, as shown in (5), a sampling output is obtained by alternately outputting the average value of the calculated two components in one line. Here, since the sampling rate is ½, the data is resized to ½ of the output of the original image sensor 1.

  Next, as an operation of the imaging apparatus and the LSI 100A, an operation at the time of still image shooting, that is, a still image shooting mode will be described. At the time of still image shooting processing, since the high-resolution video signal is used, the sub-sampling circuit 4 does not perform sub-sampling because the output signal of the image sensor 1 does not need to be resized. Accordingly, the imaging apparatus, particularly the LSI 100A, sets the video signal input to the sub-sampling circuit 4 to be output as it is without performing the sampling process through the operation mode switching register 9. Further, through the operation mode switching register 9, the switch 14 is set to send the output signal of the sub-sampling circuit 4 to the SDRAM 11 side, and the switch 15 sends the output signal after the signal processing in the video signal processing circuit to the SDRAM 11 side. Set. Through an operation based on the above setting, an output signal for each frame from the image sensor 1 is temporarily stored in the SDRAM 11 through the memory control 10.

  In the next processing stage, the imaging device, particularly the LSI 100A, reads out the frames stored in the SDRAM 11 by dividing into a predetermined number in the horizontal direction, performs video signal processing, and stores the frames in the SDRAM 11 again. Let N be the number of divisions. As a result, the number of pixels in the horizontal direction of the video data to be processed by the camera signal processing circuit 5 or the like becomes 1 / N with respect to the frame output from the original image sensor 1, so that the line memories 12 and 13 are shown in FIG. Compared with the circuit configuration of, signal processing can be executed with a memory capacity in which the word length in one line is reduced to 1 / N. Each of the N divided frame regions is sequentially processed by the camera signal processing circuit 5 and the electronic zoom processing circuit 6, and the processed data is re-determined from the undivided frame when written to the SDRAM 11. Synthesize. By the above division processing, signal processing can be performed on all pixels in one frame, and high-resolution still image shooting processing can be achieved.

  Next, referring to FIG. 3 and FIG. 4, a method for reading and writing frame data to and from the SDRAM 11 when performing the division processing will be described in more detail. FIG. 3 is an explanatory diagram showing a method of reading data from the SDRAM 11 when the frame is divided. Reference numeral 16 denotes an image sensor output data area, 17 denotes a cut-out range for electronic zoom processing, 18 to 20 denote reading ranges at the time of division, and 21 denotes a reading order at the time of division.

  A solid line area of 16 represents output data of one frame full size (all pixels) stored in the SDRAM 11 and the number of pixels in the horizontal direction is represented by H. A solid line area 17 represents a cut-out range for electronic zoom processing in the output data area 16 for one frame. In this cut-out range, the number of pixels in the horizontal direction is (1 / M) × H, where M is the enlargement ratio in the electronic zoom processing in the electronic zoom processing circuit 6. Of the area 17 divided by the broken line, 18 areas indicate the first reading range when the cutout range is divided into N sheets in the horizontal direction by the dividing process. Similarly, the 19 area indicates the read range of the second sheet, and the 20 area indicates the read range of the Nth sheet. The number of pixels in the horizontal direction of each readout range 18 to 20 is (1 / M · N) × H because the region 17 to be the cutout range is divided into N in the horizontal direction. An arrow 21 indicates the order of reading data in the first reading range 18, and signal processing is performed for each reading range in this order. In other words, in each readout range, data is divided for one line divided in the horizontal direction and processed for the next divided line in the vertical direction.

  FIG. 4 is an explanatory diagram showing a method of writing the output signal to the SDRAM 11 after performing signal processing on the video data divided and read from the SDRAM 11 as shown in FIG. Reference numeral 17b denotes a write range to the SDRAM 11 corresponding to the cut-out range 17 for electronic zoom processing, 22 to 24 denote write ranges at the time of division, and 25 denotes a write order at the time of division. The solid line area 17b corresponds to the area cut out from the SDRAM 11 shown in FIG. 3, and this area is written to the storage area of the frame before signal processing in the SDRAM 11, that is, recombined. Twenty-two regions out of the region 17b divided by broken lines indicate the write range of the signal processing output to the SDRAM 11 corresponding to the divided first read range. Similarly, the area 23 indicates the writing range of the second sheet, and the area 24 indicates the writing range of the Nth sheet. The number of horizontal pixels in each writing range 22 to 24 is (1 / N) × H because one frame before reading and signal processing is divided into N in the horizontal direction. An arrow 25 indicates the order of data writing in the writing range of the first sheet, and writing to the SDRAM 11 is performed for each writing range in this order.

  In the dividing process, first, the divided first reading range 18 shown in FIG. 3 is read from the SDRAM 11 and stored in the line memories 12 and 13, while the camera signal processing circuit 5 and the electronic zoom processing circuit are processed for this data. 6, after each signal processing is performed, writing is again performed on the first writing range 22 shown in FIG. 4 in the SDRAM 11. Next, the signal processing for the second and subsequent reading ranges 19 is performed in the same manner. At this time, in order to reproduce continuity at the boundary of division in the frame, the imaging apparatus and the LSI 100A overlap the data in the horizontal direction (partially overlap) as in the areas 18 and 19 shown in FIG. The data is read from the SDRAM 11 and processed.

  As the video signal processing, the electronic zoom processing is continuous processing in the horizontal direction of the frame, and a coefficient that continuously changes in the horizontal direction is used in calculating the electronic zoom output signal. At this time, the N-divided read ranges from the SDRAM 11 are overlapped as described above, but the continuity at the boundary of the frame division cannot be reproduced simply by overlapping and performing signal processing. For this purpose, the electronic zoom processing circuit 6 is provided with a coefficient holding register (not shown) that holds a coefficient that continuously changes in the horizontal direction of the frame for calculating the electronic zoom output signal. The coefficient used to calculate the electronic zoom output signal at the boundary of the frame division is held in this coefficient holding register, and is reflected during the electronic zoom processing for the next divided readout range. As a result, the continuity at the boundary between the frame divisions is reproduced.

  As described above, in the still image shooting mode, the frames once stored in the SDRAM 11 are sequentially read, video signal processing, and writing in units of video signal data divided into N frames, that is, signals divided into N times. Through the processing, signal processing for the entire frame is completed.

  FIG. 5 shows an operation sequence in the still image shooting mode in the imaging apparatus and the LSI 100A. 5A shows a vertical synchronization signal output from the image sensor 1, FIG. 5B shows an internally generated vertical synchronization signal generated inside the LSI 100A, and FIG. 5C shows an operation sequence. The period of the vertical synchronization signal (1) is a period in which the image sensor 1 outputs a video signal of one frame. The internally generated vertical synchronization signal (2) is generated by the LSI 100A based on the vertical synchronization signal of the image sensor 1. The internally generated vertical synchronization signal has a period of 1 / N with respect to the period of the vertical synchronization signal when the number of divisions is N as in the case of the sequence of video signal processing using the frame division processing. . Each process in the operation sequence shown in (3) is operated in synchronization with the internally generated vertical synchronization signal.

  First, the video signal for one frame output from the image sensor 1 is stored in the SDRAM 11 in the first period of the vertical synchronizing signal. Next, in the second period of the vertical synchronization signal, signal processing (# 1 to #N) is performed in each period of the internally generated vertical synchronization signal obtained by dividing the vertical synchronization signal into N parts. That is, in one signal processing # 1, frame division reading from the SDRAM 11, video signal processing (that is, the camera signal processing and electronic zoom processing), and division writing to the SDRAM 11 are performed as a set. After this signal processing is performed N times to complete the video signal processing for one frame, the video signal data after the video signal processing for one frame is read from the SDRAM 11 in the third period of the vertical synchronization signal. Then, after the image compression processing by the image compression processing circuit 7, the captured still image is output to an external device via the output IF 8. Thereby, for example, the photographed still image is recorded on the storage medium through the external storage device as an external device. In this manner, a high-resolution still image can be created at a frame rate of 1 frame per 3 frames as compared with the real-time monitoring mode.

  With the above-described configuration and processing method, the imaging apparatus and the LSI 100A perform processing by switching the operation at the time of monitoring and at the time of still image shooting with the operation mode switching register 9, so that the line memory 12 used for video signal processing, As for 13, the capacity for video signal processing corresponding to the video signal of the number of pixels in the horizontal direction necessary for monitoring, that is, a small capacity of 1 / N per line compared to the conventional circuit configuration as shown in FIG. With the configuration of the line memory, both high-resolution still image shooting and real-time monitoring with a predetermined frame rate can be realized.

(Embodiment 2)
Next, another embodiment will be described. FIG. 6 is a block diagram illustrating a configuration of the imaging apparatus according to Embodiment 2 of the present invention. The imaging device includes the semiconductor integrated circuit device 100B according to the second embodiment of the present invention.

  The second embodiment is a shared line memory that is a line memory in which the line memory 12 used for the camera signal processing and the line memory 13 used for the electronic zoom processing are shared with respect to the first embodiment shown in FIG. 60 is provided. The LSI 100B according to the second embodiment includes a shared line memory 60, a camera signal processing circuit 5B, an electronic zoom processing circuit 6B, an operation mode switching register 9B, and the like, and the other portions have substantially the same configuration as that of the first embodiment. By using only the shared line memory 60 as the line memory used for the video signal processing, the line memory capacity is further reduced as compared with the first embodiment.

  In the imaging apparatus and LSI 100B according to the second embodiment, the switching control between the monitoring mode and the still image shooting mode is performed by the operation mode switching register 9B as in the first embodiment, and at the time of still image shooting, the same as in the first embodiment. The frame division process is used for the above. The capacity of the shared line memory 60 is a capacity corresponding to (1 / N) × H. As a result, high-resolution still image shooting can be realized by the shared line memory 60 having a capacity reduced from the total capacity of the two line memories 12 and 13. However, in the second embodiment, since the camera signal processing and the electronic zoom processing cannot be performed at the same timing as shown in the above (3), the electronic zoom processing circuit 6B performs electronic processing both at the time of still image shooting and monitoring. Before zoom processing, it is necessary to perform processing for temporarily storing data from the camera signal processing circuit 5B to the SDRAM 11. The memory control 10B stores data after camera signal processing in the SDRAM 11B based on a request from the camera signal processing circuit 5B, and reads the data and supplies it to the electronic zoom processing circuit 6B at the next timing. Accordingly, in the second embodiment, the frame rate is reduced by the amount that the line memory capacity can be reduced. Specifically, a still image can be created at a frame rate of one frame for four frames during still image shooting, while a frame rate of one frame for two frames can be created during monitoring. As a result, the monitoring output becomes possible, which is half of the output rate of the image sensor 1.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be used for various imaging apparatuses such as a digital video camera, a digital still camera, and a camera-equipped mobile phone.

It is a block diagram which shows the structure of the imaging device in Embodiment 1 of this invention. (1)-(5) is explanatory drawing about the subsampling process in the imaging device and semiconductor integrated circuit device in Embodiment 1 of this invention. It is explanatory drawing about the division | segmentation read-out of the video signal from SDRAM in the imaging device and semiconductor integrated circuit device in Embodiment 1 of this invention. It is explanatory drawing about the division | segmentation writing of the video signal to SDRAM in the imaging device and semiconductor integrated circuit device in Embodiment 1 of this invention. (1)-(3) is a figure which shows the operation | movement sequence at the time of the still image photography with the imaging device and semiconductor integrated circuit device in Embodiment 1 of this invention. It is a block diagram which shows the structure of the imaging device in Embodiment 2 of this invention. It is a block diagram which shows the conventional imaging device circuit structure examined as a premise technique of this invention for the comparison with embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Imaging device, 2 ... Imaging device drive circuit, 3 ... A / D circuit, 4 ... Subsampling circuit, 5 ... Camera signal processing circuit, 6 ... Electronic zoom processing circuit, 7 ... Image compression circuit, 8 ... Output IF, DESCRIPTION OF SYMBOLS 9 ... Operation mode switching register, 10 ... Memory control, 11 ... SDRAM, 12 ... Line memory, 13 ... Line memory, 14, 15 ... Switch, 16 ... Image sensor output data area, 17 ... Extraction range, 17b ... Extraction range Corresponding writing range, 18 to 20: Reading range at the time of division, 21: Reading order at the time of dividing, 22 to 24: Writing range at the time of dividing, 25: Writing order at the time of dividing, 60: Shared line memory.

Claims (10)

A memory circuit for storing an output signal from the image sensor, at least one line memory for delaying a signal read from the memory circuit or an output signal from the image sensor, and an image based on the output of the line memory A semiconductor integrated circuit device comprising a video signal processing circuit for generating a signal,
A subsampling circuit for resizing the output signal from the image sensor so that the number of pixels in the horizontal direction of one frame is H (1 / N) × H;
An external image sensor driving circuit, the video signal processing circuit, and a register for switching the operation of the sub-sampling circuit,
The capacity per line of the line memory is a capacity for holding video information corresponding to (1 / N) × H. The semiconductor integrated circuit device according to claim 1.
The operation of causing the video signal processing circuit to perform signal processing on the signal read from the memory circuit during still image shooting, and the output signal from the image sensor to 1 / N by the sub-sampling circuit during monitoring A semiconductor integrated circuit device characterized in that a process of switching the resized signal by an operation of causing the video signal processing circuit to perform signal processing is performed by the register. The semiconductor integrated circuit device according to claim 2.
The register switches the operation mode by switching the operation of the external image sensor driving circuit, the video signal processing circuit, and the sub-sampling circuit between still image shooting and monitoring.
At the time of still image shooting, the output signal from the image sensor is stored in the memory circuit without resizing processing by the sub-sampling circuit, and the signals stored in the memory circuit correspond to N / N signals corresponding to the 1 / N. An operation for dividing the region into signals and performing signal processing in the video signal processing circuit for each of the divided regions, and a signal obtained by resizing the output signal from the image sensor by the sub-sampling circuit during the monitoring Frame rate at the time of monitoring by performing the process of switching by the register between the operation of acquiring the video signal by performing the signal processing in the video signal processing circuit without storing and dividing into the memory circuit The semiconductor integrated circuit device characterized by ensuring. The semiconductor integrated circuit device according to claim 3.
A memory circuit control unit for operating a read / write address of data to the memory circuit;
The sub-sampling circuit stops the operation of the clock supplied to the video signal processing circuit in units of N pixels corresponding to the 1 / N, and the data to be put on the clock is output for each N pixels of the output signal from the imaging device. Perform the process of switching to the addition average value,
At the time of still image shooting, the output signal from the image sensor is temporarily stored in the memory circuit without resizing processing by the sub-sampling circuit, and the signal stored in the memory circuit is horizontally framed using the memory circuit control unit. A semiconductor integrated circuit characterized by causing the video signal processing circuit to sequentially perform signal processing on the N divided regions by reading the line memory in the direction of (1 / N) × H in the direction. apparatus. The semiconductor integrated circuit device according to claim 4.
As the video signal processing circuit, a camera signal processing circuit that performs camera signal processing, and an electronic zoom processing circuit that performs electronic zoom processing,
The signal stored in the memory circuit when the enlargement ratio in the electronic zoom processing is M when the video signal processing circuit is divided into the N areas during the still image shooting. Is cut out to be (1 / M) × H in the horizontal direction of the frame, and the cutout area is partially overlapped in the horizontal direction of the frame corresponding to the N so that the signal continuity is maintained. A semiconductor integrated circuit device characterized in that it is divided and read to perform signal processing. An image sensor, an image sensor drive circuit that drives the image sensor, a memory circuit that stores a signal output from the image sensor, and a signal read from the memory circuit or a signal output from the image sensor An imaging apparatus comprising: a line memory of at least one line; and a video signal processing circuit that generates a video signal based on an output of the line memory,
A subsampling circuit for resizing the output signal from the image sensor so that the number of pixels in the horizontal direction of one frame is H (1 / N) × H;
A register for switching operations of the image sensor driving circuit, the video signal processing circuit, and the sub-sampling circuit;
The capacity per line of the line memory is a capacity for holding video information corresponding to (1 / N) × H. The imaging device according to claim 6.
The operation of causing the video signal processing circuit to perform signal processing on the signal read from the memory circuit at the time of still image shooting, and the signal output from the image sensor at the time of moving image shooting at the 1 / An image pickup apparatus, wherein an operation for performing signal processing in the video signal processing circuit on a signal resized to N is switched by the register. The imaging device according to claim 7.
The register switches the operation mode by switching the operation of the image sensor driving circuit, the video signal processing circuit, and the sub-sampling circuit between still image shooting and monitoring.
At the time of still image shooting, the output signal from the image sensor is stored in the memory circuit without resizing processing by the sub-sampling circuit, and the signals stored in the memory circuit correspond to N / N signals corresponding to the 1 / N. An operation of reading the image signal processing circuit into the line memory for each of the divided regions and performing signal processing in the video signal processing circuit, and an output signal from the image sensor during the monitoring by the sub-sampling circuit By performing a process of switching by the register, an operation for causing the video signal processing circuit to perform signal processing without storing and dividing the resized signal in the memory circuit, the frame at the time of monitoring An imaging apparatus characterized by securing a rate. The imaging apparatus according to claim 8.
A memory circuit control unit for operating a read / write address of data to the memory circuit;
The sub-sampling circuit stops the operation of the clock supplied to the video signal processing circuit in units of N pixels corresponding to the 1 / N, and the data to be put on the clock is output for each N pixels of the output signal from the imaging device. Perform the process of switching to the addition average value,
At the time of still image shooting, the output signal from the image sensor is temporarily stored in the memory circuit without resizing processing by the sub-sampling circuit, and the signal stored in the memory circuit is horizontally framed using the memory circuit control unit. An image pickup apparatus characterized by causing the video signal processing circuit to sequentially perform signal processing on the N divided areas by reading out (1 / N) × H in order in a line order. The imaging apparatus according to claim 9, wherein
As the video signal processing circuit, a camera signal processing circuit that performs camera signal processing, and an electronic zoom processing circuit that performs electronic zoom processing,
The signal stored in the memory circuit when the enlargement ratio in the electronic zoom processing is M when the video signal processing circuit is divided into the N areas during the still image shooting. Is cut out to be (1 / M) × H in the horizontal direction of the frame, and the cutout area is partially overlapped in the horizontal direction of the frame corresponding to the N so that the signal continuity is maintained. An imaging apparatus characterized by dividing and reading out and performing signal processing.

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