JP2002033939A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor, by which the phase of a sampling clock used in the A/D conversion of a static image signal is adjusted automatically to a proper phase. SOLUTION: Image data which is digitized by an A/D conversion part 1 is stored once in a memory part 4. In a difference detection part 5, image data on a present field is compared with image data on an immediately preceding field which is read out from the memory part 4, and the difference between both fields is found. In a deciding part 6, when the difference is at a prescribed value or less, the image is decided as being a static image. When the static image is judged, a control part 7 selects the tap (a to n) of a phase adjustment part 3, in such a way that the difference data from the part 5 becomes a prescribed value or less. Thereby, the phase of a clock signal CKo generated by a clock generation part 2 is shifted, and a clock CKs at a proper phase is supplied to the part 1 as the sampling clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image processing apparatus, and more particularly, to automatic adjustment of the phase of a sampling clock used in A / D conversion.

[0002]

2. Description of the Related Art In an apparatus for displaying an image by digital image processing such as a PDP, an A / D converter is provided in a signal input stage to convert an analog input video signal into a digital signal. The sampling clock signal used for the A / D conversion is required to have accurate and stable frequency. However, even if the frequency is accurate and stable, if the phase is inappropriate, the image quality may be degraded. In particular, with the recent diversification of video sources, video processing apparatuses often target not only moving images but also still images, and in this case, the image quality tends to be more noticeable in still images. For example, as shown in FIG. 2A, in the case where the analog input video signal Si is sampled by the clock CK, sampling at the level change point such as point A or point B shown in FIG. The sampling data becomes different data, and the obtained pixel data becomes uncertain data. Such pixel data may cause problems such as a change in luminance (noise) and vertical lines causing jitter (lateral displacement) on the screen,
Still images are unsightly. Therefore, in the past, a person manually adjusted the clock phase while checking the screen to minimize the noise and jitter, but there was a problem that it was not easy to perform the adjustment accurately. Was.

[0003]

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a video processing apparatus in which the phase of a clock signal is automatically corrected to an appropriate phase to prevent a deterioration in image quality mainly at the time of a still image. The purpose is to:

[0004]

According to the present invention, an analog input video signal is sampled by a sampling clock,
An A / D converter for converting to digital video data; a sampling clock generator for generating the sampling clock; and a difference between video data between successive fields based on the digital video data from the A / D converter. Detecting means for detecting whether a still image is present in the input video signal based on the difference data from the difference detecting means, and determining the difference when the determining means determines that the image signal is a still image. It is an object of the present invention to provide a video processing apparatus comprising: control means for shifting the phase of a sampling clock generated by the sampling clock generation means so that the difference in the detection means is equal to or less than a preset value.

The sampling clock generating means comprises a clock generating unit for generating a clock and a phase adjusting unit for shifting the phase of the clock from the clock generating unit.

Further, the clock generator is constituted by a PLL circuit which generates a clock based on a horizontal synchronizing signal separated from the input video signal.

Further, the phase adjuster is configured by cascade-connecting a plurality of delay circuits for delaying the clock signal by a predetermined time, and providing a tap at an output terminal of each delay circuit.
The required delay time is set by selecting the position of the tap.

Further, the difference detecting means detects a difference between current field data and field data from the memory unit, and a memory unit for storing video data from the A / D conversion unit for one field. And a difference detection unit.

[0009] The detection of the difference by the difference detection means may be detected from video data between successive frames.

Further, the difference detecting means detects a difference between current frame data and frame data from the memory, and a memory for storing video data from the A / D converter for one frame. It may be configured with a difference detection unit.

In the determination by the determination means, the input video signal is determined to be a still image when the difference data from the difference detection means is equal to or less than a predetermined value.

[0012]

Embodiments of the present invention will be described below with reference to the drawings based on embodiments. FIG. 1 is a main block diagram showing an embodiment of a video processing apparatus according to the present invention.
Is an explanatory diagram of sampling. In FIG. 1, Si is an analog input video signal, and 1 is an input video signal Si clock CKs.
A to sample and convert to digital video data
/ D conversion unit. Reference numeral 2 denotes a clock generation unit that generates a clock CCo using a horizontal synchronization signal HD separated from the input video signal Si as a reference signal. The clock generation unit 2 is constituted by, for example, a PLL circuit. Reference numeral 3 denotes a phase adjustment unit that shifts the phase of the clock CKo from the clock generation unit 2 and outputs a clock CKs having an appropriate phase.

Reference numeral 4 denotes a memory unit, which temporarily stores the digital video data from the A / D conversion unit 1 in field units or frame units and then reads out the digital image data. Reference numeral 5 denotes a difference detection unit that detects a difference between the digital video data from the A / D conversion unit 1 and the digital video data read from the memory unit 4. Note that the memory unit 4 and the difference detection unit 5 serve as difference detection means. Reference numeral 6 denotes a determination unit which determines whether or not the input video signal Si is a still image based on the detection result of the difference detection unit 5. Reference numeral 7 denotes a control unit (control means) that controls still image determination by the determination unit 6 and phase adjustment by the phase adjustment unit 3 based on the detection result of the difference detection unit 5. Note that the clock generator 2 and the phase adjuster 3 under the control of the controller 7 serve as sampling clock generators,
The judging unit 6 is used as judging means.

Next, the operation of the present invention will be described. The analog input video signal Si is sampled by the clock CKs in the A / D converter 1, converted into digital video data, and temporarily stored in the memory 4. As a form of the storage, either a field unit or a frame unit may be used. After the storage, the video data is read and input to the difference detection unit 5. On the other hand, A /
The data from the D conversion unit 1 is also directly input. Therefore, when the memory unit 4 is a field memory, the current video data and the video data one field before are input to the difference detection unit 5. The difference detection unit 5 detects the difference between the two data on a pixel-by-pixel basis, and obtains the sum of the difference data. When the memory unit 4 is a frame memory, the difference is data between frames.

Data relating to the sum of the difference data is sent to the determination unit 6 via the control unit 7, where it is determined whether or not there is a still image. In this case, when the data relating to the sum total of the difference data is equal to or less than the first reference value set in advance, it is determined that the image is a still image. When the determination unit 6 determines that the image is a still image, the control unit 7 continuously performs the following processing. In the case of a still image, video data between one successive field or one frame is essentially the same, and if accurate sampling is performed in the A / D converter 1, the difference between the two is zero or very small. Should be a value. However, since the phase of the clock CKs is inappropriate, when the sampling as shown in FIG. 2A is performed, the difference between the two does not become zero or a small value.
The value will be larger than this. Accordingly, if the phase of the clock signal CKs is set so that the difference between video data between one field or one frame before and after becomes zero or a minute value, the phase becomes an appropriate phase. Therefore, when the determination unit 6 determines that the image is a still image, the control unit 7 monitors the difference data from the difference detection unit 5 and determines that the difference data is equal to or less than a predetermined second reference value (zero or minute value). The phase of the phase adjustment unit 3 is shifted so as to be as follows.

The phase adjusting section 3 connects delay circuits (DL) in a required number of stages in cascade as shown in FIG. 1 and sets a delay time for each delay circuit (for example, 1/16 clock time). , And taps (a to
n) is provided, and the required delay time is set by selecting this tap. As a result, the phase of the clock CCo generated by the clock generator 2 is shifted. Control unit 7
When the difference data between a certain field (or frame) and the immediately preceding field (or frame) exceeds the second reference value, the tap position of the phase adjustment unit 3 is set in the direction of a → n. For example, the data is shifted by one, and the difference data from the difference detection unit 5 is monitored. If the difference data still exceeds the second reference value, the tap position is further switched to the direction of n, the delay time is increased, and the difference data from the difference detector 5 is monitored.
This process is repeated to set the tap position at which the difference data becomes equal to or less than the second reference value. When set as described above, the phase relationship between the clock signal CKs and the video signal Si is as shown in FIG. 2B, and sampling is performed at a level change point (point A or point B) as shown in FIG. And the sampling data is stabilized, thereby preventing the above-described noise and jitter from occurring.

[0017]

As described above, according to the present invention, P
In still image processing in a digital video processing device such as DP, the phase of a sampling clock used in an A / D converter provided in a signal input stage can be automatically set to an appropriate phase. This eliminates the need for conventional advanced manual adjustment, enables high-accuracy phase setting, and prevents the occurrence of noise and jitter in displayed images. From the above, it can be said that the present invention can contribute to the performance improvement of the digital video processing device.

[Brief description of the drawings]

FIG. 1 is a main block diagram showing an embodiment of a video processing apparatus according to the present invention.

FIG. 2 is an explanatory diagram of sampling by a clock signal.

[Explanation of symbols]

 Si analog input video signal 1 A / D conversion unit 2 Clock generation unit 3 Phase adjustment unit 4 Memory unit 5 Difference detection unit 6 Judgment unit 7 Control unit

Claims (8)

[Claims] An A / D converter for sampling an analog input video signal with a sampling clock and converting the input video signal into digital video data; a sampling clock generator for generating the sampling clock; Difference detecting means for detecting a difference between video data between successive fields based on digital video data; and determining whether the input video signal is a still image based on the difference data from the difference detecting means. Determining means;
Control means for shifting a phase of a sampling clock generated by the sampling clock generating means so that a difference in the difference detecting means is equal to or less than a preset value when the determination means determines that the image is a still image. A video processing device characterized by the above-mentioned. 2. The method according to claim 2, wherein the sampling clock generating means includes:
2. The video processing device according to claim 1, further comprising: a clock generation unit that generates a clock; and a phase adjustment unit that shifts a phase of the clock from the clock generation unit. 3. The clock generator according to claim 2, wherein the clock generator comprises a PLL circuit that generates a clock based on a horizontal synchronization signal separated from the input video signal.
The video processing device according to the above. 4. The phase adjuster is configured by cascade-connecting a plurality of delay circuits for delaying the clock signal by a predetermined time and providing taps at output terminals of the respective delay circuits, and selecting a position of the tap. 3. The video processing apparatus according to claim 2, wherein the delay time is set to a required delay time. 5. The difference detecting means detects a difference between current field data and field data from the memory unit, wherein the memory unit stores video data from the A / D conversion unit for one field. 2. The video processing device according to claim 1, further comprising a difference detection unit. 6. The video processing apparatus according to claim 1, wherein the detection of the difference by the difference detection means is detected from video data between successive frames. 7. A difference detecting means for detecting a difference between current frame data and frame data from the memory unit, wherein the memory unit stores video data from the A / D conversion unit for one frame. The video processing device according to claim 7, further comprising a difference detection unit. 8. The video according to claim 1, wherein the determination by said determination means determines that said input video signal is a still image when the difference data from said difference detection means is equal to or less than a preset value. Processing equipment.