JP2002278495A - Sampling phase adjusting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sampling phase adjusting circuit capable of automatically adjusting a proper sampling point. SOLUTION: The sampling phase adjusting circuit is provided with a clock phase control part 30 for detecting the best point of a sampling clock phase to a video signal based on an A-D converted video data value and controlling the clock phase, and this clock phase control part 30 is provided with either the one which detects such a sampling clock phase as maximizes a mean value of the video data for a specified period to set the best point, or the one which detects such a sampling clock phase as minimizes an integral value to set the best point, or both of them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for a video display using a digital display device such as a PDP, an LCD, etc. The present invention relates to a phase adjustment circuit.

[0002]

2. Description of the Related Art As shown in FIG. 6, a signal processing circuit of a video display receives an analog video signal from a video signal input terminal 10 and sends it to an analog signal processing circuit 11 and a sync separation circuit 14. The synchronization separation circuit 14 separates the synchronization signal from the input video signal, adjusts the phase in the PLL circuit 15, and outputs a sampling clock. The analog video signal processed by the analog signal processing circuit 11 as shown in FIG. 7A is output from the PLL circuit 15 as shown in FIG.
A / D conversion is performed in the A / D conversion circuit 12 by the sampling clock as shown in FIG. 7, and A / D conversion output data as shown in FIG. 7C output from the A / D conversion circuit 12 is obtained. . The A / D conversion output data is assigned to each pixel of the display 16 by the digital signal processing circuit 13, and one video data is displayed on one pixel as shown in FIG.

Here, the rising sampling point of the sampling clock as shown in FIG.
If the timing coincides with the timing of the white level or the black level as shown in (a), there is no need to adjust the sampling point, indicating an appropriate state.

However, an A / D as shown in FIG.
If there is a phase shift as shown in FIG. 8B-1 with respect to the converted input signal, the output data as shown in FIG. t11, t1
3,... Sometimes black level, but t12, t14,.
Sometimes a white level is not obtained and a gray level is obtained. Similarly, if there is a phase shift as shown in FIG. 8B-2, the output data as shown in FIG.
As shown in -2), at times t22, t24,..., The black level is obtained, but at times t21, t23,. Therefore, the luminance level of the display screen decreases.

[0005] In addition, if jitter of the sampling clock occurs before and after the rise of the black level or the fall of the white level in the A / D conversion input signal shown in FIG. . For example, FIG.
(B-1) and the sampling clock t in FIG.
When jitter occurs at t12 and t22, the display 16
The display changes repeatedly from black to gray or vice versa, causing unstable fluctuations in the displayed image. The same applies to other sampling clocks.

In order to adjust the above-mentioned phase shift, a circuit for manually adjusting the phase as shown in FIG. 9 has been proposed. In FIG. 9, based on a horizontal synchronization signal input from a horizontal synchronization signal input terminal 17, a phase comparator 18, LP
PLL circuit 1 including F19, VCO 20, and frequency divider 21
At 5, the clock data as shown in FIG. A clock having no delay from the PLL circuit 15 is set to an output 0, and is input to the selector 24. The clock of the PLL circuit 15 is supplied to the shift register 22.
10 (c) is output from the shift register 22 to the multiplier 23 as shown in FIG. 10 (b). The outputs 1, 2,..., 7 whose phases are shifted by one clock from the multiplier 23 as shown in FIG. The operator manually sends a switching control signal to the switching signal input terminal 25 while watching the screen from among the outputs 0, 1, 2,..., And selects a sampling clock to make adjustments so that an appropriate image can be obtained.

[0007]

In the above-described conventional circuit, the operator manually adjusts the phase for setting an appropriate sampling point when A / D converting a video signal while looking at the screen. Since adjustment is performed to obtain an appropriate image, there is a problem that complicated adjustment work is required.

An object of the present invention is to provide a sampling phase adjusting circuit capable of automatically adjusting a proper sampling point.

[0009]

SUMMARY OF THE INVENTION A first embodiment of the present invention comprises:
When the video signal is A / D converted, the average video data of one field at each sample point is sequentially calculated by utilizing the fact that the luminance is reduced if the sampling point is not appropriate, and the point which becomes the largest is detected. The gist of the present invention is to automatically set the sampling phase by automatically setting the sampling clock phase at that point.

In a second embodiment of the present invention, an image signal is converted to an A / D signal.
When converting, if the sampling point is not correct,
Using the fact that the video data value becomes unstable due to the jitter of the sampling clock, the field integrated value of the video data at each sample point is calculated twice, and these differences are sequentially compared, and the point where the difference becomes the smallest is calculated. Is detected, and the sampling clock phase is automatically set at that point, thereby automating the sampling phase adjustment.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described with reference to the drawings. 1, an analog signal processing circuit 11 connected to a video signal input terminal 10 and an A / D conversion circuit 1
2, digital signal processing circuit 13, display 16,
The sync separation circuit 14 and the PLL circuit 15 are circuits similar to the circuit configuration shown in FIG. 6, and the shift register 22, the multiplier 23, and the selector 24 connected to the subsequent stage of the PLL circuit 15 are shown in FIG. This is a circuit similar to the circuit configuration shown. The present invention is characterized in that a clock phase control unit 30 is inserted in order to automate sampling phase adjustment.

A first embodiment of the present invention will be described with reference to FIGS. The gist of the first embodiment of the present invention is to detect the maximum value of the average video data, and FIG.
FIG. 3 shows a detailed block diagram of the clock phase control unit 30 in the embodiment. In FIG. 2, the input side of the video data 1-field average value calculation unit 34a has an A / D
A / D conversion output data input terminal 3 from conversion circuit 12
1. A sampling clock input terminal 32 from the selector 24 and a VD input terminal 33 from the sync separation circuit 14 are connected. On the output side, a first register 35 for storing video data and a second register 36 for storing video data Are sequentially connected, and a comparator 37 is connected to the output side of the first register 35 for storing video data and the second register 36 for storing video data.

The input side of the control section 41 is connected to the VD input terminal 33 and the start signal input terminal 40. One output side of the control section 41 has a first switch control signal first terminal.
The register 38 is connected to one input side of the third switch circuit 44. The output side of the first register 38 for switching control signal is connected to the second register 39 for switching control signal. Further, the third switch circuit 4
4 is connected to the other input side. The VD input terminal 33 is connected to the control unit 41 and is connected to a first switch 35 for storing video data through a first switch circuit 42.
And a switching control signal first register 38, and further connected to a video data storage second register 36 and a switching control signal second register 39 via a second switch circuit 43. The first switch circuit 42 and the third switch circuit 44 are controlled to be switched by the other output of the control unit 41, and the second switch circuit 43 includes a comparator 37
Are switched and connected by the output of. Switching signal input terminal 2
The switching signal 5 controls the automatic switching of the selector 24.

In the above circuit, the video data one-field average value calculating section 34a calculates the average value of one field of the A / D conversion output data from the A / D conversion output data input terminal 31, and for each VD. It outputs the calculated value. The control section 41 outputs a switching signal to be supplied to the selector 24 in FIG. 1 and outputs a switching control signal for the first switch circuit 42 and the third switch circuit 44 in FIG. Also, the control unit 41
When the start signal is input, the switching controls 1 to n are set to 1
After sequentially outputting for each field and outputting the switching control n,
The switching control of the third switch circuit 44 is performed one field later. The first register 3 for storing video data
5, video data storage second register 36, comparator 37,
The second switch circuit 43 compares the average value for each field and compares the large data with the second data for storing the video data.
It is stored in the register 36. At the same time, the switching control signal corresponding to the data stored in the video data storing second register 36 is stored by the switching control signal first register 38 and the switching control signal second register 39.

The operation of the circuit shown in FIG. 2 will be described with reference to FIG. As shown in (a), a start signal is sent from the start signal input terminal 40 to the control unit 41 at the time of power supply switching, video signal switching, or the like. This start signal is maintained until the next start. With this start signal, a control output D of the control unit 41 as shown in (i) appears, and the first switch circuit 42 is turned on. Further, the control section 41 outputs the switching control signals 1 to n shown in (c) every time the VD signal from the VD input terminal 33 shown in (b) rises. Also, a VD signal as shown in (b) is sent from the VD input terminal 33 to the video data 1-field average value calculation unit 34a and the control unit 41. In the video data 1-field average value calculation unit 34a, the A / D conversion output data input terminal 31
The average value of one field of the A / D conversion output data from is calculated, and the calculated value is output to the video data storage first register 35 for each VD.

The first register 35 for storing video data includes:
At t3, the average video data 1 from the video data 1 field average value calculation unit 34a is stored. During the detection period from t3 to t4, the data B1 and the video data storage second register 3 are stored.
The data A1 of No. 6 is compared by the comparator 37. t3-t
In the detector period of No. 4, the second register 36 for storing video data
Is set to 0, A1 <B1, and the second switch circuit 43 is turned on at t3 immediately after the start of comparison as shown in (f). Accordingly, the VD clock is sent to the video data storage second register 36, and the average video data 1 from the video data storage first register 35 is stored in the video data storage second register 36 at t4. In synchronization with the transfer of the average video data from the video data storage first register 35 to the video data storage second register 36, the switching control signal 1 shown in (e) also shifts as shown in (h).

With the next VD clock, the average video data 2 from the video data 1-field average value calculation unit 34a is stored in the video data storage first register 35 at time t5, and the data is stored in the detection period from t5 to t6. B2 and data A2 (corresponding to B1) corresponding to the average video data 1 stored in the video data storage second register 36 immediately before.
Are compared by the comparator 37. Assuming that the average video data 2 has the maximum value, A2 (= B1) <B2,
The second switch circuit 43 continues to be turned on as shown in (f). Accordingly, the VD clock is sent to the video data storage second register 36, and the video data storage first register 3
The average video data 2 from 5 is stored in the second video data storage register 36 at t6. First for saving video data
In synchronization with the shift of the average video data from the register 35 to the second video data storage register 36, the switching control signal 2 shown in (e) also shifts as shown in (h).

Further, at the next VD clock, the first video data storage register 35 stores the video data 1 at t7.
Average video data 3 from the field average value calculation unit 34a
Is stored, and during the detection period from t7 to t8, the data B3
The comparator 37 compares the data A3 (corresponding to B2) corresponding to the average video data 2 stored in the video data storage second register 36 immediately before. Since the average video data 2 is assumed to be the maximum value, A3 (= B2)> B
3, the second switch circuit 43 is turned off as shown in FIG. Then, the VD clock becomes the second video data storage.
The average video data 3 from the video data storage first register 35 is not sent to the register 36 and is not stored in the video data storage second register 36. First for saving video data
Since the average video data does not shift from the register 35 to the video data storage second register 36, the switching control signal 2 shown in (e) does not shift as shown in FIG. 39, and output via E of the third switch circuit 44. In this way,
The switching control signal from the switching control signal second register 39 is sent to the selector 24, and the selector 24 detects the point where the average video data of one field at each sample point becomes largest, and sets the sampling clock phase to that point. By automatically setting, the optimum sampling phase is adjusted.

Next, a second embodiment of the present invention will be described with reference to FIGS. The gist of the second embodiment of the present invention is to calculate twice the field integrated value of the video data at each sample point, compare these differences sequentially, and detect the point where the difference is the smallest. FIG. 4 shows a detailed block diagram of the clock phase control unit 30 in the second embodiment. The difference from the first embodiment is that
The video data one-field integrated value calculation unit 34b calculates the integrated value of one field. The difference detector 45 calculates the integrated value data of each of the video data storage first register 35 and the video data storage second register 36. , The comparator 37 compares the difference with the next difference, the third register 46 for storing the difference data stores the small difference data, and the second register 39 for the switching control signal. Is to output a switching control signal at the time of the minimum difference value.

More specifically, the video data one-field integrated value calculating section 34b calculates the integrated value of one field of the A / D conversion output data from the A / D conversion output data input terminal 31, and calculates the calculated value for each VD. Is output. The control section 41 outputs a switching signal given to the selector 24 in FIG. 1 and outputs a switching control signal for the first switch circuit 42 and the third switch circuit 44 in FIG. When the start signal is input, the control unit 41 sequentially outputs the switching controls 1 to n every two fields, outputs the switching control n for two fields, and after one field, the first switch circuit 42. The switching of the third switch circuit 44 is controlled.

The first register 35 for storing video data,
The second register 36 for storing video data, the third register 46 for storing difference data, the difference detector 45, the second switch circuit 43, and the comparator 37 compare the difference between the two integrated values of the fields to obtain a small difference value. The data is stored in the third register 46 for storing difference data. At the same time, the switching control signal first register 38 and the switching control signal
The third register 4 for storing difference data is provided by the register 39.
6 stores a switching control signal corresponding to the data stored in. The first switch circuit 42 includes a first register 35 for storing video data, a second register 36 for storing video data, a third register 46 for storing differential data, a first register 38 for a switching control signal, and a second register 38 for a switching control signal.
The clock of the register 39 is passed or stopped, and the operation and non-operation of the circuit are controlled.

The operation of the circuit shown in FIG. 4 will be described with reference to FIG. From the start signal input terminal 40, a start signal is sent to the control unit 41, as shown in (a), and is maintained until the next start. With this start signal, a control output D of the control unit 41 as shown in FIG. 4C appears, and the first switch circuit 42 is turned on. Also, from the control unit 41,
Each time the VD signal from the VD input terminal 33 shown in (b) rises, the switching control signals 1 to n shown in (e) are output.
Further, a video data one-field integrated value calculation unit 34b, a first switch circuit 42, a control unit 41
A VD signal as shown in (b) is sent to the first switch circuit 42, and a clock signal as shown in (d) is sent from the first switch circuit 42 to the first register 35 for storing video data, the second register 36 for storing video data, The signal is sent to the first register 38 and the frequency divider 47. The video data one-field integrated value calculation unit 34b calculates the integrated value of one field of the A / D conversion output data from the A / D conversion output data input terminal 31, and outputs the calculated value for each VD. In the frequency divider 47, the first
The clock of the switch circuit 42 is frequency-divided by 1/2, and the clock shown in (i) is output.

The first register 35 for storing video data includes:
t1, t3, t5,..., the integrated value data 1-1, 1-2, 2 from the video data 1 field integrated value calculating unit 34b.
-1,... Are sequentially stored as shown in (f), and the video data storage second register 36 stores t3, t5, t7,.
.. From the video data storage first register 35 are sequentially shifted as shown in FIG. The data of the first register 35 for storing video data and the second register 36 for storing video data are
The difference is detected by the difference detector 45 as shown in (h). This difference is sequentially stored as shown in (j) by the clock divided by の of the frequency divider 47.

The data B1 of the difference detector 45 and the data A1 of the third register 46 for storing difference data are compared by a comparator 37. At this time, the comparison between adjacent fields is invalid, and the comparison between the same fields is valid. t3 to t4
In the detector period, the difference data storage third register 46 is set to 0, and A1 <B1, but if the video data integrated value difference of the switching control n = 2 is the minimum, t7 to The detector period at t8 is A2> B2.
Therefore, the second switch circuit 43 is turned on, the switching control signal from the first register 38 for switching control signal is sent to the second register 39 for switching control signal and stored therein, and thereafter the switching control signal 2 is continuously output. The switching control signal is output from the second register 39. In this way, the switching control signal from the switching control signal second register 39 is sent to the selector 24, and the selector 24 detects the point where the integrated value data of one field at each sample point becomes the smallest, and detects the sampling clock. By automatically setting the phase to that point, the optimal sampling phase is adjusted.

In the above-described embodiment, when the video signal is A / D converted, the average video data of one field at each sample point is sequentially calculated and compared by utilizing the fact that the brightness is reduced if the sampling point is not appropriate. In the first embodiment, the largest point is detected and the sampling clock phase is automatically set to that point. When the video signal is A / D converted, if the sampling point is not appropriate, the sampling clock Taking advantage of the fact that the image data value becomes unstable due to jitter, the field integrated value of the image data at each sample point is calculated twice, and these differences are sequentially compared to detect the point where the difference becomes the smallest. And the second embodiment, in which the sampling clock phase is automatically set at that point, are independent from each other. However, the present invention can be provided with the first embodiment and the second embodiment at the same time, and in any case, the sampling phase adjustment can be automated.

In the above-described embodiment, the clock phase control unit 30 can be realized by a firmware method using a microcomputer, so that the hardware can be simplified and standardized.
There is an advantage that an instruction repertoire different from the standard can be used by changing the contents of M and RAM.

[0027]

According to the first aspect of the present invention, the best point of the sampling clock phase for the video signal is determined by the A / D
A clock phase control unit that detects a converted video data value and controls a clock phase based on the converted video data value; Since the best point is set by detecting the clock phase, the decrease in the luminance level of the display screen can be automatically adjusted.

According to the second aspect of the present invention, the clock phase control unit 30 switches between the video data average value calculation unit 34a, the video data storage first register 35, and the video data storage second register 36. First register 3 for control signal
8, the second register 39 for the switching control signal, and the comparator 3
7 is effective when it is mainly used for still images.

According to the third aspect of the present invention, since the control unit 41 for sequentially outputting a data storage clock switching control signal for selecting a sampling clock phase point at predetermined time intervals is provided, Sequential storage of video data, comparison of data, and control of output timing of the switching control signal are smoothly performed.

According to the fourth aspect of the present invention, the video data average value calculating section a sequentially calculates the average value of one field of the video data, so that the circuit configuration is simpler than the pixel unit. Can be configured.

According to the fifth aspect of the present invention, the clock phase control unit 30 detects the best point of the sampling clock phase for the video signal based on the A / D converted video data value and controls the clock phase. The clock phase control unit 30 detects the sampling clock phase at which the integral value of the video data in a predetermined period is minimized and sets the best point, so that the display image is unstable. The occurrence of shaking can be automatically adjusted.

According to the sixth aspect of the present invention, the clock phase control unit 30 includes a video data integration value calculation unit 34b, a video data storage first register 35, a video data storage second register 36, Since it includes the detector 45, the third register 46 for storing difference data, the first register 38 for the switching control signal, the second register 39 for the switching control signal, and the comparator 37, not only a still image but also a However, it is effective to adopt it for moving images.

According to the seventh aspect of the present invention, since the video data integrated value calculating section 34bb sequentially calculates the integrated value between two fields of the video data, the circuit configuration is simpler than the pixel unit. Can be configured.

According to the eighth aspect of the present invention, since the control unit 41 for sequentially outputting a data storage clock switching signal for selecting a sampling clock phase point for each field is provided, And the timing of switching control and the like can be smoothly performed.

According to the ninth aspect of the present invention, the clock phase controller 30 detects the best point of the sampling clock phase for the video signal based on the A / D converted video data value and controls the clock phase. The clock phase control unit 30 detects the sampling clock phase at which the average value of the video data in a predetermined period is maximum and sets the best point, and the integrated value of the video data in a predetermined period. That detects the sampling clock phase such that the minimum value is obtained and sets the best point, it is possible to automatically adjust the decrease in the brightness level of the display screen and to make the display image unstable. It is possible to automatically adjust the occurrence of the shaking.

According to the tenth aspect of the present invention, since the clock phase control unit 30 is realized by a firmware method using a microcomputer, the hardware can be simplified and standardized.
By changing the contents of the ROM or RAM, an instruction repertoire different from the standard can be used.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a sampling phase adjusting circuit according to the present invention.

FIG. 2 is a detailed block diagram showing a first embodiment of a clock phase control unit 30 in FIG. 1;

FIG. 3 is an operation waveform diagram of each unit in FIG. 2;

FIG. 4 is a detailed block diagram showing a second embodiment of the clock phase control unit 30 in FIG. 1;

FIG. 5 is an operation waveform diagram of each unit in FIG. 4;

FIG. 6 is a block diagram showing a conventional sampling phase adjustment circuit.

7 is an operation waveform diagram of each unit in the case of a proper sampling clock in the sampling phase adjustment circuit shown in FIG. 6;

8 is an operation waveform diagram of each unit in the case of an inappropriate sampling clock in the sampling phase adjustment circuit shown in FIG.

FIG. 9 is a block diagram of a sampling phase adjustment circuit in the case where a conventional manual phase adjustment is performed.

10 is an operation waveform diagram of each unit in FIG. 9;

[Explanation of symbols]

10: video signal input terminal, 11: analog signal processing circuit, 12: A / D conversion circuit, 13: digital signal processing circuit, 14: synchronization separation circuit, 15: PLL circuit, 16 ...
Display, 17: Horizontal synchronization signal input terminal, 18: Phase comparator, 19: LPF, 20: VCO, 21: Frequency divider, 22: Shift register, 23: Multiplier, 24: Selector, 25: Switching signal input terminal , 26 ... Sampling clock output terminal, 30 ... Clock phase controller, 31 ...
A / D conversion output data input terminal, 32 ... Sampling clock input terminal, 33 ... VD input terminal, 34a ... Video data 1 field average calculation unit, 34b ... Video data 1
Field integration value calculation unit, 35...
Register, 36: second register for storing video data, 37
... Comparator, 38 ... First register for switching control signal, 39
... second register for switching control signal, 40 ... start signal input terminal, 41 ... control unit, 42 ... first switch circuit, 4
3: second switch circuit, 44: third switch circuit, 45
... difference detector, 46 ... third register for storing difference data,
47 ... frequency divider.

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 5C021 PA18 PA28 PA54 PA56 PA58 PA62 PA64 PA66 PA76 PA85 PA87 RA07 RC01 XC00 YC01 YC10 5C080 AA05 AA10 BB05 DD01 EE28 JJ02 JJ04 5K047 AA15 DD02 GG02 MM45 MM46 MM55 MM62

Claims (10)

[Claims] A clock phase control unit that detects a best point of a sampling clock phase for a video signal based on an A / D-converted video data value and controls a clock phase; The sampling phase adjusting circuit is characterized in that the section 30 detects the sampling clock phase at which the average value of the video data in a predetermined period becomes maximum and sets the best point. 2. The clock phase control unit 30 includes a video data average value calculation unit 34a that sequentially calculates an average value of video data in a predetermined period, and a video data average value calculation unit 34.
a first video data storage register 35 for sequentially storing the output video data a, a video data storage second register 36 for sequentially storing the output video data of the video data storage first register 35 after a predetermined period, A first switching control signal register 38 for sequentially storing a switching control signal corresponding to the video data storing first register 35 and a switching control signal corresponding to an output of the video data storing second register 36 are sequentially transmitted after a predetermined period. The data of the switching control signal second register 39 to be saved, the data of the video data saving first register 35 and the data of the video data saving second register 36 are compared, and the video data average is stored in the video data saving second register 36. The maximum value of the output video data of the value calculation unit 34a is stored, and the switching control signal second register 39 stores the maximum value. A comparator 37 for outputting a signal for storing a switching control signal for selecting the best point of the sampling clock phase corresponding to the output of the image data storing second register 36. 2. The sampling phase adjustment circuit according to 1. 3. A control unit according to claim 2, further comprising a control unit for sequentially outputting a data storage clock switching control signal for selecting a sampling clock phase point at predetermined time intervals. Sampling phase adjustment circuit. 4. The sampling phase adjusting circuit according to claim 2, wherein the video data average value calculating section a sequentially calculates an average value for one field of the video data. 5. A clock phase control unit 30 for detecting a best point of a sampling clock phase for a video signal based on an A / D-converted video data value and controlling a clock phase. The unit 30 calculates at least two or more integrated values of the video data during a predetermined period, detects a sampling clock phase that minimizes the difference between them, and sets the best point. Sampling phase adjustment circuit. 6. A clock phase control section 30 includes a video data integration value calculation section 34b for sequentially calculating integration values of video data in a predetermined period, and a video data integration value calculation section 34.
b, a video data storage first register 35 for sequentially storing output video data b, a video data storage second register 36 for sequentially storing output video data of the video data storage first register 35 after a predetermined period, A difference detector 45 for detecting difference data between the first register 35 for storing video data and the second register 36 for storing video data, a third register 46 for storing difference data of the difference detector 45, A first switch control signal register 38 for sequentially storing a switch control signal corresponding to the video data storage first register 35 and a switch control signal corresponding to the output of the difference data storage third register 46 after a predetermined period of time. A second register 39 for a switching control signal for sequentially storing the data, and a data for the difference detector 45 and a third register 46 for storing the differential data. And stores the minimum value of the difference value between at least two or more pieces of video data output from the video data integrated value calculation unit 34b in the third register 46 for storing difference data. In the second register 39, the third register 46 for storing the differential data is stored.
6. The sampling phase adjusting circuit according to claim 5, further comprising a comparator for outputting a signal for storing a switching control signal for selecting a best point of the sampling clock phase corresponding to the output of the sampling phase adjusting circuit. 7. The sampling phase adjusting circuit according to claim 6, wherein the video data integrated value calculation section calculates the integrated value between two fields of the video data sequentially. 8. The sampling system according to claim 7, further comprising a control unit for sequentially outputting a data storage clock switching signal for selecting a sampling clock phase point for each field. Phase adjustment circuit. 9. A clock phase control unit 30 for detecting a best point of a sampling clock phase for a video signal based on an A / D-converted video data value and controlling a clock phase. The unit 30 detects the sampling clock phase such that the average value of the video data in a predetermined period is maximum and sets the best point, and calculates at least two or more integral values in the predetermined period of the video data, A sampling clock phase that minimizes these differences and sets the best point. 10. The sampling phase adjusting circuit according to claim 1, wherein the clock phase control unit is realized by a firmware method using a microcomputer.