JP3486343B2 - Video signal processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a video signal processing apparatus that samples and digitizes a video signal and then processes and displays the video signal. The present invention relates to a simple video signal processing device. FIG. 8 shows a block diagram of a conventional video signal processing apparatus. 8, reference numeral 1 denotes an A / D converter for converting an input analog video signal to a digital video signal;
Is a video signal processing circuit for processing a digitized video signal, 3 is a video display device for displaying the processed video signal, 4 is a delay circuit for delaying a horizontal synchronization signal, and 9 is the A / D converter 1 And a clock generation circuit 8 for supplying a clock to the video signal processing circuit 2, and a system microcomputer 8 for controlling the video signal processing device. The clock generation circuit 9 includes a phase comparator 5 and a VCO (Voltage Controlled).
Oscillator (voltage controlled oscillator) 6, 1 /
An N frequency dividing circuit 7 is provided. FIG. 9 shows the configuration of the delay circuit 4. As shown in FIG. In FIG. 9, reference numeral 11 denotes a delay element for delaying the horizontal synchronization signal, and reference numeral 12 denotes a multiplexer for selecting and outputting a horizontal synchronization signal having a delay amount selected by a selection signal from the system microcomputer 8. Hereinafter, the operation will be described. The video signal input to the video signal processing device is sampled by the A / D converter 1 with the clock from the clock generation circuit 9 and converted into a digital signal. After that, the video signal processing circuit 2 performs appropriate video processing, and the video signal is displayed on the video display device 3. Here, the gain of the VCO 6 is set by the frequency of the input horizontal synchronizing signal and the like, and the numerical value N in the 1 / N frequency dividing circuit 7 which is generally called a frequency dividing ratio is determined by the frequency of the horizontal synchronizing signal and the vertical Based on the frequency of the synchronizing signal, a comparison with the standard is made and a numerical value that can be expected to be optimal is set. However, a signal conforming to the standard is not always input, and if this frequency division ratio is not appropriate,
There is a problem that the sampling of the video signal is not correctly performed in the A / D converter 1 and the quality of the image is deteriorated. Therefore, in order to avoid the above problem, by providing means for changing the frequency dividing ratio N in the 1 / N frequency dividing circuit 7 via the system microcomputer 8 by the operation of the user, It is configured to have a frequency division ratio adjusting means for adjusting an optimum point visually. On the other hand, the analog phase difference between the horizontal synchronizing signal and the video signal is not defined by the standard, and it cannot be expected due to a delay due to wiring as a design problem. There is also a problem that the sampling of the video signal is not correctly performed by the converter 1 and, in some cases, a flickering noise occurs particularly in a high-contrast portion of the screen, thereby deteriorating the image quality. [0010] To solve the problem, a method shown in FIG. 10 is employed. In FIG. 10, the clock phase at which the sampling of the video signal is not performed correctly by the A / D converter 1 is referred to as a dot clock 1, and the phase of the horizontal synchronization signal at this time is H.
It is assumed that the synchronization signal is 1. In this case, a horizontal synchronizing signal (H synchronizing signal 2) is generated by delaying the horizontal synchronizing signal of the video signal by the delay circuit 4 by the selection signal from the system microcomputer 8, and is supplied to the A / D converter 1. The phase of the sampling clock of the video signal in the A / D converter 1 is set to the phase shown by the dot clock 2 as a reference for generating a clock to be generated. The A / D converter 1 is operated by the dot clock 2.
The above-mentioned problem is solved by sampling the video signal. Here, the delay amount of the horizontal synchronizing signal can be visually adjusted by a user to a high-quality place, and a clock phase adjusting means for this purpose is provided. [0014] However, as described above, these adjustments are left to the user, but these adjustments are difficult and troublesome for the user, and use with low image quality is not possible. Can possibly happen. An object of the present invention is to reproduce a high-quality display without bothering the user by automatically performing the division ratio adjustment and the phase adjustment entrusted to the user. is there. Means for Solving the Problems The present invention has the following configuration to solve the above problems. That is, in a video signal processing device that digitally processes and displays a video signal, the square of the absolute value of the signal level difference between adjacent picture elements is calculated, and the sum of the calculated values for one screen is calculated. A delay circuit for delaying a horizontal synchronizing signal separated from a video signal, and a clock generation circuit having a frequency dividing circuit, wherein a delay amount of the delay circuit and the clock generation are determined by a calculation result of the calculation circuit. This is a video signal processing device whose main purpose is to adjust a sampling phase and a frequency division number at which a video signal can be appropriately sampled by controlling a frequency division ratio of a frequency dividing circuit of the circuit. FIG. 1 is a block diagram showing an embodiment of the present invention. 1, the same components as those in FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted. Hereinafter, the operation of the video signal processing device of the present invention will be described. The video signal input to the video signal processing device is sampled by the A / D converter 1 with the clock from the clock generation circuit 9 and converted into a digital signal. After that, the video signal processing circuit 2 performs appropriate video processing, and the video signal is displayed on the video display device 3. The video signal converted into a digital signal by the A / D converter 1 is input to a phase detection operation circuit 10. Here, the phase detection arithmetic circuit 10 is a circuit for calculating and storing the square of the difference between adjacent video signals on a screen basis, and its block diagram is shown in FIG. In FIG. 2, reference numeral 13 denotes a one-pixel delay circuit;
4 is a difference circuit which takes the absolute value of the difference between the signal delayed by one picture element and the signal which is not delayed, and 15 is the output 2 of the difference circuit.
A squaring circuit for calculating the power, 16 is an adding circuit, and 17 and 18 are registers. The absolute value of the difference between the digital signal input to the phase detection operation circuit 10 and the signal delayed by the one-pixel delay circuit 13 is arithmetically operated by the difference circuit 14. This means that the difference between the signal levels of adjacent video signals is determined. Next, by the squaring circuit 15,
The square of the digital value signal is calculated. The value obtained by the squaring circuit 15 is sequentially cumulatively added to the register 17. The value stored in the register 17 is cleared by an external vertical synchronizing signal. The value stored in the register 17 immediately before the clear is cleared is stored in the register 18. With these circuits, the value obtained by calculating the square of the difference between adjacent video signals is calculated and accumulated over the entire screen. Then, the value can be read out by the system microcomputer 8. Regarding the operation of the phase detection arithmetic circuit 10, first, there is a division ratio, that is, the number of clocks in the 1H period of the video signal coincides with the division ratio N of the 1 / N divider circuit of the video device. Explanation will be given in the state. FIG. 3 shows the relationship between the video signal in the A / D converter 1 and the phase of the sampling clock. As shown in the figure, a video signal transmitted in an analog form always has a slope at the rise or fall of the signal, and it is almost certain that data changes depending on the sampling location. . When the value of the digitized video signal is squared by taking the difference in the phase detection arithmetic circuit 10 and added,
Compared to the value (130050) at the phase (phase 1) at which the original value is sampled, the value (85) at the phase (phase 2) at which the video signal changes at the changing point is sampled.
025) takes a small value. From this, the relationship between the clock phase and the value calculated by the phase detection calculation circuit 10 is expected to draw a curve as shown in FIG. Where there is a phase, the contrast becomes highest and has a peak. Conversely, the contrast of the image is highest where there is a peak, that is, if the calculation is performed on the same video signal, the peak is found to be the best in phase. The shape of this curve differs depending on the video signal, and it is expected that the absolute value of the curve will take various values. However, only the peak and the relative value are problematic. There is no meaning. Next, consider the change in the calculated value with respect to the frequency division ratio. If the frequency division ratio is present, the change with respect to the phase is as described above. If the frequency division ratio is not present, the phase and the phase in the horizontal direction match. Missing parts appear periodically. The larger the difference between the frequency division ratios, the greater the frequency shift, so that the period in which the phase is out of phase tends to increase. Where there is no phase, the calculated value in the phase detection calculation circuit 10 is reduced as described above, so that the calculated value as a whole tends to be reduced. Here, if the range of the image is infinite, there is no change with respect to the phase change by the delay circuit 4 in FIG. 1, but of course, since the screen is actually finite on the left and right, the phase circuit Therefore, when the phase of the clock is shifted, the image is cut off at the left and right edges, so that there are variations when there are many areas where the phases match, and when there are few areas. The result is as shown in the graph of FIG. This is also understood from the fact that the larger the difference between the division ratios, the larger the period in which there is no phase, and the smaller the dispersion tends to be. (FIG. 6) From these facts, it can be seen that a graph in which the frequency division ratio and the phase are plotted on the X and Y axes and the calculated value is plotted on the Z axis is as shown in FIG. That is, the peak point A may be found. Although various search methods are conceivable, the details are omitted here because they are not essential problems. As the simplest method, the range defined as the range in which the frequency division ratio can be adjusted, the phase is changed as much as necessary, and all the values corresponding thereto are taken in as data, and the maximum value is taken. If the frequency division ratio and the delay amount of the phase are obtained, it can be said that this is the place where the frequency division ratio and the phase match this video signal. In the configuration described so far, it takes at least one screen time to capture one value, so it is easily assumed that this takes too much time. Some improvements in the algorithm, such as replacing a part with a circuit or performing thinning out measurement to predict and narrow down, are considered. In order to reduce the time, it is possible to take in only a part of the area. However, it is a problem as an implementation method. The dividing ratio N of the 1 / N dividing circuit and the delay amount of the horizontal synchronizing signal delay circuit are automatically set to the best values by the phase detection calculating circuit of the video signal processing apparatus according to the present invention. Can be set, so that complicated adjustment for improving the screen display conventionally entrusted to the user's hand can be omitted.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an overall block diagram according to an embodiment of the present invention. FIG. 2 is a block diagram of a phase detection operation circuit according to the embodiment of the present invention. FIG. 3 is a first diagram illustrating a relationship between a sampling phase of a video signal and a calculation result of a phase detection calculation circuit. FIG. 4 is a second diagram illustrating a relationship between a sampling phase of a video signal and a calculation result of a phase detection calculation circuit. FIG. 5 is a diagram illustrating a relationship between a frequency division ratio of a video signal and a calculation result of a phase detection calculation circuit. FIG. 6 is a diagram illustrating a relationship between a phase delay amount, a dividing ratio, and a calculation result of a phase detection calculation circuit. FIG. 7 is a diagram showing the relationship between the operation value of the phase detection operation circuit and the amount of phase delay when the frequency division ratio is changed. FIG. 8 is an overall block diagram in a conventional example. FIG. 9 is a block diagram of a horizontal synchronization signal delay circuit. FIG. 10 is a diagram illustrating a phase relationship between a video signal and a sampling clock. [Description of Signs] 1 A / D converter 2 Video signal processing circuit 3 Video display device 4 Delay circuit 5 Phase comparator 6 VCO 7 1 / N frequency dividing circuit 8 System microcomputer 9 Clock generation circuit 10 Phase detection calculation circuit 11 Delay Element 12 Multiplexer 13 One-pixel delay circuit 14 Difference circuit 15 Square circuit 16 Addition circuit 17 Register 18 Register

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H04N 5/66 H04N 5/66 B (56) References JP-A-10-133619 (JP, A) JP-A-7-160222 ( JP, A) (58) Fields surveyed (Int. Cl. ⁷ , DB name) G09G 3/20 623 G09G 3/20 612 G09G 3/36 G09G 5/18 H04N 5/06 H04N 5/66

Claims (1)

(57) [Claim 1] In a video signal processing apparatus for digitally processing and displaying a video signal, a square of an absolute value of a difference between signal levels of adjacent picture elements is calculated, and An arithmetic circuit for summing the calculated values for one screen, a delay circuit for delaying a horizontal synchronizing signal separated from a video signal, and a clock generating circuit having a frequency dividing circuit; The delay amount of the delay circuit
And by controlling the frequency division number of the frequency divider of the clock generator circuit, a video signal processing apparatus characterized by adjusting the sampling phase and frequency division ratio may video signal adequately sample.