JP2010171907A - Device and method for separating synchronization signal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that, since a synchronization separation threshold is calculated using a pedestal level in a conventional synchronization separation circuit, synchronization separation cannot be stably carried out when an input signal of an NTSC signal or the like is varied. <P>SOLUTION: This device for separating a synchronization signal separates a synchronization signal of a video input signal, and includes: a synchronization signal chip level calculation means to calculate a synchronization signal chip level of the input signal; a threshold calculation means to calculate a synchronization separation threshold by adding a correction value to the synchronization signal chip level; a comparison means to compare the input signal with the synchronization separation threshold; and a synchronization signal generation mans to generate a synchronization signal based on the comparison result of the comparison means. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a synchronization signal separation device and a synchronization signal separation method for video signals, and more particularly to a synchronization signal separation device and a synchronization signal separation method that can stably separate a synchronization signal from an input signal with noise.

  In general, a video signal is composed of a synchronization signal and an input signal representing video information, and it is necessary to separate the synchronization signal from the input signal. A method for separating a synchronization signal from an input signal is disclosed in Patent Document 1, for example. A synchronization signal separation device disclosed in Patent Document 1 is shown in FIG. A conventional synchronization signal separation device includes a clamp control unit 111 that reproduces a direct current component of an input video signal, an analog / digital (A / D) converter 107 that converts an output video signal of the clamp control unit 111 into a digital video signal, and the like. , A digital low-pass filter 109 for removing color signal components and noise components from the digital video signal from the A / D converter 107, and a synchronization signal from the digital data of the synchronization signal portion and the pedestal signal portion in the digital video signal from the digital low-pass filter. An arithmetic unit 115 that calculates a threshold value that is reference data for separation, a digital / analog (D / A) converter 137 that converts the threshold value from the arithmetic unit into an analog voltage, and an analog threshold value from the D / A converter 137 And an analog signal obtained by removing color signal components and noise components from the input signal to the A / D converter 107. And it includes an analog comparator 139 for outputting a synchronous signal by comparing the image signal. As described above, in the conventional synchronization signal separation device, when calculating a threshold value (synchronization separation threshold value) that is reference data for synchronization signal separation used for separating the synchronization signal from the input signal, the digital data ( Pedestal level).

  A method for obtaining the synchronization separation threshold from the pedestal level will be described with reference to FIG. First, the sync separation process and the pedestal level that is the reference for the brightness of the output video are calculated. First, the pedestal sample value (for example, the average value of four points) is obtained for each line in units of the horizontal sync signal (HSYNC). Specifically, as shown in FIG. 2, the pedestal sample value is obtained in the region of several clocks from the rising edge of the input signal. The obtained pedestal sample value for each line is input to an infinite impulse response (IIR) filter means shown in FIG. 3 to calculate an averaged pedestal level for a plurality of lines. As shown in FIG. 3, the IIR filter means includes arithmetic means 201 and 204, an adder 202, and a latch 203, and an example in the case of a filter coefficient 1/256 is shown here. Next, a synchronization separation threshold value for performing synchronization separation processing is calculated using the obtained pedestal level. For example, in FIG. 2, the sync separation process is performed using a value between the pedestal level and the sync signal chip level that is the minimum value of the signal level as a threshold value.

JP 2001-69370 (FIG. 1, [0009] paragraph)

  As described above, the method of using the pedestal level when calculating the synchronization separation threshold has the following problems. First, since the average value of the accumulated values of the pedestal sample values is used as the synchronization separation threshold, a position shift of synchronization separation occurs when an input signal such as an NTSC signal fluctuates (so-called V sag). Secondly, since two points of the synchronization signal chip level and the pedestal level, both of which cause noise, are used as the synchronization separation threshold, they are susceptible to noise. Thirdly, when Macrovision (registered trademark) video is used as an input source, the pedestal level is different between the clamp level and the video portion, so that the pedestal level fluctuates and there is a possibility that synchronization and separation cannot be performed correctly. Therefore, the present invention provides a synchronization signal separation device and synchronization that can stably separate a synchronization signal even when a Macrovision (registered trademark) video signal is used as an input source or when the input signal fluctuates. An object is to provide a signal separation method.

  The synchronization signal separation device of the present invention is a synchronization signal separation device for a video input signal, a synchronization signal chip level calculation means for calculating a synchronization signal chip level of an input signal, and a correction value is added to the synchronization signal chip level. Threshold calculation means for calculating a synchronization separation threshold, comparison means for comparing the input signal and the synchronization separation threshold, and synchronization signal generation means for generating a synchronization signal based on the comparison result of the comparison means It is characterized by.

  The synchronization signal separation method of the present invention is a synchronization signal separation method of a video input signal, the step of calculating a synchronization signal chip level of the input signal, and a synchronization separation threshold value is calculated by adding a correction value to the synchronization signal chip level. And a step of comparing the input signal with the synchronization separation threshold value, and generating a synchronization signal based on the comparison result.

  According to the synchronization signal separation device and the synchronization signal separation method of the present invention, since the pedestal level is not used when calculating the synchronization separation threshold, the synchronization signal can be stably separated from the input signal on which the noise is placed. The effect is obtained.

It is a block diagram which shows the structure of the conventional synchronous signal separation apparatus. It is a figure which shows the relationship between the input signal and isolation | separation signal in a prior art. It is a block diagram of the IIR filter means by a prior art. It is a block diagram of the synchronous signal separation apparatus of Example 1 of this invention. It is a figure which shows the relationship between the input signal in this invention, and a synchronous separation signal. It is a flowchart of the synchronous signal separation method of Example 1 of this invention. It is a block diagram of the synchronous signal separation apparatus of Example 2 of this invention. It is a figure which shows the relationship between the HSYNC period and synchronizing signal period in each line of Example 2 of this invention. It is a flowchart of the synchronous signal separation method of Example 2 of this invention.

  Hereinafter, a synchronization signal separation device and a synchronization signal separation method according to the present invention will be described with reference to the drawings. However, it should be noted that the technical scope of the present invention is not limited to these embodiments, but extends to the invention described in the claims and equivalents thereof.

  FIG. 4 shows a configuration diagram of a synchronization signal separation device according to Embodiment 1 of the present invention. The synchronization signal separating apparatus 100 according to the first embodiment includes a clamp unit 1 that performs adjustment (clamp processing) of a synchronization signal chip level of an input signal, and an A / D conversion unit 2 that performs A / D conversion on an output signal from the clamp unit 1. Have Furthermore, the synchronization signal separation device 100 includes a digital low-pass filter 4 that removes noise from the output signal of the A / D conversion means 2. The output of the digital low-pass filter 4 is input to the synchronization signal chip level calculation means 3 in the synchronization signal separation device 100, and the synchronization signal chip level is obtained from the minimum value of the input signal based on an instruction from the control means 5.

  The synchronization signal separating apparatus 100 is provided with a correction value adjusting means 8 and outputs a correction value adjusted as described later. As an initial value, for example, as shown in FIG. An average value of the level and the input signal level at the immediately preceding front porch can be output. The synchronization signal chip level and the correction value are input to the threshold value calculation means 7, and a threshold value (synchronization separation threshold value) for separating the synchronization signal from the input signal is output based on an instruction from the control means 5. The synchronization separation threshold value and the input signal are input to the comparison means 9, and the synchronization separation threshold value and the input signal are compared. The comparison result of the comparison unit 9 is output to the synchronization signal generation unit 10, and the synchronization signal is separated from the input signal based on an instruction from the control unit 5.

The generated synchronization signal is input to the synchronization signal period measuring means 11. In the synchronization signal period measuring means 11, the length of the period of the synchronization signal is measured. The measurement result of the length of the period of the synchronization signal is output to the correction value adjusting unit 8 to adjust the correction value. The measurement method and adjustment method will be described with reference to FIG. FIG. 5 shows temporal changes in the levels of the input signal and the sync separation signal, and the sync separation signal separated from the input signal is shown below the input signal. The sync separation signal can be obtained by comparing the level of the input signal with the size of the sync separation threshold level. Here, when the synchronization separation threshold level is “minimum value + correction value” ((i) in FIG. 4), the length of the period of the synchronization signal, that is, the length of the period equal to or less than the synchronization separation threshold level of the input signal Let L be L. When L is equal to the desired length L ₀ , it is not necessary to adjust the correction value, the period of the synchronization signal is kept constant, and synchronization separation is performed stably. Here, the value of L ₀ is stored in the memory 6 in the control means 5 and passed to the synchronization signal period measurement means 11.

On the other hand, when L <L ₀ , it is necessary to lengthen L, and therefore it is necessary to increase the absolute value of the synchronization separation threshold level. That is, an appropriate value X is added to the correction value, the synchronization separation threshold level is set to “minimum value + correction value + X” ((ii) in FIG. 4), and L = L ₀ is adjusted.

In addition, when L> L ₀ , L needs to be shortened, so the absolute value of the synchronization separation threshold level needs to be reduced. That is, the appropriate value X is subtracted from the correction value, and the synchronization separation threshold level is set to “minimum value + correction value−X” ((iii) in FIG. 4), and is adjusted so that L = L ₀ . However, the difference ΔL between L and L ₀ may be within an allowable range instead of being strictly matched. That is, the adjustment may be performed so that the period L of the synchronization signal is in a predetermined range: L ₀ −ΔL ≦ L ≦ L ₀ + ΔL.

  The generated synchronization signal is input to the YC separation / RGB decoder 12 together with the input signal, and the input signal is synchronized. The output of the YC separation / RGB decoder 12 is input to the capture 13 and then output to the display device 14 to display an image.

  Thus, in the present invention, since the pedestal level is not used in the calculation of the synchronization separation threshold for separating the synchronization signal, the synchronization signal is stably generated even when the pedestal level fluctuates. In addition, since the period of the synchronization signal can be set to a fixed length by adjusting the correction value, a stable synchronization signal can be obtained.

  Next, the synchronization signal separation method according to the first embodiment of the present invention will be described with reference to the block diagram of FIG. 4 and the flowchart of FIG. First, in step S101, the clamp means of the synchronization signal separation device 100 performs synchronization signal chip level adjustment (clamp processing) of the input signal. Next, in step S102, the clamped output signal is input to the A / D conversion means 2 and converted into a digital signal. Next, in step S103, the digital signal is input to the digital low-pass filter 4 to remove noise. In step S104, the signal from which the noise has been removed is input to the synchronization signal chip level calculation unit 3, and the synchronization signal chip level is calculated based on an instruction from the control unit 5 in the synchronization signal separation device 100. The synchronization signal chip level is obtained from the minimum value of the input signal as shown in FIG.

  Next, in step S105, the initial value of the correction value stored in the memory 6 in the control means 5 is passed to the threshold value calculation means 7 to set the synchronization separation threshold level. Specifically, the correction value is added to the synchronization signal chip level (minimum value). Next, in step S106, the input signal and the synchronization separation threshold level are input to the comparison means 9, and the two are compared.

  Next, in step S107, the comparison result is input to the synchronization signal generation means 10, and the synchronization signal generation means 10 generates a synchronization signal as shown in FIG. 5 based on the comparison result of both. Next, the generated synchronization signal is input to the synchronization signal period measuring unit 11, and in step 108, the synchronization signal period measuring unit 11 measures the period of the synchronization signal. Specifically, as described above with reference to FIG. 5, the length L of the input signal equal to or less than the synchronization separation threshold level is measured. Although the measurement of this period may directly measure time, the number of clock pulses may be measured.

  Here, when the target number of clock pulses is 127 clocks (clk), in step 109, the synchronization signal period measuring means 11 determines whether or not the synchronization signal period L is 127 [clk]. Here, 127 [clk] is the number of clocks with a sampling frequency of 27 MHz corresponding to 4.7 μsec, which is the standard of the horizontal synchronization signal period (tip) of the NTSC signal. When L = 127 [clk], since it is not necessary to adjust L, it is not necessary to adjust the synchronization separation threshold level, and the signal processing after step S114 proceeds.

  If L is not 127 [clk], the synchronization signal period measuring means 11 determines the magnitude relationship between L and 127 [clk] in step S110. When L is smaller than 127 [clk], it is necessary to lengthen L, so the synchronization separation threshold level is increased as shown in FIG. In step S111, the synchronization signal period measuring unit 11 determines a value X such that L = 127 [clk], and outputs the result to the correction value adjusting unit 8. On the other hand, when L is larger than 127 [clk], it is necessary to shorten L, so the synchronization separation threshold level is decreased as shown in FIG. In step S112, the synchronization signal period measuring unit 11 determines a value X such that L = 127 [clk], and outputs the result to the correction value adjusting unit 8.

  Next, in step S113, the correction value adjustment unit 8 adjusts the magnitude of the correction value based on the adjustment value X from the synchronization signal period measurement unit 11. The magnitude of the correction value is sent to the threshold calculation means 7, and the synchronization separation threshold is calculated. Specifically, the synchronization separation threshold level is calculated by adding or subtracting X to the sum of the minimum value (synchronization signal chip level) and the correction value to obtain L = 127 [clk]. .

  Next, returning to step S106, the synchronization separation threshold level adjusted by the comparison means 9 is compared with the input signal, and a synchronization signal is generated in step S107. Since the subsequent processing is the same as described above, the description thereof is omitted. Steps S106 to S113 are repeated until the synchronization signal period L reaches a predetermined length (here, 127 [clk]).

  If L = 127 [clk] in step S109, in step S114, the control unit 5 instructs the synchronization signal period measurement unit 11 to pass the synchronization signal to the YC separation / RGB decoder 12. The YC separation / RGB decoder 12 separates the input signal into a luminance signal (Y) and a color signal (C) to generate an RGB signal. Next, in step S115, the RGB signal is input to the capture 13 and subjected to the capture process, and then input to the display device 14 in step S116 to display an image.

  Next, a synchronization signal separation method according to Embodiment 2 of the present invention will be described. The synchronization signal separation method according to the second embodiment has a feature that the synchronization signal period is variable in accordance with the HSYNC period when the length of the horizontal synchronization signal (HSYNC) changes for each line, such as a deteriorated video tape. It is a feature.

  FIG. 7 is a block diagram illustrating the configuration of the synchronization signal separation device according to the second embodiment. The difference from the synchronization signal separating apparatus according to the first embodiment is that an HSYNC period measuring unit 15 is provided. The HSYNC period measured by the HSYNC period measuring means 15 is sent to the synchronization signal period measuring means 11, and the correction value is adjusted with reference to the synchronization signal period corresponding to the HSYNC period.

  FIG. 8 shows an HSYNC period and a synchronization signal period for a plurality of lines as an example. Table 1 summarizes the HSYNC period and the synchronization signal period in each line.

FIG. 9 shows a flowchart of the synchronization signal separation method according to the second embodiment. The difference from the synchronization signal separation method according to the first embodiment is that the noise is removed in step S103 and then the HSYNC period is measured in step S1031. Measurement results of the HSYNC period is utilized in determining the length L ₀ of the period of the synchronization signal to the target in step S108. For example, when the HSYNC period is 1725 [clk] as in the above example, L ₀ = 128 [clk] is set, and when the HSYNC period is less than 1725 [clk], L ₀ = 127 [clk] is set. Set. Thereafter, in steps S109 to S113, L and L ₀ are compared in the same manner as in the first embodiment.

  As described above, when the length of the HSYNC period is 1725 [clk] (lines 3 and 4), the correction value is adjusted so that the synchronization signal is 128 [clk]. Adjust the correction value so that becomes 127 [clk]. As described above, in the synchronization signal separation method according to the second embodiment, not only the length of the input signal below the threshold is measured to adjust the length of the synchronization signal, but also the length of the line itself is measured to obtain the reference. The synchronizing signal period is also adjusted. As described above, by changing the number of clock pulses of the synchronization signal according to the HSYNC period, it is possible to minimize image disturbance even when the video tape is deteriorated.

  In the above embodiment, the case of the NTSC signal has been described as an example, but the present invention can be similarly implemented even in the case of other systems such as PAL and SECAM.

DESCRIPTION OF SYMBOLS 1 Clamp means 2 A / D conversion means 3 Synchronization signal chip level calculation means 4 Digital low-pass filter 5 Control means 6 Memory 7 Threshold value calculation means 8 Correction value adjustment means 9 Comparison means 10 Synchronization signal generation means 11 Synchronization signal period measurement means 12 YC Separation / RGB decoder 13 Capture 14 Display device 15 HSYNC period measurement means 100 Sync signal separation device

Claims (4)

A synchronization signal separation device for video input signals,
Synchronization signal chip level calculation means for calculating the synchronization signal chip level of the input signal;
Threshold calculation means for calculating a synchronization separation threshold by adding a correction value to the synchronization signal chip level;
A comparison means for comparing the input signal with the synchronization separation threshold;
Synchronization signal generation means for generating a synchronization signal based on the comparison result of the comparison means;
A synchronization signal separation device comprising: Synchronization signal period measuring means for measuring the period of the synchronization signal;
A correction value adjusting means for adjusting the correction value when the period of the synchronization signal is not within a predetermined range;
The synchronization signal separation device according to claim 1, further comprising: A method for synchronizing video input signals, comprising:
Calculating a synchronization signal chip level of the input signal;
Calculating a synchronization separation threshold by adding a correction value to the synchronization signal chip level;
Comparing the input signal with the sync separation threshold;
Generating a synchronization signal based on the comparison result;
A synchronization signal separation method comprising: Measuring a period of the synchronization signal;
If the period of the synchronization signal is not within a predetermined range, adjusting the correction value;
The synchronization signal separation method according to claim 3, further comprising:

Images