KR100866571B1 - Apparatus and method for correcting a synchronous signal - Google Patents

Abstract

The present invention relates to an apparatus and a method for compensating a sync signal. In particular, when a sync signal is missed by latching a minimum / maximum width of a vertical / horizontal sync signal, the sync signal is referred to by referring to a latch value for a previously stored sync signal width. The purpose is to restore the. The present invention for this purpose is a video / synchronous separator 210 for receiving an analog video signal and separating the horizontal / vertical synchronization signal and the image signal, and the missing of the horizontal or vertical synchronization signal separated from the video / synchronous separator 210 Is detected, the horizontal / vertical sync controller 250/260 corrects the horizontal or vertical sync signal, and the horizontal / vertical sync controller 250/260 outputs the analog image signal separated by the video / sync separator 210. An analog / digital converter 220 for converting the digital image data based on a horizontal / vertical synchronization signal (HsyncOut / VsyncOut) output from the digital image data, and the horizontal / vertical image data converted by the analog / digital converter 220. An image processor 23 that adjusts the resolution to a display device (not shown) based on the horizontal / vertical synchronization signal output from the synchronization controller 250/260. 0) and a video controller 240 for converting digital image data from the image processor 230 into an analog image signal to display an image on a display device (not shown).

Description

Synchronization signal correction apparatus and method {APPARATUS AND METHOD FOR CORRECTING A SYNCHRONOUS SIGNAL}

1 is a block diagram of a conventional video signal processing apparatus.

2 is a block diagram of a synchronization signal correction apparatus for an embodiment of the present invention.

3 is a block diagram of a horizontal synchronization controller in FIG.

4 is a block diagram of a vertical synchronization controller in FIG.

FIG. 5 is a horizontal synchronous signal waveform diagram of FIG. 2; FIG.

6 is a vertical synchronous signal waveform diagram in FIG.

7 is an operation flowchart for horizontal synchronization correction in an embodiment of the present invention.

8 is an operation flowchart for vertical synchronization correction in an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

210: video / sync separator 220: analog / digital (A / D) converter

230: image processor 240: video controller

250: horizontal synchronous controller 260: vertical synchronous controller

The present invention relates to digital TVs, and more particularly, to an apparatus and method for correcting vertical / horizontal synchronization signals.

In general, a digital TV receives a video signal from an external device (DVD, VCR, STV, etc.) to display an image on a display device.

To this end, the digital TV consists of a video / synchronous separator 110, an analog / digital (A / D) converter 120, an image processor 130, and a video controller 140, as shown in the block diagram of FIG. do.

The operation process of the general digital TV is as follows.

When an analog video (composite or component) in which a sync signal (Hsync, Vsync) and a picture signal are mixed is input from an external device such as a DVD, a VCR, or a STV, the video / sync separator 110 generates a horizontal / vertical sync signal (Hsync / Vsync). ) And the image signal.

The analog-to-digital (A / D) converter 120 converts an image signal into digital data in synchronization with a horizontal / vertical synchronization signal (Hsync / Vsync) and inputs the image signal to the image processor 130.

The image processor 130 may display image data digitally converted by the analog / digital converter 120 based on the horizontal / vertical sync signal Hsync / Vsync in the video / sync separator 110 of the display device (not shown). Convert to fit the resolution and input to the video controller (140).

The video controller 140 converts the digital image data whose resolution is adjusted to the display device (not shown) by the image processor 130 into an analog video signal to display an image on the display device (not shown).

However, in the related art, when the synchronization signal is not properly separated due to a problem such as the quality state of an analog video signal input from an external device, and the horizontal / vertical synchronization signal is missing, there is a problem that affects the image quality displayed on the display device.

For example, when the vertical synchronization signal is missing, a pause or vertical flow of the entire screen appears. When the horizontal synchronization signal is missing, horizontal screen distortion and splashing appear.

That is, conventionally, when a vertical / horizontal synchronization signal of an externally input video signal is missing, a problem arises in that image quality is impaired.

Accordingly, the present invention recovers the synchronization signal by referring to the latch value for the previously stored synchronization signal width when the synchronization signal is missing by latching the minimum / maximum width of the vertical / horizontal synchronization signal to solve the conventional problem. It is an object of the present invention to provide an apparatus and method for compensating for synchronizing signal, which is invented to make it possible.

The present invention provides a digital TV that receives a video signal from an external device and displays an image on a display device in order to achieve the above object. When the detection of the missing sync signal is detected in the video / sync separator, the sync signal is corrected. And a synchronization controller for outputting to an analog / digital converter and an image processor.

The sync controller includes a counter unit for counting the width of the sync signal, a latch unit for storing the sync signal width counted by the counter unit, and a comparator for comparing whether the value counted by the counter unit is greater than the value stored in the latch unit. And a synchronizing generator and a synchronizing switch to correct the synchronizing signal by the width of the synchronizing signal stored in the latch unit when the comparator determines that the latch value is larger than the current count value.

The present invention also provides a synchronization signal providing method of a digital TV in order to achieve the above object, the step of separating the synchronization signal from the external video signal, and counting and storing the maximum / minimum width of the separated synchronization signal; Comparing the count value of the current sync signal with the count value of the previous sync signal; and if it is determined that the stored count value is greater than the current count value, the sync signal is low by the row width of the stored sync signal. And repeating the outputting step so as to correct the synchronization signal.

Hereinafter, the present invention will be described in detail with reference to the drawings.

2 is a block diagram of an apparatus for an embodiment of the present invention, as shown therein, a video / sync separator 210 for receiving an analog video signal and separating a horizontal / vertical sync signal (Hsync / Vsync) and an image signal. And a horizontal / vertical sync controller 250 that corrects the horizontal or vertical sync signal Hsync or Vsync when detecting the omission of the horizontal or vertical sync signal Hsync or Vsync separated from the video / sync separator 210. 260 and the analog image signal separated by the video / sync separator 210 as digital image data based on the horizontal / vertical synchronization signal (HsyncOut / VsyncOut) output from the horizontal / vertical synchronization controller 250/260. A horizontal / vertical synchronization signal output from the horizontal / vertical synchronization controller 250/260 to convert the analog / digital converter 220 to be converted and the digital image data converted by the analog / digital converter 220. An image processor 230 that adjusts the resolution to a display device (not shown) based on a call, and converts the digital image data from the image processor 230 into an analog image signal and displays an image on the display device (not shown). It is configured to include a video controller 240 to display.

As shown in the block diagram of FIG. 3, the horizontal sync controller 250 counts the high / low widths of the horizontal sync signals Hsync separated from the video / sync separator 210 based on the clock HCLK2. Storing the high / low widths of the first and second horizontal counters 310 and 320 and the horizontal sync signal Hsync currently counted by the first and second horizontal counters 310 and 320, respectively. The first and second latches 330 and 340 and the count value of the first horizontal counter 310 and the stored value of the first latch 330 are compared to determine that the count value is greater than the stored value. A horizontal synchronous generator 360 for outputting a horizontal synchronous signal low by a width corresponding to a stored value of the second latch 340 when the comparator 350 and the comparator 350 output a high signal; When the output value of the comparator 350 is low, the horizontal sync signal Hsync separated by the video / sync separator 210 is selected and the If the output of ryeokgap Gyoki 350 is high and consists of a synchronization switch 370 for selecting and outputting a low output of the horizontal sync generator 360.

As shown in the block diagram of FIG. 4, the vertical sync controller 260 counts the high / low widths of the vertical sync signals Vsync separated from the video / sync separator 210 based on the clock VCLK2. Storing the high / low widths of the first and second vertical counters 410 and 420 and the vertical sync signal Vsync currently counted by the first and second vertical counters 410 and 420, respectively. Comparing the count value of the third and fourth latches 430 and 440 with the count value of the first vertical counter 410 and the stored value of the third latch 430 to output a high signal when the count value is greater than the stored value. When the output value of the comparator 450 and the comparator 450 is high, the vertical sync generator 460 outputs a vertical sync signal low by a width corresponding to the stored value of the fourth latch 440, and the comparator ( When the output value of 450 is low, the vertical sync signal Vsync separated from the video / sync separator 210 is selected and the comparator 450 of the comparator 450 is selected. If the high ryeokgap constitute a synchronization switch 470 for selecting and outputting a low output of the vertical synchronization generator (460).

Referring to the operation and effect of the embodiment of the present invention configured as described above are as follows.

According to an embodiment of the present invention, the video / sync separator 210, the analog / digital converter 220, the image processor 230, and the video controller 240 perform the same operation as the prior art to input a video signal from an external device. When the image is displayed on the display device (not shown), the horizontal / vertical synchronization controllers 250 and 260 compensate for the loss of the horizontal / vertical synchronization signal.

Hereinafter, the horizontal sync signal Hsync and the vertical sync signal Vsync will be described separately in order to explain the obvious operation of the present invention.

First, a process of correcting a horizontal sync signal (Hsync) in the horizontal sync controller 250 will be described with reference to the signal waveform diagram of FIG. 5 and the operation flowchart of FIG. 7.

The count values of the first and second horizontal counters 310 and 320 that count the width of the horizontal sync input HsyncIn are cleared to '0'.

In addition, the output of the comparator 350 is set to be low to disable the horizontal synchronization generator 360, and the synchronization switch 370 is configured to select the horizontal synchronization input HsyncIn as the horizontal synchronization output HsyncOut. (S701)

Subsequently, when the horizontal synchronization signal HsyncIn is input high, the first horizontal counter 310 increases the count value every clock HCLK2 and the current status is set high and, conversely, the horizontal synchronization signal HsyncIn ) Is input low, the second horizontal counter 320 increases the count value every clock HCLK2, and the current state is set low (S702 to S704).

In this case, when the current state is changed, that is, when the horizontal synchronization signal HsyncIn is changed from low to high or from high to low, as shown in FIG. 5A, the first and second latches 330 and 340 are changed. Latches and stores the current count value (S706-S708).

That is, when the horizontal synchronization signal HsyncIn is changed from low to high, the second latch 340 latches and stores the count value up to the present of the second horizontal counter 320 (S707). When HsyncIn is changed from high to low, the first latch 330 latches and stores the count value up to the present of the first horizontal counter 310 (S708).

If there is no change of the current state, it is checked whether the current state of the horizontal synchronization signal HsyncIn is high, and if it is a high period, the comparator 35 checks the count value of the first horizontal counter 310 and the first latch 330. Compare the stored values. (S709, S710)

At this time, if the count value of the first horizontal counter 310 is larger than the stored value of the first latch 330, the comparator 350 determines that a loss occurs in a low section of the horizontal sync input HsyncIn, and FIG. As shown in (b), the high signal is output to the horizontal sync generator 360 and the sync switch 370. (S711 to S713).

That is, the comparator 350 compares the count value of the first horizontal counter 310 and the stored value of the first latch 330 at the rising edge of the horizontal clock HCLK1 as shown in FIG. 5E. When the count value of the first horizontal counter 310 is greater than the stored value of the first latch 330, the high signal is output at the falling edge of the horizontal clock HCLK1.

However, when comparing the count value of the first horizontal counter 310 and the stored value of the first latch 330, the first horizontal counter 310 is actually considered in consideration of the occurrence of delay depending on the input state of the horizontal synchronization signal HsyncIn. ) And the output of the comparator 350 becomes high under the condition that the count value of is greater than the sum of the stored value of the first latch 330 and the arbitrary value C.

Here, the arbitrary value C is set large in the range which does not affect an image even when the horizontal synchronizing signal Hsyn is correct | amended.

At this time, the horizontal synchronization generator 360 checks whether the output of the comparator 350 is high at the rising edge of the horizontal clock HCLK1, and if the output of the comparator 350 is high, as shown in FIG. The horizontal synchronization signal is output as low as the count value stored in the two latches 340 to be input to the synchronization switch 370.

Accordingly, since the output of the comparator 350 is high, the synchronous switch 370 selects the output of the horizontal synchronous generator 360 and outputs the output to the horizontal synchronous output terminal HsyncOut. As shown in), the output is corrected to a normal state.

Therefore, the horizontal synchronization signal Hsync whose loss in the row period is corrected is input to the analog / digital converter 220 and the image processor 230.

The above operation is repeatedly performed in synchronization with the horizontal clock HCLK1 while a video signal is input from an external device.

In addition, the vertical sync signal Vsync correction operation in the vertical sync controller 260 is performed in the same manner as the horizontal sync signal Hsync correction operation, which is illustrated in the signal waveform diagram of FIG. 6 and the operation flowchart of FIG. 8. As shown.

However, since the width of the vertical sync signal Vsync is greater than the width of the horizontal sync signal Hsync, the sizes of the first and second vertical counters 410 and 420 and the third and fourth latches 430 and 440 are different. To reduce the frequency, the frequency of the vertical clock VCLK2 used to count the width of the vertical synchronization signal is set to a lower frequency than that of the horizontal synchronization.

Since the vertical clock VCLK1 is only related to a delay from the output of the comparison result of the comparator 450 to the output of the vertical sync signal VsyncOut, the vertical clock VCLK1 is used to correct the horizontal sync signal Hsync or the vertical sync signal Vsync. In both cases, increasing the frequency can reduce the delay.

As described in detail above, the present invention corrects the loss of the vertical / horizontal synchronization due to the quality state of the analog video signal input from an external device, thereby temporarily stopping the entire screen that may appear during the vertical and horizontal synchronization loss. It has the effect of providing clear image quality by preventing freeze or vertical flow, horizontal screen distortion, and screen glitch.

Claims (10)

In the digital TV having a video / synchronous separator, an analog / digital converter, an image processor and a video controller to receive a video signal from an external device and display the image on the display device, And a sync controller for correcting the sync signal and outputting the missing sync signal to the analog / digital converter and the image processor. The sync controller, A counter unit for counting the width of the synchronization signal; A latch unit for storing the synchronization signal width counted by the counter unit; A comparator for comparing the stored value of the latch portion with the current count value in the counter portion; And And a synchronization correction unit for correcting a current synchronization signal by the width of the synchronization signal stored in the latch unit when it is determined that the latch value is larger than the count value as a result of the comparison of the comparator. delete The method of claim 1, wherein the counter unit, And a width of the synchronization signal is counted each time the level of the synchronization signal is changed. The method of claim 1, wherein the latch unit, And a count value up to the present of the counter unit when the level of the synchronization signal is changed. The method of claim 1, wherein the synchronization correction unit, A synchronization generator for generating a synchronization signal having a width corresponding to the latch value stored in the latch unit when the comparator determines that the current count value of the counter unit is greater than a previous count value stored in the latch unit; And selecting and outputting the sync signal separated by the video / sync separator, and selecting and outputting the sync signal generated by the sync generator when the comparator determines that the current count value is larger than the previous count value. Sync signal correction device. In the digital TV having a video / synchronous separator, an analog / digital converter, an image processor and a video controller to receive a video signal from an external device and display the image on the display device, And a sync controller for correcting the sync signal and outputting the missing sync signal to the analog / digital converter and the image processor. The sync controller, First and second counters each counting a high / low width of a sync signal separated by the video / sync separator; First and second latches respectively storing the high / low widths of the synchronization signal sync currently counted by the first and second counters; A comparator for comparing a count value of the first counter with a stored value of the first latch and outputting a high signal if it is determined that the count value is greater than the stored value; A synchronization generator configured to output a synchronization signal low by a width corresponding to a stored value of the second latch when the comparator outputs a high signal; And a synchronous switch selecting a synchronous signal separated by the video / sync separator when the output value of the comparator is low, and selecting and outputting a low output of the synchronous generator when the output value of the comparator is high. Sync signal correction device. The method of claim 1, wherein the synchronization controller, And a horizontal synchronization controller and a vertical synchronization controller, respectively, for the horizontal / vertical synchronization signal. The method of claim 7, wherein the vertical synchronization controller, And a clock having a lower frequency than that used by the horizontal synchronization controller for counting the width of the sync signal. A first step of separating a synchronization signal from an external video signal; Counting the width of the separated synchronization signal; A third step of storing a count value up to the present when the level of the synchronization signal is changed; A fourth step of comparing the count value of the stored previous sync signal with the count value of the current sync signal; If it is determined that the stored count value is greater than the current count value, the synchronization signal correction is repeated by repeating the fifth step of outputting the sync signal low by the width of the stored sync signal. Way. The method of claim 9, wherein the third step, And performing a comparison operation when the state of the current synchronization signal is high.

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