KR100277993B1 - Synchronization signal generator of digital television receiver - Google Patents

Abstract

A device for synchronizing a digital television (DTV) receiver, and in particular, an image processing unit for processing any one of an input digital broadcast signal and an NTSC broadcast signal for display, and a synchronization signal generation generating a synchronization signal in the image processing unit. And a synchronization signal correction unit for outputting a synchronization correction signal so that the synchronization signal of the synchronization signal generator is corrected based on the synchronization signal of the NTSC image if the synchronization signal of the NTSC image is within a predetermined range. The digital broadcast signal and the NTSC signal are corrected by correcting the synchronization signal of the image processing unit based on the vertical synchronization signal of the NTSC image only when the number of the horizontal synchronization signals in one vertical synchronization section of the NTSC image is the NTSC image. Depending on the type of signal input to the video signal processor that processes all Providing a definite sync signal, the picture quality can be improved.

Description

Synchronization signal generator of digital television receiver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital television receiver for receiving and processing digital video signals and analog video signals. In particular, a synchronization signal generator of a digital television receiver for generating a synchronization signal necessary for image processing by locking a synchronization signal of an analog video signal. It is about.

The United States began digital broadcasting in August 1998 and fully switched to digital broadcasting by 2006.

In Europe, the UK and Sweden are expected to switch to digital broadcasting around 2012, starting with digital broadcasting starting in 2H1998.

In addition, Korea plans to start digital test broadcasting in 2001 and carry out digital broadcasting by 2010. Japan will change all broadcasting to digital broadcasting from 2000 to 2010.

However, the development of TV sets for receiving digital broadcasts is still insufficient.

Therefore, until the development for digital broadcasting is made to some extent, there is a need for a digital television (DTV) receiver capable of simultaneously processing an NTSC broadcast signal and a digital broadcast signal.

At this time, the frame rate of NTSC broadcast video is fixed at 59.94 Hz, and the clock used is set at 74.175 MHz. On the other hand, digital broadcast video has a variety of frame rates, including 74.25 MHz clock signal for frame rates 60 Hz, 30 Hz, and 24 Hz, and 74.175 MHz clock for frame rates 59.94 Hz, 29.97 Hz, and 23.98 Hz. use.

Then, the corresponding clock signal is selected and used according to the frame rate of the input data so that the digital television receiver can be properly operated.

Therefore, when a digital broadcast and an NTSC broadcast must be processed simultaneously, an appropriate clock signal selection is required. In other words, when displaying NTSC broadcasting, data is processed by synchronizing the clock for processing the receiver to 59.94 Hz, and when displaying digital broadcasting, image data is selected by selecting an appropriate clock signal for the frame rate of the input data. Should be dealt with.

On the other hand, even though the synchronization signal of the NTSC broadcast image transmitted from the broadcasting station and the synchronization signal of the image processing unit itself in the digital TV receiver use the same 59.94Hz signal, the two synchronization signals due to the error of the clock signal due to the characteristics of the two signals, analog and digital. May occur. Therefore, this problem does not occur when the digital broadcast is received and displayed.

In other words, when processing NTSC video, a 74.175 MHz clock corresponding to 59.94 Hz is used by the video processing unit in the digital television receiver to match the NTSC synchronization signal. Therefore, the difference between the synchronization signal of the NTSC image and the synchronization signal of the image processor itself can be reduced. However, even in this case, the clock of the NTSC input side and the clock of the image processing unit may not be exactly synchronized, and even if the synchronization is consistent at first, there is a problem that the synchronization is gradually lost.

For example, one of the two synchronization signals may be relatively early or late. This is due to the data being sent in the wrong form in the actual data exchange. In this situation, an image processed with incorrect data may be displayed when performing a process such as deinterlacing in the image processing unit of the receiver.

For example, as shown in FIG. 1, when the vertical synchronization signal of the NTSC image lead and the NTSC image to be written is shifted, that is, the vertical synchronization signal of the NTSC broadcast image is relatively late with respect to the synchronization signal of the image processor in the digital television receiver. Consider the case.

In the time T, the image processing unit of the digital television receiver receives image data corresponding to the area ⓑ of the vertical synchronization signal from the NTSC image processing unit (not shown) as shown in FIG. We want to perform deinterlacing together.

However, the NTSC unit has not yet written the data in the corresponding area ⓑ as shown in FIG. 1 (b), and the image processing unit of the digital television receiver cannot store the correct image data because of synchronization of the previous data. . Therefore, the digital television receiver performs deinterlacing with wrong image data.

In order to prevent this, a circuit for synchronizing the synchronization of the NTSC image with the image processing unit of the digital television receiver is essentially required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a synchronization signal generator of a digital image signal processor for generating a synchronization signal in the digital image signal processor by locking to the synchronization signal of the analog image signal. .

Another object of the present invention is to provide a synchronization signal generator of a digital image signal processor which corrects an error of a synchronization signal only when the number of horizontal synchronization signals of an input analog image signal is within a predetermined number of ranges based on the vertical synchronization signal. Is in.

(A) and (b) of FIG. 1 are waveform diagrams showing a synchronization signal of a slowed NTSC image when an error occurs in the self-synchronization signal of the NTSC image and the synchronization signal generated by the receiver.

2 is a block diagram of a digital television receiver according to the present invention;

3 is a detailed circuit diagram of a synchronization signal corrector of FIG.

4A to 4D are signal waveform diagrams of respective parts P1 to P4 in FIG.

5 (a) to (h) is a waveform diagram showing the change in the counter value for NTSC input synchronization and trick mode recognition in FIG.

6 (a) to 6 (f) are waveform diagrams showing the output of the final synchronous correction signal by trick mode recognition in FIG.

Explanation of symbols for main parts of the drawings

100 frame rate detection unit 200 display mode detection unit

300: clock generator 400: synchronization signal correction unit

410,440: Inverter 420: Delay

430: NAND gate 450: ora gate

460: counter 470: register

480: comparator 490: correction determination unit

500: synchronization signal generator 600: image processor

700: display unit 800: video decoder

900: NTSC processing unit

In order to achieve the above object, a synchronization signal generator of an image signal processor according to the present invention includes an image processor for processing any one of an input DTV image signal and an analog image signal for display, and a synchronization signal to the image processor. A synchronization signal generator for generating a synchronous signal and a synchronous signal generator for outputting a synchronous correction signal to correct the synchronous signal of the synchronous signal generator based on the synchronous signal of the analog video signal if the synchronous signal of the analog video signal is within a predetermined range. It is characterized by including a wealth.

The synchronization signal correcting unit outputs the synchronization correction signal only when the number of horizontal synchronization signals is within a predetermined number of ranges in one vertical synchronization section of the analog video signal.

The sync signal corrector outputs the sync correction signal only when the number of horizontal sync signals in a vertical sync interval of the analog video signal is within a predetermined number of predetermined frames.

The synchronizing signal correcting unit logically combines the output of the delay and the vertical synchronizing signal of the analog television video signal to output the delay of the vertical synchronizing signal of the analog television video signal by one clock. A first calculator for detecting, a counter for counting the number of horizontal synchronization signals of the analog television video signal based on every vertical synchronization signal of the analog television video signal, and the value counted by the counter is within a predetermined number range A comparator for comparing whether there is a comparator, a calibration discrimination unit for outputting a presence / absence signal only when the output of the comparator is above a certain reliability, an output of the first calculator and an output of the calibration discrimination unit, and a logic signal according to a display mode. Output as a reset signal of the synchronization signal generator; Is characterized by consisting of a second operator.

The synchronization signal correction unit may determine whether the input analog television video signal is in normal reproduction or trick mode, and output the synchronization correction signal only when it is determined as normal reproduction.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram illustrating an apparatus for generating a synchronization signal of a digital television receiver according to an embodiment of the present invention, wherein the frame rate detector 100 detects a frame rate of an input digital broadcast signal, and whether the image to be displayed is a digital image. Display mode detection unit 200 for detecting whether the NTSC image, clock generation unit 300 for selecting and providing a corresponding clock signal according to the signal output from the frame rate detection unit 100 and the display mode detection unit 200, display mode A synchronization signal correction unit 400 which receives a display mode signal output from the detector 200, a clock signal output from the clock generator 300, and a vertical synchronization signal of an NTSC image, and outputs a synchronization correction signal; The sync signal generator 500 and the sync signal generator 50 for outputting a sync signal corrected by the sync correction signal output from the government unit 400. 0) and an image processor 600 for processing a digital image or an NTSC image input according to a clock signal and a synchronization signal output from the clock signal generator 300, and image data from the image processor 600. It consists of a display unit 700.

The clock generator 300 is an ora gate 310 for calculating a frame rate signal output from the frame rate detector 100 and a display mode signal output from the display mode detector 200, and the ora gate 310. The clock selector 320 selectively outputs any one of a 74.25 MHz clock signal and a 74.175 MHz clock signal according to the output signal of the.

In addition, as shown in FIG. 3, the synchronization signal corrector 400 may include a first inverter 410 for inverting the vertical synchronization signal of the NTSC image and a delay delay for outputting one vertical delay of the vertical synchronization signal of the NTSC image. (D-flip flop in this embodiment) 420, a NAND gate 430 for NAND-operating the signal output from the first inverter 410 and the signal output from the delay unit 420, the display mode detector A second inverter 440 for inverting the signal output from 200, a counter 460 for counting an NTSC horizontal synchronization signal based on the NTSC vertical synchronization signal, a register 470 for storing a reference value for comparison, and Comparator 480 for comparing the value counted by the counter 460 and the value stored in the register 470, a correction determination unit 490 for determining the presence or absence of correction using the result of the comparator 480, and the NAND gate 430 and the second inverter 440, and the correction By computing the signal outputted from the Iowa byeolbu 490 it consists of Iowa gate 450 to output a reset signal from the synchronous signal generating section 500. The

In the present invention configured as described above, the video decoder 800 receives the compressed digital broadcast signal, restores it to the original state, and outputs it to the image processor 600. In this case, the video decoder 800 receives horizontal and vertical synchronization signals from the image processor 600, decodes the image signal, and outputs the decoded data to the image processor 600 again. Therefore, the image processing unit 600 does not cause a problem such as a misalignment in displaying the digital broadcast signal.

In addition, the NTSC processor 900 receives an analog NTSC signal in an analog form, separates horizontal and vertical sync signals, converts them to digital, and outputs the digital signals to the image processor 600 and the sync signal corrector 400.

At this time, the frame rate detection unit 100 generates a logic signal "0" if the format of the input digital television image is any one of 60 Hz, 30 Hz, and 24 Hz, and generates a logic signal "1" if any one of 59.94 Hz and 29.98 Hz is used. Output to the unit 300.

In addition, the image processing unit 600 may set a display mode by using an I ² C bus or a remote controller, and the display mode detection unit 200 detects this and outputs a corresponding logic signal. If the display mode is set to NTSC, the display mode detector 200 outputs a logic signal “1” to the clock generator 300 when the display mode is set to the DTV. Therefore, when the display mode is set to NTSC, the image processor 600 may display the NTSC image output from the NTSC processor 900 as the main image.

That is, when the display mode is NTSC, this causes the 74.175 MHz clock to be the input clock of the image processing unit 600, similarly to when the 59.94 Hz digital broadcast (= DTV) format is input.

To this end, the OR gate 310 of the clock generator 300 performs an oral operation on the signals output from the display mode detector 200 and the frame rate detector 100, and outputs an operation result to the clock selector 320.

The clock selector 320 selects a clock signal of 74.25 MHz when the logic signal "0" is output from the OR gate 310, and selects a clock signal of 74.175 MHz when the logic signal "1" is output.

That is, when the display mode is an NTSC video mode, the clock generator 320 always selects and provides a clock signal of 74.175 MHz to the video processor 600 regardless of an input format of a digital broadcast video.

At this time, the first inverter 410 of the synchronization signal corrector 400 inverts the vertical synchronization signal of the NTSC image as shown in FIG. 4A and outputs the signal as shown in FIG. 420 delays the vertical synchronization signal of the NTSC video as shown in FIG. 4 (a) by one clock and outputs it as shown in FIG.

The NAND gate 430 of the synchronization signal corrector 400 is a vertical synchronization signal of the NTSC image delayed by one clock as shown in FIG. 4B and a vertical synchronization of the inverted NTSC image as shown in FIG. The NAND-signal of the signal detects the falling edge of the NTSC vertical synchronization signal as shown in FIG. The output of the NAND gate 430 is input to the OR gate 450.

The OR gate 450 performs an OR operation on the signal as shown in FIG. 4D and the display mode signal inverted by the inverter 440, and then outputs the result as a reset signal of the synchronization signal generator 500. .

At this time, when the display mode is set to NTSC in the display mode detector 200, the OR gate 450 outputs the signal as shown in FIG. 4 (d) to the sync signal generator 500 as a reset signal. Accordingly, when the display mode is an NTSC image, the synchronization signal generator 500 locks the NTSC vertical synchronization signal by resetting the synchronization signal of the image processor 600 at the falling edge of the NTSC vertical synchronization signal. The generated synchronization signal may be generated, and the synchronization signal is output to the image processor 600. That is, the synchronization signal generator 500 periodically corrects the vertical synchronization signal of the image processor 600 based on the vertical synchronization signal vsync separated from the NTSC processor 900.

At this time, even if the input image is an NTSC image, synchronization correction should be performed only when the number of horizontal synchronization signals is within a certain range during one vertical synchronization period of the current NTSC image.

If the video cassette recorder (VCR) is taken as an example, if the number of horizontal sync signals is within a certain range during one vertical sync period, normal playback is recognized.

Here, in the condition recognized as normal reproduction, 260 to 265 horizontal synchronization signals must exist during one vertical synchronization period of the top or bottom field. As a result, if the number of horizontal synchronization signals is less than 260 or more than 265 during one vertical synchronization period, the signal is recognized as a trick mode. In this case, 260 to 265 are used as comparison numbers for determining normal reproduction, but this may vary depending on the system designer.

For convenience of explanation, the present invention describes normal playback and trick modes by way of example.

That is, since the NTSC synchronization signal is irregular in the trick mode other than normal playback, generating the synchronization signal of the image processing unit 600 in accordance with the synchronization of the irregular NTSC image may produce undesirable results. That is, some or all of the screen may not come out or the screen may shake.

Therefore, a circuit is needed to determine whether the current NTSC video is in normal playback or trick mode and to control synchronous correction only in normal playback.

To this end, the synchronous correction unit 400 includes a counter 460, a register 470, a comparator 480, and a correction determination unit 490.

Here, the counter 460 counts the horizontal sync signal hsync based on the vertical sync signal vsync to determine whether the currently input NTSC sync signal is normal playback or trick mode. In the register 470, reference values 260 and 265 are stored.

That is, in the NTSC field divided into the top and the bottom as shown in FIG. 5A, the NTSC vertical sync signal vsync is input as shown in FIG. 5B, and the NTSC horizontal sync signal hsync is shown in FIG. (D) to (h) in FIG. 5 are enlarged parts of FIGS. 5 (b) and 5 (c).

At this time, when the hpulse as shown in FIG. 5 (f) is generated at the falling edge of the NTSC horizontal synchronization signal (hsync) as shown in (e) of FIG. 5, the value of the counter 460 increases by 1 every hpulse. In a similar manner, when a vpulse such as (g) of FIG. 5 is generated at the falling edge of the NTSC vertical synchronization signal (vsync), the value of the counter 460, which is incremented every hpulse, is reset to zero. At this time, the value of the counter 460 is the number of horizontal synchronization signals during 1 vsync.

Here, the hpulse and the vpulse may be generated at the falling edge of the horizontal synchronizing signal and the falling edge of the vertical synchronizing signal by the combination of the gates. Can be generated.

Accordingly, the comparator 480 compares the value counted by the counter 460 with the value stored in the register 470 to determine whether the count value of the counter 460 is in the range of 260 to 265.

If the count value of the counter 460 is in the range of 260 to 265, the comparator 480 determines normal playback and outputs a trick_on signal as 0 as shown in FIG.

6A to 6F are waveform diagrams showing the output of the final synchronous correction signal by trick mode recognition, for example, when normal playback is selected by using a remote controller and when rewind is selected during trick mode. Is showing.

At this time, even if the comparator 480 determines that the normal playback is performed by the comparator 480, the correction determining unit 490 of FIG. 6 (e) only when recognition of normal playback is continued for a predetermined frame or more as shown in FIG. A signal indicating that normal reproduction has been detected is output.

In this case, the predetermined frame is about 3 frames and may be recognized at the top start of the DTV.

That is, even in normal playback, the number of horizontal sync signals in one vertical sync section may be out of the range of 260 to 265 depending on the state of the system, and even in trick mode, it may be in the range of 260 to 265. Therefore, in order to determine the correct normal playback and trick mode, the normal playback is recognized for a certain frame, that is, a signal indicating that normal playback is detected only when the reliability is above a certain value is output. The same is true in trick mode.

The correction determining unit 490 outputs a logic signal "0" in normal playback and a logic signal "1" in a trick mode to the OR gate 450.

Accordingly, the OR gate 450 resets the synchronization signal of the image processing unit 600 at the falling edge of the NTSC vertical synchronization signal only when NTSC is set as the display mode and normal reproduction is detected by the correction determination unit 490. The correction signal is output as shown in FIG.

That is, the correction signal becomes active only when the display mode is NTSC and normal playback, and becomes inactive when the trick mode NTSC or the display mode is DTV.

If the type of image to be displayed is a DTV image or an NTSC image and is in trick mode, the image processing unit 600 displays the image data on the display unit 700 using the clock signal output from the clock generator 300, and NTSC. If it is an image, the display unit 700 uses both the vertical synchronization signal outputted from the synchronization signal generator 500 and the clock signal outputted from the clock generator 300 together with the vertical synchronization signal of the NTSC image corrected during normal playback. Display image data on the screen. That is, in the non-standard mode NTSC, the image processor 600 receives and processes an uncorrected sync signal from the sync signal generator 500.

According to the synchronizing signal generator of the digital television receiver according to the present invention, the synchronizing signals between two kinds of images input from a digital television receiver employing a DTV image and an NTSC image are simultaneously matched with each other. In particular, even if the input video is an NTSC video, the synchronization is corrected by correcting the synchronization signal of the image processing unit based on the vertical synchronization signal of the NTSC video only when the number of horizontal synchronizing signals in one vertical synchronization section of the NTSC video is within a predetermined number. There is an effect of obtaining a cleaner picture quality without causing an error that brings wrong data due to signal misalignment.

Claims (12)

A digital television receiver having an image processing unit for processing any one of an input digital broadcast signal and an analog broadcast signal for display and a synchronization signal generator for generating a synchronization signal in the image processing unit, And a synchronization signal correction unit for outputting a synchronization correction signal so that the synchronization signal of the synchronization signal generator is corrected based on the synchronization signal of the analog image when the synchronization signal of the analog image is within a predetermined range. Synchronizing signal generator. The synchronization signal corrector of claim 1, wherein the synchronization signal corrector And a synchronizing correction signal is output only when the number of horizontal synchronizing signals is within a predetermined number of ranges in one vertical synchronizing section of the analog video signal. The method of claim 2, wherein the synchronization signal correction unit A synchronization signal generator of a digital television receiver characterized in that the synchronization correction signal is output only when the number of horizontal synchronization signals in a vertical synchronization section of the analog video signal is within a predetermined number of predetermined frames. . The method of claim 2, wherein the predetermined predetermined number range is In the case of the top / bottom field, the synchronization signal generator of a digital television receiver is characterized in that between 260 and 265. The synchronization signal corrector of claim 1, wherein the synchronization signal corrector A delay unit for delaying and outputting the vertical synchronization signal of the analog image by one clock; A first calculator configured to logically combine the output of the delayer and the vertical synchronization signal of the analog image to detect the start of the vertical synchronization signal; A counter for counting the number of horizontal synchronization signals of the analog image based on every vertical synchronization signal of the analog image; A comparator for comparing whether a value counted by the counter is within a predetermined number range; A correction determination unit which outputs a correction existence signal only when the output of the comparator is equal to or greater than a certain reliability level; And a second calculator for combining the output of the first calculator, the output of the correction discrimination unit, and a logic signal according to a display mode to output the reset signal of the synchronization signal generator. 6. The synchronizing signal generator of claim 5, wherein the retarder is a D flip-flop. The method of claim 5, wherein the first operator And inverting the vertical synchronizing signal of the analog image and performing NAND-computation with the output of the delayer to detect the falling edge of the vertical synchronizing signal of the analog image. The method of claim 5, wherein the counter And a reset edge at the falling edge of the vertical synchronization signal of the analog image. The method of claim 5, wherein the second calculator And outputting the result of the first calculator to the sync signal generator only when the display mode is an analog image and the correctable signal is output from the calibration discriminator. The method of claim 5, wherein the reset signal is And a falling edge of the vertical synchronization signal of the analog image. The synchronization signal corrector of claim 1, wherein the synchronization signal corrector And determining whether the input analog video signal is in normal reproduction or trick mode, and outputting a synchronization correction signal only when the analog image signal is determined to be normal reproduction. 2. The synchronization signal generator of claim 1, wherein the analog video signal is an NTSC signal.