JPH09135368A - Digital horizontal synchronizing separator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain stable synchronizing separation immune to disturbance of every noise with a simple circuit by observing a signal state other than a horizontal synchronizing signal period so as to set continuously setting of a proper synchronizing separation level automatically depending on intrusion of pulse noise. SOLUTION: When a noise signal is detected for a period other than a horizontal synchronizing signal period, a noise detection circuit 7 detects a control circuit 3 based on detected data (h) to reduce a synchronizing separation level (c). The level (c) is set to a level c' not affected by noise with a level adjustment operation of the consecutive synchronizing separation level. Furthermore, when no noise signal is detected by the noise detection circuit 7 for a prescribed period, the corrected synchronizing separation level c' is adjusted again to the initial setting level to set an optimum synchronizing separation. The optimum synchronizing separation level is set in response to a state of a digital video signal by repeating it, the level (c) is decreased more than the noise level to prevent deterioration in the synchronizing separation performance arisen from noise intrusion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital horizontal sync separation circuit used in a digital television receiver.

[0002]

2. Description of the Related Art In recent years, due to advances in semiconductor technology, digital television receivers that digitize video signals and perform various signal processing have become widespread, and technological developments related to various multimedia have been activated. It is important for television receivers to support these various media, and among them, improvement of digital sync separation technology is indispensable. The conventional digital horizontal sync separation circuit will be described below with reference to FIG.

FIG. 9 is a block diagram of a conventional digital horizontal sync separation circuit. In FIG. 9, reference numeral 1 is a horizontal sync signal level discriminating circuit for discriminating between the pedestal level P and the horizontal sync signal tip level S in the horizontal sync signal period from the digital video signal a sampled at a predetermined sampling clock. 2 is a horizontal sync signal level determination circuit 1
With the pedestal level P output from and the horizontal sync signal tip level S as input, the calculation of (P + S) / 2
The sync separation level setting circuit sets the sync separation level b necessary for separating the horizontal sync signal from the digital video signal a to about 50% of the level of the horizontal sync signal.

The horizontal sync signal combined with the digital video signal a is compared with the set sync separation level b, and a signal portion having a level lower than the sync separation level b is separated by the sync separation circuit 4 as a sync signal. . The data d separated by the sync separation circuit 4 is used as phase information in the horizontal PLL circuit 5 because it is a horizontal sync pulse synchronized with the digital video signal a or a pulse corresponding to the horizontal sync signal.

The output e of the horizontal PLL circuit 5 is input to a sync discriminating circuit 6 which discriminates the sync state based on the phase with the digital video signal a. The output g of the sync discrimination circuit 6 controls the switch SW18 to send the output data d of the sync separation circuit 4 to the horizontal PLL circuit 5 before the sync pull-in.
After the sync pull-in, the control pulse f indicating the horizontal sync signal period
The output data m of the AND circuit 17 limited by
Send to L circuit 5.

As shown in FIG. 6, the output m of the AND circuit 17 limits the output of the sync separation circuit 4 to only the horizontal sync signal period by the control pulse f, so that the horizontal sync signal period after the sync pull-in is performed. Other than that, the influence of noise on the sync separation operation is reduced, and the horizontal sync pulse e that is accurately synchronized with the input digital video signal a is generated.

[0007]

However, in the above configuration, although the sync separation performance for the standard video signal conforming to the standard is sufficiently satisfied, a signal reproduced by the VTR or a signal whose horizontal frequency fluctuates, etc. For non-standard video signals, since the sync separation operation is limited to a narrow range, there is a problem that the sync performance is extremely deteriorated or the sync separation operation itself becomes impossible.

[0008]

In order to solve the above problems, a digital horizontal sync separation circuit of the present invention comprises a horizontal sync signal level discrimination circuit for discriminating between a pedestal level of a digital video signal and a horizontal sync signal tip level. A sync separation level setting circuit that sets the sync separation level to 50% of the horizontal sync signal from the output of the horizontal sync signal level determination circuit, a noise detection circuit that detects noise other than the horizontal sync signal period after the sync pull-in, and a noise detection A sync separation level control circuit that automatically controls the sync separation level according to the result,
It is composed of a sync separation circuit for synchronously separating a horizontal sync signal from a set sync separation level and a digital video signal, a sync judgment circuit for judging a sync pull-in state, and a horizontal PLL circuit.

In view of the above-mentioned problems, the present invention automatically sets the optimum sync separation level according to the input video signal level or the mixing condition of noise, so that not only the standard video signal but also the outside of the horizontal sync signal period is set. The present invention provides a digital horizontal sync separation circuit in which sync separation performance does not deteriorate even with respect to a nonstandard video signal such as a signal in which pulse noise is mixed in or a signal whose horizontal frequency fluctuates.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION The invention according to claim 1 of the present invention is
A horizontal sync signal level discriminating circuit for discriminating between the pedestal level and the horizontal sync signal tip level in the horizontal sync period from the inputted digital video signal, and a sync separation level for setting the sync separation level by the pedestal level and the horizontal sync signal tip level. A setting circuit, a sync separation level control circuit that increases the sync separation level when the digital video signal level other than the horizontal sync signal period is smaller than the sync separation level, and a sync signal from the digital video signal according to the sync separation level. A sync separation circuit for separating, a horizontal PLL circuit that generates a horizontal sync signal and a signal corresponding to a horizontal sync signal period using the output of the sync separation circuit as phase information, an output signal of the horizontal PLL circuit, and the digital video signal. The same as the synchronization determination circuit that determines the synchronization state from the phase of A noise detection circuit for determining a noise mixing state of the digital video signal other than the signal period, wherein the synchronization separation circuit sets a synchronization separation level according to an output signal from the noise detection circuit. This is a digital horizontal sync separation circuit, which compares the input video signal other than the horizontal sync period with the sync separation level and constantly observes the input video signal state of the input video signal outside the horizontal sync signal period, thereby eliminating noise. The optimum sync separation level is automatically set according to the mixing status of the signal, and reliable sync separation operation is achieved not only for standard signals but also for digital video signals with noise mixing or horizontal frequency fluctuations. It has the effect of being able to.

According to a second aspect of the present invention, a horizontal sync signal level discriminating circuit for discriminating between a pedestal level in the horizontal sync period and a horizontal sync signal tip level from an inputted digital video signal, and the pedestal level and the horizontal level. A sync separation level setting circuit for setting the sync separation level according to the sync signal tip level, and lowering the sync separation level when the digital video signal level other than the horizontal sync signal period is lower than the sync separation level, and lowering the sync separation level. In the set state, when the digital video signal level is higher than the sync separation level, a sync separation level control circuit for increasing the sync separation level, and for separating the sync signal from the digital video signal by the sync separation level Of the sync separation circuit and the output of the sync separation circuit as phase information. Signal and a horizontal PLL circuit for generating a signal corresponding to the horizontal synchronization signal period, a synchronization determination circuit for determining the synchronization state from the phase of the output signal of the horizontal PLL circuit and the digital video signal, and a digital video signal other than the horizontal synchronization signal period A noise detection circuit for determining the noise mixing state, the sync separation circuit is a digital horizontal sync separation circuit characterized by setting a sync separation level according to the output signal from the noise detection circuit, By comparing the input video signal other than the horizontal sync period with the sync separation level and always observing the input video signal state of the input video signal outside the horizontal sync period, it is optimal depending on the noise mixing status. Automatic sync separation level is set automatically, and not only standard signals but also digital signals with noise or horizontal frequency fluctuations Even for O signal, an effect that can realize a reliable synchronization separating operation.

According to a third aspect of the present invention, the noise detection circuit discriminates the lowest level of the digital video signal other than the horizontal synchronizing signal period after the sync pull-in, and the lowest level discriminating circuit. 2. A digital horizontal sync separation circuit according to claim 1, further comprising a level comparator for comparing the discrimination result with the sync separation level, wherein the sync separation level is set according to the mixing status of noise components other than the horizontal sync signal period. The optimum sync separation level is automatically set according to the noise mixing status, and not only the standard signal but also the signal with noise mixing or horizontal frequency fluctuation or the level of the horizontal sync signal is lowered A reliable sync separation operation can be realized even for a video signal.

According to a fourth aspect of the present invention, the noise detecting circuit integrates the level of the digital video signal lower than the sync separation level other than the horizontal sync signal period after the sync pull-in, and the integrating circuit. An integrated value discriminating circuit that outputs a result of comparison between the result and a certain integral specified value, and an optimum synchronization separation level is automatically set according to the mixing state of noise components other than the horizontal synchronizing signal period. The digital horizontal sync separation circuit according to Item 1, which automatically sets an optimum sync separation level according to the noise mixing state, and not only a standard signal but also a signal accompanied by noise mixing or horizontal frequency fluctuation or A reliable sync separation operation can be realized even for a digital video signal in which the level of the horizontal sync signal is lowered.

According to a fifth aspect of the present invention, there is provided a switch SW for switching the output of the sync separation level setting circuit and the output of the sync separation level control circuit between the horizontal sync signal period and the period other than the horizontal sync signal period. 2. The digital horizontal sync separation circuit according to claim 1, wherein the sync separation level is set in accordance with a noise component mixing state other than the sync signal period. The level is automatically set, and reliable sync separation operation can be realized not only for standard signals but also for digital video signals in which the level of horizontal sync signals or signals accompanied by noise or horizontal frequency fluctuations have decreased. .

Hereinafter, embodiments of the present invention will be described with reference to the drawings. (Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 5 is a waveform diagram for explaining the operation in the configuration example of the present invention shown in FIG. The same numbers and reference numerals used in FIGS. 1, 2, 3, 4, and 5 indicate the same things. Reference numeral 1 is a horizontal sync signal level discriminating circuit for discriminating between the pedestal level P and the horizontal sync signal tip level S in the horizontal sync signal period from the digital video signal a. The horizontal sync signal tip level S indicates the lowest level of one horizontal cycle period, and its value is held for one horizontal cycle period. The reason for discriminating the lowest level is to set the sync separation level that follows the level even if the level of the horizontal sync signal changes.

With the pedestal level P output from the horizontal sync signal level discrimination circuit 1 and the horizontal sync signal tip level S as inputs, the sync separation level setting circuit 2 receives (P +
The calculation of S) / 2 sets the sync separation level b to 50% of the level of the horizontal sync signal. The sync separation level b is input to the sync separation level control circuit 3. In the initial state in which the digital video signal a is input, the horizontal sync pulse e of the horizontal PLL circuit 5 and the digital video signal a are not in the sync pull-in state, and are 50% of the horizontal sync signal set by the sync separation level setting circuit 2. The corresponding sync separation level c is directly output from the sync separation level control circuit 3.

The sync separation circuit 4 separates the sync signal from the digital video signal a at the sync separation level c set in the initial input state, and outputs the data d after the sync separation as phase information. The horizontal PLL circuit 5 outputs a horizontal synchronizing pulse e synchronized with the digital video signal a using the phase data d and various pulses corresponding to a horizontal synchronizing signal period. The output pulse f of the horizontal PLL circuit 5 is a pulse indicating the horizontal synchronization signal period after the synchronization pull-in.

The synchronization discriminating circuit 6 discriminates the synchronous operation state of the horizontal PLL circuit 5 from the phase relationship between the horizontal synchronizing pulse e output from the horizontal PLL circuit 5 and the digital video signal a, and it is judged that the horizontal PLL circuit 5 is in the synchronous pull-in state. Output g
Is set to a high level. When the sync discriminating circuit 6 discriminates that it is in the sync pull-in state, the noise detecting circuit 7 uses the output control pulse f of the horizontal PLL circuit 5 within the range other than the horizontal synchronizing signal period to separate the sync separation level c and the digital video. The noise detection operation is performed using the signal a.

When noise is detected in a period other than the horizontal sync signal period, the noise detection circuit 7 controls the sync separation level control circuit 3 based on the detection data h to lower the sync separation level c. By the continuous level adjustment operation of the sync separation level, as shown in FIG. 7, the sync separation level c is finally set to a level c ′ that is not affected by noise. However, the modified sync separation level c'is set to a lower limit so as not to exceed the horizontal sync signal tip level s. Further, when noise is not detected by the noise detection circuit 7 for a certain period of time, it also has a function of re-adjusting the corrected sync separation level c ′ to the initial setting level, and sets the optimum sync separation level. An upper limit value is also set for the sync separation level c.

By repeating this operation, the optimum sync separation level can be set according to the state of the digital video signal, and by lowering the sync separation level c below the noise level, the sync separation performance due to mixing of noise or the like can be improved. In addition to preventing deterioration, it is not necessary to limit the sync separation operation range, so that a stable horizontal sync separation operation can always be realized against frequency fluctuations.

(Second Embodiment) Next, a digital horizontal sync separation circuit according to a second embodiment of the present invention will be described with reference to the drawings.

FIG. 2 shows a block diagram of a digital horizontal sync separation circuit in the second embodiment. Further, FIG. 6 is a waveform diagram for explaining the operation.

In FIG. 2, as a concrete realizing means of the noise detecting circuit of the first embodiment, inversion circuits 8 and A are provided to carry out the noise detecting operation in the period other than the horizontal synchronizing signal period.
ND circuit 9, lowest level discrimination circuit 10 and level comparator 1
And 1. When the output g of the synchronization determination circuit 6 is set to the high level, the AND circuit 9 uses the pulse obtained by inverting the control pulse f indicating the horizontal synchronization signal period by the inversion circuit 8 to determine the level of the digital video signal a. Is set to a period other than the horizontal sync signal period. Lowest level discrimination circuit 1
0 uses the output of the AND circuit 9 to determine the signal level of the digital video signal a during periods other than the horizontal synchronizing signal period,
The lowest level i is output. The level comparator 11 performs a level comparison between the sync separation level c output from the sync separation level control circuit 3 and the lowest level i of the digital video signal a during a period other than the horizontal sync signal period output from the lowest level determination circuit 10. Then, the determination data h is output.

As shown in FIG. 6, the sync separation level control circuit 3 judges that noise is mixed when the minimum level i is lower than the sync separation level c in the initial setting according to the judgment data h. In order to prevent deterioration of the sync separation operation due to noise, the initially set sync separation level c is lowered by n steps, and this operation is continued until the modified sync separation level c'is lower than the lowest level i. However, a lower limit value is set for the sync separation level c so as not to exceed the horizontal sync signal tip level. Further, the sync separation level control circuit 3 is also provided with control for increasing the sync separation level c in units of n steps when the set sync separation level c is higher than the lowest level i for a certain period of time. , Set the optimal sync isolation level. An upper limit value is also set for the sync separation level c.

By repeating this operation, it is possible to set the optimum sync separation level in accordance with the state of the digital video signal, prevent the deterioration of the sync separation performance due to mixing of noise, etc., and limit the sync separation operation range. Therefore, a stable horizontal sync separation operation can be always realized against frequency fluctuations.

(Third Embodiment) Next, a digital horizontal sync separation circuit according to a third embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a block diagram of a digital horizontal sync separation circuit according to the third embodiment. Further, FIG. 7 is a waveform diagram for explaining the operation.

In FIG. 3, as a concrete implementation means of the noise detecting circuit of the first embodiment, an inverting circuit 8 and an A circuit are provided for performing the noise detecting operation in a period other than the horizontal synchronizing signal period.
It has an ND circuit 9, an integrating circuit 12, and an integrated value discriminating circuit 13. 3 is different from the second embodiment in that
In the second embodiment, the signal level other than the horizontal sync signal period is used as the determination reference in the control method of the sync separation level control circuit 3 other than the horizontal sync signal period. 8 and the AND circuit 9 are used to use the integrated value of the phase data d after the sync separation other than the horizontal sync signal period. Reference numeral 12 is an integration circuit that integrates the phase data d output from the sync separation circuit 4 when the phase data d shows a certain value outside the horizontal sync signal period. In the case of the standard video signal, there is no signal level lower than the sync separation level c except during the horizontal sync signal period, so that the signal level higher than the sync separation level c is set to 0.

As shown in FIG. 7, in a digital video signal in which a signal level lower than the sync separation level c in the initial setting exists during periods other than the horizontal sync signal period, the output d of the sync separation circuit 4 is lower than the sync separation level c. Indicates a certain value during the signal level period. The value is integrated by the integrating circuit 12.

Judgment data j calculated by the integrating circuit 12
Is compared with a certain integral prescribed value in the integral value discriminating circuit 13, and when the integral result is larger than the prescribed value, the synchronous separation level control circuit 3 is controlled by the decision data h. The control method of the sync separation level control circuit 3 is the same as that of the second embodiment. If the specified integral value is set stepwise, more continuous control becomes possible.

By repeating this operation, it is possible to set the optimum sync separation level according to the state of the digital video signal, prevent the deterioration of the sync separation performance due to the mixing of noise, and limit the sync separation operation range. Therefore, a stable horizontal sync separation operation can be always realized against frequency fluctuations.

(Fourth Embodiment) Next, a digital horizontal sync separation circuit according to a fourth embodiment of the present invention will be described with reference to the drawings.

FIG. 4 shows a block diagram of a digital horizontal sync separation circuit in the fourth embodiment. In FIG.
The difference from the configuration of FIG.
By adding the configuration of the switch SW16 and the switch SW16, the sync separation level is switched between the horizontal sync signal period after the sync pull-in and the period other than the horizontal sync signal period.

The operation of adjusting the sync separation level c to a level not affected by noise by detecting noise in a period other than the horizontal sync signal period is the same as in FIG. Keep the default sync isolation level. In order to realize this operation, the output k of the AND circuit 15 depending on the output g of the synchronization discrimination circuit 6
Then, the switch SW16 is controlled to always use the output b of the sync separation level setting circuit 2 set to 50% of the level of the horizontal sync signal as the sync separation level before the sync pull-in.

After the synchronization pull-in, the output SW of the AND circuit 15 limited by the output of the inverting circuit 14 which inverts the output control pulse f of the horizontal PLL circuit is used to switch the switch SW16 to a period other than the horizontal synchronization signal period and the horizontal synchronization signal period. 8, and the output b of the sync separation level setting circuit 2 is set to the sync separation level in the horizontal sync signal period as shown in FIG. 8, and the synchronization is not affected by the noise set by the noise detection result except in the horizontal sync signal period. Isolation level c can be used.
Therefore, the output 1 of the switch SW16 is set to different sync separation levels in the horizontal sync signal period and in periods other than the horizontal sync signal period.

With this configuration, the optimum sync separation level can be set according to the state of the digital video signal,
While preventing the deterioration of the sync separation performance due to the mixing of noise,
Since it is not necessary to limit the sync separation operation range, a stable horizontal sync separation operation can always be realized even with frequency fluctuations. Furthermore, by switching the sync separation levels in the horizontal sync signal period and in periods other than the horizontal sync signal period, a reliable sync separation operation can be realized even for a digital video signal whose horizontal sync signal level has dropped.

[0038]

As described above, according to the present invention, by observing the signal states other than the horizontal sync signal period, the optimum sync separation level can be continuously set automatically in accordance with the inclusion of pulse noise. Therefore, with a relatively simple circuit configuration, it is possible to prevent the deterioration of the sync separation performance due to any noise disturbance, frequency fluctuations, level drop of the horizontal sync signal, etc., and to realize stable sync separation operation.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital horizontal sync separation circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a digital horizontal sync separation circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a digital horizontal sync separation circuit according to a third embodiment of the present invention.

FIG. 4 is a block diagram of a digital horizontal sync separation circuit according to a fourth embodiment of the present invention.

FIG. 5 is an operation waveform diagram of horizontal sync separation in the first embodiment of the present invention.

FIG. 6 is an operation waveform diagram of horizontal sync separation in the second embodiment of the present invention.

FIG. 7 is an operation waveform diagram of horizontal sync separation in the third embodiment of the present invention.

FIG. 8 is an operation waveform diagram of horizontal sync separation in the fourth embodiment of the present invention.

FIG. 9 is a block diagram of a digital horizontal sync separation circuit in a conventional example.

FIG. 10 is an operation waveform diagram of horizontal sync separation in a conventional example.

[Explanation of symbols]

 1 horizontal sync signal level discrimination circuit 2 sync separation level setting circuit 3 sync separation level control circuit 4 sync separation circuit 5 horizontal PLL circuit 6 sync judgment circuit 7 noise detection circuit 8, 14 inverting circuit 9, 15 AND circuit 10 lowest level judgment circuit 11 Level Comparator 12 Integration Circuit 13 Integration Value Discrimination Circuit 16 Switch SW

Claims (5)

[Claims] 1. A horizontal sync signal level discriminating circuit for discriminating between a pedestal level and a horizontal sync signal tip level during a horizontal sync period from an input digital video signal, and a sync separation level based on the pedestal level and the horizontal sync signal tip level. A sync separation level setting circuit for setting, a sync separation level control circuit for increasing the sync separation level when the digital video signal level other than the horizontal sync signal period is smaller than the sync separation level, and the digital video according to the sync separation level A sync separation circuit for separating a sync signal from a signal, a horizontal PLL circuit for generating a horizontal sync signal and a signal corresponding to a horizontal sync signal period using the output of the sync separation circuit as phase information, and an output signal of the horizontal PLL circuit. And a synchronization determination time for determining the synchronization state from the phase of the digital video signal. And a noise detection circuit that determines the noise mixing state of the digital video signal other than the horizontal synchronization signal period, and the synchronization separation circuit sets a synchronization separation level according to the output signal from the noise detection circuit. A digital horizontal sync separation circuit characterized by the above. 2. A horizontal sync signal level discriminating circuit for discriminating a pedestal level and a horizontal sync signal tip level during a horizontal sync period from an input digital video signal, and a sync separation level based on the pedestal level and the horizontal sync signal tip level. A sync separation level setting circuit for setting the sync separation level when the digital video signal level other than the horizontal sync signal period is lower than the sync separation level, and the digital video signal is set in a state where the sync separation level is set low. When the level is higher than the sync separation level, a sync separation level control circuit for increasing the sync separation level, a sync separation circuit for separating a sync signal from a digital video signal according to the sync separation level, and the sync separation Corresponding to horizontal sync signal and horizontal sync signal period using circuit output as phase information A horizontal PLL circuit that generates a signal, a synchronization determination circuit that determines a synchronization state from the output signal of the horizontal PLL circuit and the phase of the digital video signal, and a noise mixing state of the digital video signal other than the horizontal synchronization signal period. And a noise detection circuit, wherein the sync separation circuit sets a sync separation level according to an output signal from the noise detection circuit. 3. A noise detection circuit is a minimum level discriminating circuit for discriminating the lowest level of a digital video signal other than the horizontal synchronizing signal period after the synchronization pull-in, and a level for comparing a discrimination result of the lowest level discriminating circuit with a sync separation level. 2. The digital horizontal sync separation circuit according to claim 1, further comprising a comparator, wherein the sync separation level is set according to a mixing condition of noise components other than the horizontal sync signal period. 4. The noise detection circuit compares an integration circuit that integrates the level of a digital video signal lower than the sync separation level other than the horizontal sync signal period after the sync pull-in and the result of the integration circuit with a certain integral specified value. 2. The digital horizontal sync separation circuit according to claim 1, further comprising an integrated value discriminating circuit for outputting, and automatically setting an optimum sync separation level according to a mixing condition of noise components other than the horizontal sync signal period. 5. A state in which a noise component is mixed during a period other than the horizontal synchronization signal period is provided with a switch SW for switching the output of the synchronization separation level setting circuit and the output of the synchronization separation level control circuit between the horizontal synchronization signal period and the period other than the horizontal synchronization signal period. The digital horizontal sync separation circuit according to claim 1, wherein the sync separation level is set according to