JP3075009B2 - Phase locked loop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit used for a video tape recorder or the like.

[0002]

2. Description of the Related Art In recent years, digitization of signal processing has been progressing in consumer video tape recorders. Automatic frequency control (A), a function necessary for signal processing of chroma signals
FC) and automatic phase control (APC) are also being digitally processed. A phase locked loop circuit is used for AFC and APC.

A conventional AFC phase locked loop circuit will be described below. FIG. 2 shows an example of a conventional AFC phase locked loop circuit. The phase locked loop circuits are all digital processing circuits.

[0004] As shown in FIG. 2, it comprises a phase comparator 1, a loop filter 5 and a numerically controlled oscillator 6.

The operation of the conventional phase locked loop circuit configured as described above will be described below with reference to FIG.

In the above configuration, the horizontal comparator and the output of the numerically controlled oscillator 6 are input to the phase comparator 1. The horizontal synchronizing signal is 2 by a clock of 10 MHz or more.
The value has been digitized and input, and the horizontal synchronizing signal portion is 1 and the other portions are 0. The numerically controlled oscillator 6 receives the phase signal from the loop filter 5, calculates the sum of the output phase of the numerically controlled oscillator 6 and the phase input from the loop filter 5 every clock, and outputs the calculation result to the numerically controlled oscillator. 6 is output. The output of the numerically controlled oscillator 6 is digital data of n bits (n is an integer), and the portion overflowed by the above calculation is ignored. In other words, the result of the calculation is the remainder of 2 to the power of n. The output of the numerically controlled oscillator 6 is a phase signal from −2 (n−1) power to +2 (n−1) −1 when considered in 2's complement notation. In the phase comparator 1, the output phase signal of the numerical control oscillator 6 at the time when the horizontal synchronizing signal changes from 0 to 1 is used as the phase difference output of the phase comparator. The phase difference output is held until the horizontal synchronizing signal changes from 0 to 1. The phase difference output is input to a loop filter 5, and the loop filter 5 outputs a phase signal obtained by smoothing the phase difference signal by a digital filter. PLL with the above configuration
A circuit is controlled so that the output of the loop filter 5 changes in phase with one clock of the horizontal synchronization signal.

[0007]

However, in the conventional configuration as described above, the phase comparison between the horizontal synchronizing signal and the burst signal is performed intermittently, and therefore, as shown in FIG.
(M is an integer, FIG. 3 is an example of m = 10) 1 horizontal scanning line
As a set, the phase difference output of the phase comparator repeats a constant phase change, is not pulled into the horizontal synchronization frequency to be locked, and the pull-in range of the PLL is 1 / m of the horizontal synchronization frequency.
There was a problem of becoming. Also, if the loop gain is increased, the value of m is reduced and the pull-in range is widened. However, in this method, the response is fast, and the response to noise in a steady state becomes easy.

An object of the present invention is to solve the above-mentioned problem and to provide a phase locked loop circuit which widens a pull-in range without changing a loop gain.

[0009]

To achieve the above object, a phase locked loop circuit according to the present invention comprises a phase comparator for detecting a phase difference between two input signals, and a phase difference signal output from the phase comparator. Means for sampling the phase difference signal, and calculating the absolute value of the difference between the most recently sampled phase difference signal and the phase difference signal sampled immediately before the most recently sampled phase difference signal. A phase difference judging circuit for judging whether the value is equal to or more than a certain value and outputting the result, and a signal sampled most recently when the absolute value of the signal output from the phase difference judging circuit is smaller than a certain value. A switching circuit that outputs a phase difference signal indicating that the phase difference is 0 when the absolute value is equal to or greater than a certain value, and an output signal of the switching circuit is input. And a loop filter.

[0010]

According to the present invention, there is provided a sampling system in which the phase difference output changes from a value close to +180 degrees to a value close to -180 degrees or from a value close to -180 degrees to a value close to +180 degrees. A point is detected, and the phase difference output at that time is not output to the loop filter.

In the process of pulling in the frequency of the phase locked loop circuit, the following can be considered. For example, for a horizontal synchronization signal frequency of 15625 Hz (for a PAL signal),
If the output frequency of the numerically controlled oscillator is 10% higher than the horizontal synchronization signal frequency, the phase is 360 at the frequency of 1562.5 Hz which is the difference frequency between the two.
゜ It will change. The phase locked loop circuit operates to increase the frequency of the numerically controlled oscillator when the phase difference output of the phase comparator is negative, and lowers the frequency of the numerically controlled oscillator when the phase difference output of the phase comparator is positive. To work. If the movement for raising the frequency and the movement for lowering the frequency are balanced as shown in FIG. 3, it will not be possible to draw in to a lower frequency. Therefore, in the present invention, in order to break this balance, the phase difference output is set to +
By detecting a point that changes from around 180 ° to −180 ° and not outputting the phase difference output at that time to the loop filter, by enabling the frequency pull-in,
The pull-in range can be widened without changing the loop gain.

[0012]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a phase locked loop circuit according to the present embodiment. As shown in FIG. 1, the phase comparator 1, D
It comprises a flip-flop 2, a phase difference determination circuit 3, a switching circuit 4, a loop filter 5, and a numerically controlled oscillator 6.

The operation of the phase locked loop circuit configured as described above will be described with reference to FIG.

In the configuration, the phase comparator 1, the loop filter 5, and the numerically controlled oscillator 6 are the same as in the conventional example. The horizontal synchronizing signal and the output of the numerically controlled oscillator 6 are input to the phase comparator 1. Horizontal sync signal is 10MHz
The data is digitized and input by the above clock, and the horizontal synchronizing signal portion is 1 and the other portions are 0.
It is. The numerically controlled oscillator 6 receives the phase signal from the loop filter 5, calculates the sum of the output phase of the numerically controlled oscillator 6 and the phase input from the loop filter 5 every clock, and outputs the calculation result to the numerically controlled oscillator. 6 is output. The output of the numerically controlled oscillator 6 is digital data of n (n is an integer) bits, and the overflow of the calculation is ignored. In other words, the result of the calculation is the remainder of 2 to the power of n. The output of the numerically controlled oscillator 6 is -2 when considered in two's complement notation.
From (n-1) to +2 (n-1) -1. In the phase comparator 1, the output phase signal of the numerically controlled oscillator 6 when the horizontal synchronizing signal changes from 0 to 1 is used as the phase difference output of the phase comparator. The phase difference output is held until the horizontal synchronizing signal changes from 0 to 1. The phase difference output is a D flip-flop 2,
The signals are input to the phase difference determination circuit 3 and the switching circuit 4. In the D flip-flop 2, the output phase difference signal of the phase comparator 1 at the time when the horizontal synchronization signal changes from 0 to 1 is used as the output of the D flip-flop 2. As a result, the output of the D flip-flop 2 is a phase difference output when the horizontal synchronizing signal one horizontal period earlier is input.

The output of the D flip-flop 2 is input to the phase difference judgment circuit 3. The phase difference determination circuit 3 calculates the absolute value of the difference between the output phase of the phase comparator 1 and the output phase of the D flip-flop 2, and determines a calculated constant value k (k is an integer) )
Output the judgment result. The determination result is output as 1-bit digital data. If the absolute value is equal to or larger than k, 1 is output.
If the absolute value is smaller than k, 0 is output. The determination result is a control signal for the switching circuit 4. Switching circuit 4
Then, if the discrimination result is 0, the output phase of the phase comparator 1 is used as the output of the switching circuit 4, and if the discrimination result is 1, 0 is output. The output of the switching circuit 4 is input to the loop filter 5. The loop filter 5 outputs a phase signal obtained by smoothing the phase difference signal output from the switching circuit 4 by a digital filter. The PLL circuit having the above configuration is controlled so that the output of the loop filter 5 changes in phase with one clock of the horizontal synchronization signal.

With this configuration, the phase difference output is +1
From a value close to 80 degrees to a value close to -180 degrees, or
Detecting a sampling point that changes from a value close to -180 degrees to a value close to +180 degrees and not outputting a phase difference output at that time to the loop filter 5, thereby widening the pull-in range without changing the loop gain. Can be.

The frequency of the horizontal synchronizing signal is 15625 Hz,
As shown in FIG. 3, when m = 10 or less and frequency integration is not possible, the pull-in range becomes 1562.5 Hz. On the other hand, when the phase-locked loop circuit of the present invention is used, for example, if the value of k is set to a phase of 270 °, the range in which the frequency is not drawn is m = 4 or less. Become wider.

[0019]

As described above, according to the present invention, it is possible to provide a PLL circuit which widens the pull-in range without changing the loop gain.

In this embodiment, the phase-locked loop circuit in the AFC has been described. However, the phase-locked loop circuit in the APC is also provided between the phase comparator and the loop filter in the same manner as in the AFC. A similar effect can be obtained by including a circuit, a phase difference determination circuit, and a switching circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of a phase locked loop circuit according to one embodiment of the present invention.

FIG. 2 is a block diagram of a conventional phase locked loop circuit.

FIG. 3 is a characteristic diagram showing a phase difference signal for explaining a problem of the conventional phase locked loop circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Phase comparator 2 D flip-flop 3 Phase difference judgment circuit 4 Switching circuit 5 Loop filter 6 Numerically controlled oscillator

Claims (1)

(57) [Claims] A phase comparator for detecting a phase difference between two input signals; a means for sampling a phase difference signal output from the phase comparator; a phase difference signal sampled most recently; A phase difference signal for calculating an absolute value of a difference from a phase difference signal sampled immediately before the sampled phase difference signal to determine whether the absolute value is equal to or greater than a predetermined value and outputting the result; And outputting the most recently sampled phase difference signal when the signal output from the phase difference determination circuit means that the absolute value is smaller than a certain value. A switching circuit that outputs a phase difference signal indicating that the phase difference is 0 when it means the above,
A loop filter to which an output signal of the switching circuit is input.