JPH08280042A - Timing generation circuit - Google Patents

Abstract

PURPOSE: To provide a function corresponding to at least two television systems with different number of samples in one horizontal period with a small circuit scale. CONSTITUTION: A designation signal designates formats in accordance with input digital video data Din from at least two formats. A counter means 12 counts the maximum number of samples in at least one horizontal period of the input digital video data Din based on the control signal LP of a skip count control means 15. Also, the skip count control means 15 controls the counter means 12 so that the count of the number of samples other than that in the effective video period of one horizontal period can be skipped by the arbitrary number based on the format designated by the designation signal. A timing generating means 13 detects a position where a synchronizing signal is attached by the count value of the counter means 12, and generates a timing signal based on the position.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing generating circuit for adding a synchronizing signal to digital video data to generate a timing signal for performing formatting required for serial transmission, and more particularly to a timing generating circuit. The present invention relates to a timing generation circuit compatible with both the NTSC system and the PAL system in which the number of samples in the horizontal period is different.

[0002]

2. Description of the Related Art For example, a digital video tape recorder (hereinafter referred to as DVTR: Digital) of a current television is used.
It is called Video Tape Recorder. )
3 models of D1, D2 and D3 standards have been put into practical use. Among these models, the D1 standard DVTR is C
It is a DVTR of the world unified standard of the current television component system based on CIR Recommendation 601, and it records digital video data in both formats of the so-called NTSC system which is 525 systems and the so-called PAL system which is 625 systems. You can

Here, when recording digital video data, formatting necessary for serial transmission is performed. This formatting is performed by using a serial digital interface (hereinafter, SD) as shown in FIG.
I: Serial Digital Interface
say e. ) IC. A television system of a 525 system or a 625 system is designated for this SDIIC, whereby the SDIIC can operate in accordance with the designated system.

That is, the SDIIC is a timing generation circuit 100 that generates various timing signals necessary for performing formatting in accordance with a designated method.
And various format processing is performed on the input digital video data D _in based on the timing signal from the timing generation circuit 100 to output digital video data D _ou.
It includes process circuits d _{1 to} d _n that generate _t .

The timing generation circuit 100 also includes a counter 102 that counts a clock C _H synchronized with a sample of the input digital video data D _in and a pulse generation that generates a reset pulse for the counter 102 when the horizontal synchronizing signal HR falls. A unit 101, a timing generation unit 103 for the 525 system and a timing generation unit 104 for the 625 system, which generate various timing signals corresponding to the 525 system or the 625 system based on the count value of the counter 102. A selection output unit 105 that selectively outputs various timing signals from the timing generation unit 103 or the timing generation unit 104 to the process circuits d _{1 to} d _n according to the designated method.

Furthermore, the timing generator 103 for 525 system includes an address decoder a ₁ ~a _n corresponding to the processing circuit d ₁ to d _n, similarly timing generator 104 for the 625 method, Process an address decoder b ₁ ~b _n corresponding to the circuit d ₁ to d _n, the selection output unit 10
5 versa, a switch c ₁ to c _n corresponding to the processing circuit _d 1 to d _n.

Hereinafter, as the format processing, for example,
End of active video (hereinafter, EAV: End) which is a synchronizing signal _{in the} input digital video data D _in
Called of Active Video. ), And start of active video (hereinafter, SAV: Sta)
It is called rt of Active Video. ) Will be described.

First, when the 525 system is designated for the timing generation circuit 100, in the 525 system, the number of samples in one horizontal period H is 1716 Sample / H. Therefore, as shown in FIG. 6, when the horizontal synchronizing signal HR is input to the pulse generator 101, the counter 10 counts the number of horizontal samples at the falling edge thereof.
2 is reset. Then, when the counter 102 counts from "0" to "1715", the counter 102 is reset by the fall of the horizontal synchronizing signal HR again. Such an operation is repeated to generate a horizontal address.

Here, in the 525 system, the count value "0" to the input digital video data D _in
"3", that is, EA at positions of addresses [0] to [3]
V is added, and SAV is added to the positions of addresses [272] to [275].

Therefore, the address decoder a ₁ decodes the addresses [0] to [3] from the counter 102 and outputs the timing signal based on the address to the switch c ₁ . Further, the address decoder a ₂ is
Addresses [272] to [275] from the counter 102
Is decoded and a timing signal based on the address is output to the switch c ₂ .

The switches c ₁ and c ₂ have 525
Since this method is specified, the switch c ₁ and the switch c ₂ are the address decoder a ₁ and the address decoder a.
_The timing signal output from _{2 is} selectively output to the process circuit d ₁ and the process circuit d ₂ . As a result, the process circuit d ₁ outputs E to the input digital video data D _n based on the timing signal from the switch c _1.
AV is added. Further, the process circuit d ₂ adds S to the input digital video data D _n to which EAV is added by the process circuit d ₁ based on the timing signal from the switch c _2.
AV is added.

Next, when the 625 line system is designated for the timing generation circuit 100, the operation is the same as in the case of the 525 system described above, but in this 625 line system, one horizontal period H The number of samples is 1728 Sample / H, which is different from the number of samples in the 525 system. Therefore, the counter 102 counts up to "1727".

Further, in the 625 system, EAV is added to the positions of the addresses [0] to [3] with respect to the input digital video data D _n , and the addresses [284] to [28] are added.
SAV is added to the position [7]. Therefore, the address decoder b ₁ decodes the addresses [0] to [3] from the counter 102 and outputs the timing signal based on the address to the switch c ₁ . The address decoder b ₂ also decodes the addresses [284] to [287] from the counter 102 and outputs a timing signal based on the address to the switch c ₂ . Then, the switches c ₁ and c ₂ selectively output the timing signals output from the address decoder b ₁ and the address decoder b ₂ to the process circuit d ₁ and the process circuit d ₂ , respectively.

Therefore, as in the case of the 525 line system, the process circuit d ₁ adds EAV to the input digital video data D _n based on the timing signal from the switch c ₁ , and the process circuit d ₂ switches the switch c 1. _Based on the timing signal from ₂ , the process circuit d ₁ adds SAV to the input digital video data D _n to which EAV has been added.

As described above, since the timing signal corresponding to the specified television system is generated, the EAV is provided at the predetermined position of the input digital video data D _in.
And SAV are added.

[0016]

However, in the timing generation circuit 100 as described above, the 525-line system and the 625-line system are used.
In order to support both types of this system, two timing generation units, that is, the timing generation unit 103 for the 525 line system and the timing generation unit 104 for the 625 line system were necessary.

That is, since the number of samples in one horizontal period H is different between the 525 line system and the 625 line system,
In order to support both methods, it is necessary to control the counter according to both methods. Therefore, in the 525 system, an address decoder a ₁ for decoding addresses [0] to [3] to which EAV is added, an address decoder a ₂ for decoding addresses [272] to [275] to which SAV is added, and In the 625 system, an address decoder b ₁ for decoding addresses [0] to [3] to which EAV is added and an address [28] to which SAV is added
4] to [287] for decoding the address decoder b ₂
Became necessary, and the circuit scale of the timing generation circuit had become large.

When performing formatting,
In addition to the timing signal for adding EAV and SAV to the input digital video data D _n , it is actually necessary to generate various other timing signals. Therefore, as described above, the timing generation circuit 100 has
Numerous switch c ₁ to c _n and the process circuit d ₁ to d _n are provided. Therefore, a large number of address decoders a _{1 to} a _n and address decoders b ₁ corresponding to both types are used.
~b _n also it becomes necessary, had gotten the cause of the increase in the circuit scale.

As described above, in the conventional timing generation circuit, when it is attempted to realize the function corresponding to at least two kinds of television systems in which the number of samples in one horizontal period is different, the circuit scale becomes large. , The power consumption of the circuit and the manufacturing cost could not be reduced.

Therefore, the present invention has been made in view of the above-mentioned conventional circumstances, and has the following objects.

That is, an object of the present invention is to provide a timing generation circuit which realizes a function corresponding to at least two television systems having different numbers of samples in one horizontal period with a small circuit scale.

Another object of the present invention is to provide a timing generation circuit which can reduce the power consumption of the circuit and the manufacturing cost because the circuit scale is small.

[0023]

In order to solve the above-mentioned problems, the timing generating circuit according to the present invention comprises a selecting means for selecting a format corresponding to input digital video data from at least two formats, and an input digital video. Counting means for counting the maximum number of samples of at least one horizontal period of data, and counting is skipped by an arbitrary number when counting the number of samples other than the valid video period of one horizontal period based on the format selected by the selecting means. And a timing generation means for detecting a position to which a synchronization signal is added by the count value of the counting means and generating a timing signal based on the position, the skip count control means for controlling the counting means. The means is based on the control of the skip count control means. The number of samples to skip characterized by counting.

[0024]

In the timing generating circuit according to the present invention, the selecting means selects the format corresponding to the input digital video data from at least two formats. The counting means counts the maximum number of samples of at least one horizontal period of the input digital video data under the control of the skip count control means. The skip count control means controls the counting means based on the format selected by the selecting means so that the counting is skipped by an arbitrary number when counting the number of samples other than the effective video period of one horizontal period. The timing generating means detects the position to which the synchronizing signal is added based on the count value of the counting means and generates a timing signal based on the position.

[0025]

An embodiment of the present invention will be described below with reference to the drawings.

The timing generating circuit according to the present invention is, for example, a serial digital interface (hereinafter referred to as SDI: Serial Digital) as shown in FIG.
It is called Interface. ) Applies to IC2.

That is, the SDIIC 2 operates in correspondence with both the 525-line system and the 625-line system, and the SDIIC 2 has 10-bit input digital video data D _in of the 525-line system or the 625-line system. A horizontal synchronizing signal HR, a frame synchronizing signal FR, a designation signal for designating a 525 line system or a 625 line system, and a clock C _H synchronized with a sample of the input digital video data D _in are input, and are required for serial transmission from the SDIIC 2. The 10-bit output digital video data D _out subjected to various formatting is output.

More specifically, the SDIIC 2 is provided with a timing generation circuit 1 to which a horizontal synchronizing signal HR, a clock C _H and a designation signal are supplied, as shown in FIG.
And process circuits Pr _{1 to} P to which the input digital video data D _in and the output signal of the timing generation circuit 1 are supplied.
r _n and.

The timing generating circuit 1 is a timing generating circuit according to the present invention, and includes a pulse generating section 11 to which a horizontal synchronizing signal HR and a clock C _H are respectively supplied, an output signal of the pulse generating section 11 and a preset value P _V. , The timing generator 13 and the jump address decoder 15 to which the output signal of the counter 12 is supplied, and the output signal of the jump address decoder 15,
A switch 16 to which a 525/625 designation signal and a high level signal (hereinafter, referred to as H signal) are respectively supplied.

Further, the timing generator 13 has address decoders Ad ₁ to Ad ₁ to which the output signal of the counter 12 is supplied.
Ad _n . This address decoder Ad _{1 to} Ad
_n is provided corresponding to the process circuits Pr _{1 to} Pr _n , and the output signals of the address decoders Ad _{1 to} Ad _n are
It is adapted to be supplied to the corresponding process circuits Pr _{1 to} Pr _n .

Here, the timing generating circuit 1 generates various timing signals necessary for formatting by the process circuits Pr _{1 to} Pr _n . For example, an end-of-active signal which is a synchronizing signal is used. Video (hereinafter, EAV: End of Active Vid
say eo. ) And Start of Active Video (SAV: Start of Active V)
It's called video. ) Will be described below. The EAV and SAV are each composed of, for example, information indicating whether it is the first field or the second field, video data or vertical blanking data, and EAV or SAV, and an error correction code. It is a synchronizing signal.

First, the input digital video data D _in is
As shown in FIGS. 3 and 4, the sampling frequency T (=
1 / horizontal period H is 1716T
Or 565 lines method in which one horizontal period H is 1728T. Also, 52
In the 5-line method, the horizontal blanking period HB is 276T.
In the 625 line method, the horizontal blanking period HB
Is 288T. Therefore, the effective video period is
Both methods will be 1440T. During this effective video period, for example, a video data stream Data including Y, C _B , and C _R data is transmitted and received.

Such input digital video data D _in
Are supplied to the process circuit Pr ₁ . At the same time,
A designation signal indicating whether the input digital video data D _{in is} the television system, that is, the 525 system or the 625 system is supplied to the switch 16 as a selection signal. The horizontal synchronizing signal HR is supplied to the pulse generator 11, and the clock C _H is supplied to the pulse generator 11 and the counter 12, respectively.

When the horizontal synchronizing signal HR is supplied, the pulse generator 11 detects the falling edge of the horizontal synchronizing signal HR as a negative polarity pulse. Then, the pulse generator 11 outputs the detected negative polarity pulse as the reset pulse RP to the counter 12 in synchronization with the clock C _H.

The counter 12 has 1728T which is one horizontal period H of the 625 system, that is, the number of samples 1728Sample / H in one horizontal period H is "0" to "172".
It is a counter composed of 11 bits so that it can continuously count up to 7 ". Therefore, the counter 12
After being reset by the reset pulse RP from the pulse generator 11, the clock C _H is continuously counted from “0”. The count value of the counter 12 is supplied to the address decoders Ad ₁ and Ad ₂ and the jump address decoder 15 as the address Adr.

Here, in this embodiment, the counter 12 is given a preset value P _V. This preset value P _V is a value whose setting can be changed depending on the circuit configuration and the like. Further, the counter 12 has a jump address decoder 1 according to the 525 line system or the 625 line system.
The load pulse LP is supplied from 5 through the switch 16.

For example, when the designation signal supplied to the switch 16 is the 625-line designation, the switch 16
The H signal is selectively output so as to be output to the counter 12. Therefore, the load pulse LP is not given to the counter 12, and the counter 12 has "0" to "172".
Up to 7 ”is counted continuously. Then, "172
When counting to "7", the reset pulse RP is output from the pulse generator 11 due to the fall of the horizontal synchronizing signal HR, and the counter 12 is reset by the reset pulse RP. Such an operation is repeated in the horizontal direction to generate the address Adr.

On the other hand, when the designation signal supplied to the switch 16 is the 525-line system designation, an operation different from the case of the 625-line system designation is performed. That is, as shown in FIG. 4, in the horizontal blanking period HB, the count value of the counter 12 is jumped only once.

More specifically, the 525 system and 62
In the 5-line method, the number of samples in the horizontal blanking period HB is different between “276” and “288”. But,
The number of samples in the effective video period is "144" in both formulas.
0 ". Therefore, by jumping 12 clocks, which is the difference in the sample numbers between the 525 system and the 625 system, in the horizontal blanking period HB, the address decoders Ad ₁ and Ad ₂ are made common to the 525 system and the 625 system. .

Therefore, for example, the preset value P _V given to the counter 12 is set to "141". The counter 12
After being reset by the reset pulse RP from the pulse generator 11, the clock C _H is continuously counted from “0”. The count value of the counter 12 is supplied to the address decoders Ad ₁ and Ad ₂ and the jump address decoder 15 as the address Adr.

The jump address decoder 15 decodes the address Adr from the counter 12 to detect an address at which a jump is made, and outputs the detection pulse to the switch 1
Output to 6. Here, the address to jump to is “128”, for example. Therefore, when the count value of the counter 12 becomes “128”, the jump address decoder 15 outputs a detection pulse.

The switch 16 selectively outputs the output signal of the jump address decoder 15 to the counter 12 in response to the designation signal indicating the 525 system designation. Therefore, the detection pulse output from the jump address decoder 15 is supplied to the counter 12 as the load pulse LP.

When the load pulse LP is supplied from the switch 16, the counter 12 jumps to the given preset value P _V = “141” and the count value “14”.
Count continuously from "1" to "1227". That is, the counter 12 continuously counts from “0” to “128”, jumps by 12 clocks from “128”, and continuously counts from “141” to “1227”.

When the counter 12 counts up to "1727", the reset pulse RP is output from the pulse generator 11 at the fall of the horizontal synchronizing signal HR, as in the case of the 625 line system, and the counter 12 is It is reset by the reset pulse RP. In this way, the counter 12 repeats counting, and the address A
generate dr.

As described above, when the 525 system is specified, the address to which SAV is added is "28" in both systems because the jump is made from "128" to "141".
4 "to" 287 ".

Therefore, the address decoder Ad ₁ is
The address to which EAV is added, that is, the address Adr “0” from the counter 12 regardless of the specified method.
~ "3" is decoded and a timing signal is output to the process circuit Pr ₁ based on the decoded address. Further, the address decoder Ad ₂ also has an address to which SAV is added, that is, an address Adr “284” to “287” from the counter 12 regardless of the designated system.
And outputs a timing signal to the process circuit Pr ₂ based on the decoded address.

The process circuit Pr ₁ adds EAV to the input digital video data D _in based on the timing signal from the address decoder Ad _1, and supplies the input digital video data D _in with the EAV added to the process circuit Pr ₂ . To do. Further, the process circuit Pr ₂ receives the process circuit Pr ₁ based on the timing signal of the address decoder Ad _2.
SAV is added to the input digital video data D _in from.

As described above, the process circuits Pr ₁ and Pr ₂ add EAV and SAV to the input digital video data D _in .

Also, various timing signals other than the timing signals for adding the EAV and SAV described above are similarly generated by the address decoders Ad _{3 to} Ad _n regardless of the designated system, circuit Pr ₃ to PR _n, based on the timing signal generated by the address decoder Ad ₃ to AD _n, performs each format process.

Then, the input digital video data D _in subjected to the format processing by the process circuits Pr ₁ and Pr ₂ and the process circuits Pr _{3 to} Pr _n is output as output digital video data D _out . The output digital video data D _out is the SDII shown in FIG.
The data is supplied to a parallel / serial conversion circuit (not shown) provided in the subsequent stage of C2, and converted into serial data by the parallel / serial conversion circuit.

As described above, when the 525-line method is designated, the horizontal blanking period HB is 12 clocks, which is the difference in the number of samples between the 525-line method and the 625-line method.
By jumping only once in (1), it is possible to combine the timing generation units required for both equations into one timing generation unit 13. Therefore, the circuit scale of the timing generation circuit 1 can be reduced, and the power consumption and manufacturing cost of the circuit can be reduced.

In the above-described embodiment, the timing generation circuit is compatible with both the 525-line system and the 625-line system, but the number of samplings in one horizontal period is not limited to the 525-line system and the 625-line system. It can be applied to timing generation circuits corresponding to at least two different types of television systems.

[0053]

According to the timing generating circuit of the present invention,
The selecting means selects a format corresponding to the input digital video data from at least two formats. The counting means counts the maximum number of samples of at least one horizontal period of the input digital video data under the control of the skip count control means. The skip count control means controls the counting means based on the format selected by the selecting means so that the counting is skipped by an arbitrary number when counting the number of samples other than the effective video period of one horizontal period. The timing generating means detects the position to which the synchronizing signal is added based on the count value of the counting means and generates a timing signal based on the position. As a result, the count value corresponding to the position to which the synchronization signal is added becomes the same regardless of the format difference, and the timing generation means can be shared. Therefore, the circuit scale can be reduced, and the power consumption and manufacturing cost of the circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram for explaining input / output to / from a serial digital interface IC.

FIG. 2 is a circuit diagram showing a configuration of a timing generation circuit according to the present invention.

FIG. 3 is a timing chart when the 625-line method is designated in the timing generation circuit.

FIG. 4 is a timing chart when the 525 line system is designated in the timing generation circuit.

FIG. 5 is a circuit diagram showing a configuration of a conventional timing generation circuit.

FIG. 6 is a timing chart when the 525 line system is designated in the timing generation circuit.

FIG. 7 is a timing chart when the 625-line method is designated in the timing generation circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 timing generation circuit 11 pulse generation part 12 counter 13 timing generation part 14 format part 15 jump address decoder 16 switch Pr _{1 to} Pr _n process circuit Ad _{1 to} Ad _n address decoder

Claims (1)

[Claims] 1. A selecting means for selecting a format corresponding to input digital video data from at least two formats, a counting means for counting the maximum number of samples of at least one horizontal period of the input digital video data, and a selecting means for selecting by the selecting means. The skip count control means for controlling the counting means so that the counting is skipped by an arbitrary number when counting the number of samples other than the effective video period of one horizontal period based on the format, and the count value of the counting means. A timing generating means for detecting a position to which the synchronization signal is added and generating a timing signal based on the position, wherein the counting means skips and counts the number of samples under the control of the skip count control means. A characteristic timing generation circuit.