JPH0440078A - Pedestal level reproducing circuit - Google Patents

Abstract

PURPOSE:To prevent the fluctuation of a pedestal level and the flicker of an decoded picture from generating by selecting either the inputted pedestal level or the reproduced value of the pedestal level of one cycle before at the absolute value of their differential signal. CONSTITUTION:The central value of the pedestal level transmitted from the transmitting side is inputted from an input terminal 1 for one frame, and read by a register 2 by a frame pulse inputted from an input terminal 8 for one frame. The difference of the outputted value of the register 2 and a register 4 is taken by a subtracter 6 and inputted to a discriminating circuit 7. The discriminating circuit 7 outputs from a terminal 7 to a selecting circuit 3 a selection controlling signal which selects in the selecting circuit 3 the outputted signal of the register 4 when the differential signal of the register 2 and the register 4 outputted from this subtracter 6 is + or -1 or less, and the outputted signal of the register 2 when the differential signal is + or -2 or more. Thus, it is possible to prevent the fluctuation of the pedestal level generated by an error signal contained in the central value of the pedestal level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pedestal level reproducing circuit for reproducing and adding an invalid pixel portion of an image on the decoder side of a TV signal encoding device.

[Conventional technology]

In a TV signal encoding device, in order to reduce the amount of information, only the valid pixel part of the image is encoded, and the invalid pixel part whose waveform is determined in advance, such as the vertical synchronization signal and horizontal synchronization signal, is not encoded and is encoded during decoding. May be added for playback.

For example, when adding a horizontal synchronization signal, if it is an NTSC signal, the amplitude of the synchronization signal is 286 mV compared to the standard level signal of IVP-P, so the signal input to the encoding device is at the standard level. If there is, it is sufficient to add a horizontal synchronization signal with this amplitude, but in reality, the level of the input signal is not necessarily IVP-P. Therefore, the amplitude of the synchronization signal to be reproduced and added depends on the amplitude of the synchronization signal of the input signal. In order to change the synchronization signal, the transmitting side transmits a pedestal level corresponding to the amplitude value of the synchronizing signal to the receiving side as a representative value.

A conventional pedestal level reproduction circuit is configured to reproduce the pedestal level by directly using the representative value of the pedestal level that is transmitted once per frame of the screen.

[Problem to be solved by the invention]

In the conventional pedestal level reproduction circuit described above, the pedestal level is reproduced using the transmitted representative value as is, so depending on the noise component included in the signal and the accuracy of A/D conversion, at least the LSB 1 bit of the digital signal may be lost. This method has the disadvantage that a quantization error occurs, which causes the pedestal level added for reproduction to fluctuate, causing flicker in the decoded image.

[Means to solve the problem]

The pedestal level reproducing circuit of the present invention includes a first register that reads a pedestal level input as a digital value at a preset constant cycle, and an output signal of the first register and one cycle output from the second register. a selection circuit that selects either one of the previous pedestal level reproduction value; a second register that reads the output of the selection circuit in the same cycle as the first register and outputs it as the pedestal level reproduction value; a subtracter for calculating the difference between the output value of the register and the second register; and a determination circuit that controls selection of the selection circuit based on the determination result.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of the determination circuit of FIG. 1.

In FIG. 1, this embodiment has an input terminal 1 to which a pedestal level value of a TV signal is input as a digital signal;
A register 2 that reads the pedestal level input as a digital value at a preset constant cycle, and a selection circuit that selects either the output signal of the register 2 or the pedestal level reproduction value output from the register 4 one cycle before. 3
, a register 4 that reads the output of the selection circuit 3 at the same cycle as the register 2 and outputs it as a pedestal level reproduction value to the output terminal 5, a subtracter 6 that calculates the difference between the output values of the register 2 and the register 4, and a subtracter A determination circuit 7 determines whether the absolute value of the difference signal outputted from 6 is less than a certain predetermined value and controls the selection of the selection circuit 3 based on the determination result; The input terminal 8 is configured to include an input terminal 8 to which a frame pulse as a read clock is input.

Next, the operation of this embodiment will be explained.

From input terminal 1, the representative value of the pedestal level sent from the transmitting side is input for each frame, and from input terminal 8
Each frame is read into the register 2 by frame pulses input from the frame pulse. Subtractor 6 takes the difference between the output values of register 2 and register 4 and inputs it to judgment circuit 7. 6 Judgment circuit 7 takes the difference between the output values of register 2 and register 4 and outputs it from subtracter 6. If so, the selection circuit 3 selects the output signal of the register 4, and if it is ±2 or more, outputs a selection control signal from the terminal 7b to the selection circuit 3, which selects the output signal of the register 2. As a result, if the pedestal level input to the input terminal 1 has a small fluctuation of ±1 or less, the pedestal level value read into the register 4 is output from the output terminal 5 while being held. If the fluctuation of the pedestal level inputted to is large by ±2 or more, the fluctuated pedestal level value is output.

FIG. 2 is a block diagram showing an example of the determination circuit 7 in this embodiment. In this judgment circuit 7, the difference value inputted from the input terminal 7a is transmitted to a comparator 71 connected in parallel.
, a comparator 72 determines whether they are less than or equal to 2 or greater than or equal to 2, and if each is true, a high level is output, and if false, a low level is output. These logical values are outputted from the output terminal 7b via the OR gate 73.

Although the present embodiment shows a case where the pedestal level is reproduced on the receiving side, the representative value may be determined by the circuit of this embodiment when the transmitting side sends the representative value.

〔Effect of the invention〕

As explained above, the present invention includes a first register that reads a pedestal level input as a digital value at a preset constant cycle, and an output signal of the first register and a signal output from the second register one cycle before. a second register that reads the output of the selection circuit at the same cycle as the first register and outputs it as a pedestal level reproduction value;
A subtracter that calculates the difference between the output value of the register and the second register, and a subtracter that determines whether the absolute value of the difference signal output from the subtracter is less than a certain preset value, and based on the determination result. By having a determination circuit that performs selection control of the selection circuit, when a representative value of the pedestal level is transmitted to the input signal in the TV encoding device and the pedestal level is reproduced using the representative value on the receiving side,
This has the effect of preventing fluctuations in the pedestal level caused by error signals included in the representative value.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of the determination circuit of FIG. 1. DESCRIPTION OF SYMBOLS 1... Input terminal, 2... Register, 3... Selection circuit, 4... Register, 5... Output terminal, 6... Subtractor, 7... Judgment circuit, 8...・Input terminal, 7a...
- Judgment circuit input terminal, 7b... Judgment circuit output terminal, 71.
...Comparator, 72...Comparator, 73...OR gate.

Claims (1)

[Claims] A first register that reads the pedestal level input as a digital value at a preset constant cycle, and an output signal of the first register and a signal output from the second register.
a selection circuit that selects either one of the pedestal level reproduction value of the previous cycle; a second register that reads the output of the selection circuit in the same cycle as the first register and outputs it as the pedestal level reproduction value; a subtracter that calculates the difference between the output values of the first register and the second register; and a subtracter that determines whether the absolute value of the difference signal output from the subtracter is less than or equal to a certain predetermined value. A pedestal level reproducing circuit comprising: a determination circuit that controls selection of the selection circuit based on a determination result.