JP2910884B2 - Video equipment with two-screen display function - Google Patents
Video equipment with two-screen display functionInfo
- Publication number
- JP2910884B2 JP2910884B2 JP10423692A JP10423692A JP2910884B2 JP 2910884 B2 JP2910884 B2 JP 2910884B2 JP 10423692 A JP10423692 A JP 10423692A JP 10423692 A JP10423692 A JP 10423692A JP 2910884 B2 JP2910884 B2 JP 2910884B2
- Authority
- JP
- Japan
- Prior art keywords
- screen
- signal
- aspect ratio
- circuit
- child
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Description
【０００１】[0001]
【産業上の利用分野】本発明は２画面表示機能を備えた
映像機器に係り、特にワイドアスペクト画像を含む２画
面を親子両画面として同一画面上に表示するようにした
ワイドアスペクト対応のテレビジョン受像機やビデオテ
ープレコーダ等に用いられる２画面表示機能を備えた映
像機器に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video apparatus having a two-screen display function, and more particularly to a wide aspect television capable of displaying two screens including a wide aspect image on the same screen as both parent and child screens. The present invention relates to a video device having a two-screen display function used for a receiver, a video tape recorder, and the like.
【０００２】[0002]
【従来の技術】従来装置のブロック図を図８に示す。図
８において、１はアナログ信号処理部である。このアナ
ログ信号処理部１は入力端子Ｔ1より導入される第１の
入力映像信号ａと入力端子Ｔ2より導入される第２の入
力映像信号ｂを、親子画面の切換を指示する入力切換制
御部５からの制御信号によって切り換え、いずれか一方
を親画面用の信号として、また他方を子画面用の信号と
して取り出すスイッチング回路ＳＷ1と該スイッチング
回路ＳＷ1で選択された親画面用の信号と、後述する信
号処理が施された子画面用の信号とを合成するスイッチ
ング回路ＳＷ2より成る信号切換スイッチ部２と、上記
親画面用の信号より水平同期信号ＭＨＤと垂直同期信号
ＭＶＤを取り出す同期信号回路３と、上記子画面用の信
号よりクロマ復調を行い輝度信号Ｙと色差信号Ｂ−Ｙ，
Ｒ−Ｙを取り出すと共に、同期分離により水平同期信号
ＳＨＤと垂直同期信号ＳＶＤとを導出するクロマ・同期
処理回路４より成る。2. Description of the Related Art FIG. 8 shows a block diagram of a conventional apparatus. In FIG. 8, reference numeral 1 denotes an analog signal processing unit. The analog signal processing unit 1 converts the first input video signal a introduced from the input terminal T 1 and the second input video signal b introduced from the input terminal T 2 into an input switching control for instructing switching between parent and child screens. It switched by the control signals from the section 5, either as a signal for the main picture and the signal for the main picture selected by the switching circuit SW 1 and the switching circuit SW 1 to take out the other as a signal for the child screen , a signal changeover switch section 2 consisting of the switching circuit SW 2 for combining the signal for the child screen signal processing to be described later has been performed, synchronization from the signal for the main picture taking out a horizontal synchronizing signal MHD vertical synchronizing signal MVD Chroma demodulation is performed on the signal circuit 3 and the signal for the small screen, and the luminance signal Y and the color difference signals BY,
It comprises a chroma / synchronization processing circuit 4 for extracting RY and deriving a horizontal synchronization signal SHD and a vertical synchronization signal SVD by synchronization separation.
【０００３】１０はデジタル信号処理部であり、上記ク
ロマ・同期処理回路４からの輝度信号Ｙ，色差信号Ｂ−
Ｙ，Ｒ−Ｙをデジタル信号に変換するアナログ・デジタ
ル（以下Ａ／Ｄという）変換回路６と、該Ａ／Ｄ変換回
路６からのデジタル映像信号を上記同期分離回路３から
の水平及び垂直同期信号ＭＨＤ，ＭＶＤ及びクロマ・同
期処理回路４からの水平及び垂直同期信号ＳＨＤ，ＳＶ
Ｄにより制御して子画面の処理を行うと共に、親子両画
面の合成を行うため上記スイッチング回路ＳＷ2に制御
信号を導出するＰｉｎＰ（Ｐｉｃｔｕｒｅ ｉｎ Ｐｉ
ｃｔｕｒｅ）制御回路７と、該ＰｉｎＰ制御回路７の出
力をアナログ信号に変換するデジタル・アナログ（以下
Ｄ／Ａという）変換回路８より成る。[0003] Reference numeral 10 denotes a digital signal processing unit, which outputs a luminance signal Y and a color difference signal B-
An analog / digital (hereinafter, referred to as A / D) conversion circuit 6 for converting Y, RY into a digital signal, and a digital video signal from the A / D conversion circuit 6 for horizontal and vertical synchronization from the synchronization separation circuit 3 The signals MHD and MVD and the horizontal and vertical synchronization signals SHD and SV from the chroma / synchronization processing circuit 4
Performs processing of the child screen is controlled by D, and deriving a control signal to the switching circuit SW 2 for performing the synthesis of the parent-child both screens PinP (Picture in Pi
(Pure) control circuit 7 and a digital / analog (D / A) conversion circuit 8 for converting the output of the PinP control circuit 7 into an analog signal.
【０００４】従って、入力端子Ｔ1，Ｔ2より供給される
第１及び第２の入力映像信号ａ，ｂは入力切換制御部５
によりいずれか一方が親画面用の信号として、また他方
が子画面用の信号として同期処理回路３及びクロマ・同
期処理回路４に入力されると共に、親画面用の信号はス
イッチング回路ＳＷ2を介して出力端子Ｔ3より導出され
る。Therefore, the first and second input video signals a and b supplied from the input terminals T 1 and T 2 are supplied to the input switching control unit 5.
Either as the signal for the main picture, also with the other is input to the synchronous processing circuit 3 and the chroma synchronous processing circuit 4 as a signal for the child screen, the signal for the main picture through the switching circuit SW 2 by It is derived from the output terminal T 3 Te.
【０００５】一方、子画面用の映像信号はクロマ・同期
処理回路４で輝度信号Ｙと色差信号Ｂ−Ｙ，Ｒ−Ｙに復
調されＡ／Ｄ変換回路６でデジタル信号となってＰｉｎ
Ｐ制御回路７に供給される。ＰｉｎＰ制御回路７では上
記子画面内のデジタル映像信号を親画面の上記同期処理
回路３及び子画面の上記クロマ・同期処理回路４からの
水平・垂直同期信号ＭＨＤ，ＭＶＤ，ＳＨＤ，ＳＶＤに
より制御し、その出力をＶ−ＲＡＭ９に一旦書き込む。
このＶ−ＲＡＭ９に一旦書き込まれた子画面の信号は子
画面出力のタイミングに合わせて読み出し、Ｄ／Ａ変換
回路８でアナログ信号に変換して、上記スイッチング回
路ＳＷ2に入力し、ＰｉｎＰ制御回路７からの制御信号
でタイミングをとって親画面の一部に合成し、出力端子
Ｔ3より親子両画面を合成した合成映像信号を導出す
る。On the other hand, the video signal for the child screen is demodulated into a luminance signal Y and color difference signals BY and RY by a chroma / synchronization processing circuit 4 and is converted into a digital signal by an A / D conversion circuit 6 to be Pin.
It is supplied to the P control circuit 7. The PinP control circuit 7 controls the digital video signal in the small screen by the horizontal and vertical synchronization signals MHD, MVD, SHD, SVD from the synchronization processing circuit 3 of the main screen and the chroma / synchronization processing circuit 4 of the small screen. , And write the output to the V-RAM 9 once.
The once written child picture signal to V-RAM 9 is read in accordance with the timing of the child screen output, into an analog signal by the D / A conversion circuit 8, and input to the switching circuit SW 2, PinP control circuit synthesized part of the parent screen timed by a control signal from 7 derives the composite video signal obtained by synthesizing the parent-child both screens from an output terminal T 3.
【０００６】[0006]
【発明が解決しようとする課題】上記従来の装置におい
ては、子画面の表示サイズを自動的に制御するシステム
がないため例えば子画面の信号のアスペクト比が４：３
で子画面の表示サイズのアスペクト比が１６：９の場合
等、入力信号と子画面表示のアスペクト比が相違すると
使用者が操作を加えない限り、子画面の上下或いは左右
が切れたり、無信号部分が生じて表示品位が低下すると
いう問題があった。In the above-mentioned conventional apparatus, since there is no system for automatically controlling the display size of the sub-screen, for example, the aspect ratio of the signal of the sub-screen is 4: 3.
If the aspect ratio of the input signal differs from that of the sub-screen display, such as when the aspect ratio of the display size of the sub-screen is 16: 9, the upper and lower sides or left and right of the sub-screen may be cut off or no signal may be generated unless the user performs an operation. There is a problem that the display quality is degraded due to the occurrence of portions.
【０００７】[0007]
【課題を解決するための手段】本発明は上記の問題を解
決するため、ワイドアスペクト画面を含む２画面のいず
れか一方を縮小して子画面とし、この子画面を上記２画
面の他方の親画面内に同時に表示させるようにした２画
面表示機能を備えた映像機器において、上記子画面の輝
度信号を予め定めた複数領域よりランダムに抽出する輝
度信号抽出手段と、該輝度信号抽出手段より抽出した輝
度信号に基づき子画面のアスペクト比を判定するアスペ
クト比判定手段と、該アスペクト比判定手段の判定結果
に基づいて子画面の表示サイズを前記判定結果のアスペ
クト比に一致するように制御する子画面表示サイズ制御
手段とを設けた構成にする。According to the present invention, in order to solve the above-mentioned problem, one of two screens including a wide aspect screen is reduced to a small screen, and this small screen is used as the other parent of the two screens. In a video device having a two-screen display function for displaying images simultaneously on a screen, a luminance signal extracting means for randomly extracting the luminance signal of the child screen from a plurality of predetermined areas, and an extracting means for extracting the luminance signal from the plurality of predetermined areas. Aspect ratio determining means for determining the aspect ratio of the child screen based on the obtained luminance signal, and the determination result of the aspect ratio determining means
Asupe the display size of the child screen of the determination result based on
A configuration in which a and sub-screen display size control means for controlling so as to match the transfected ratio.
【０００８】[0008]
【作用】上記の構成によれば、子画面の輝度信号を輝度
信号抽出手段によって予め定めた複数の領域より抽出
し、この抽出した輝度信号を基にアスペクト比判定手段
で、子画面のアスペクト比を判定する。そして、この判
定結果に基づき子画面表示サイズ制御手段で子画面の表
示サイズを判定されたアスペクト比に一致するように制
御する。According to the above arrangement, the luminance signal of the child screen is extracted from a plurality of predetermined areas by the luminance signal extracting means, and the aspect ratio determining means determines the aspect ratio of the child screen based on the extracted luminance signal. Is determined. Then, based on the result of the determination, the display size of the small screen is controlled by the small screen display size control means so as to match the determined aspect ratio .
【０００９】[0009]
【実施例】図１は本発明の一実施例のブロック図であ
り、図８に示す上記従来装置に対応する部分は同一符号
を付し、説明を省略する。図１において、１６はデジタ
ル信号処理部であり、このデジタル信号処理部１６は上
記従来装置で説明したＡ／Ｄ変換回路６，Ｄ／Ａ変換回
路８，Ｖ−ＲＡＭ９及び後述する子画面表示サイズ制御
信号によってもコントロールされるＰｉｎＰ制御回路１
８と子画面表示サイズ制御システム部１７で構成する。FIG. 1 is a block diagram of an embodiment of the present invention. The portions corresponding to those of the conventional apparatus shown in FIG. In FIG. 1, reference numeral 16 denotes a digital signal processing unit. The digital signal processing unit 16 includes an A / D conversion circuit 6, a D / A conversion circuit 8, a V-RAM 9, and a small-screen display size to be described later. PinP control circuit 1 also controlled by control signal
8 and a small screen display size control system unit 17.
【００１０】上記子画面表示サイズ制御システム部１７
は上記Ａ／Ｄ変換回路６より供給される子画面の輝度信
号Ｙを、図２に示すような複数の予め定めた領域Ａ，
Ｂ，Ｃ，Ｄ、即ちアスペクト比が９：１６の中央部に位
置するワイドアスペクト画面の上方部（領域Ｂ）と下方
部（領域Ｃ）及びアスペクト比が４：３の画面とアスペ
クト比が１６：９のワイドアスペクト画面間の上方に位
置する領域Ｂと下方に位置する領域Ｄにおいて、ランダ
ムに同数づつ抽出する判定ポイント抽出回路１１と、該
判定ポイント抽出回路１１の出力により子画面のアスペ
クト比を判定するアスペクト判定回路１２と、アスペク
ト比判定回路１２の判定結果を一旦書き込むＲＡＭ１３
と該ＲＡＭ１３の内容に応じて子画面表示サイズを決定
する子画面表示サイズ決定回路１４と、この子画面表示
サイズ決定回路１４の出力信号に基づき、子画面表示サ
イズ制御信号を上記ＰｉｎＰ制御回路１８に供給する子
画面表示サイズ制御回路１５で構成する。The above-mentioned small screen display size control system section 17
Is used to convert the luminance signal Y of the child screen supplied from the A / D conversion circuit 6 into a plurality of predetermined areas A, as shown in FIG.
B, C, D, that is, the upper part (area B) and the lower part (area C) of the wide aspect screen located at the center of the aspect ratio of 9:16, the screen having the aspect ratio of 4: 3, and the aspect ratio of 16: : In a region B located above and a region D located below the wide aspect screen of 9: a determination point extraction circuit 11 for randomly extracting the same number of areas, and an aspect ratio of a child screen based on an output of the determination point extraction circuit 11 Determination circuit 12 and RAM 13 for temporarily writing the determination result of aspect ratio determination circuit 12
A small-screen display size determining circuit 14 for determining a small-screen display size in accordance with the contents of the RAM 13, and a small-screen display size control signal based on the output signal of the small-screen display size determining circuit 14. And a small-screen display size control circuit 15 that supplies the small-screen display size control circuit 15.
【００１１】従ってクロマ・同期処理回路４から導出さ
れる子画面の輝度信号Ｙ及び色差信号Ｂ−Ｙ，Ｒ−Ｙは
Ａ／Ｄ変換回路６でデジタル信号に変換された後、Ｐｉ
ｎＰ制御回路１８に導かれ一旦ＲＡＭ９に書き込まれ
る。ＲＡＭ９に書き込まれた子画面の映像信号は子画面
の出力タイミングに合わせて読み出される。Therefore, the luminance signal Y and the color difference signals BY and RY of the child screen derived from the chroma / synchronization processing circuit 4 are converted into digital signals by the A / D conversion circuit 6 and then Pi.
It is led to the nP control circuit 18 and is once written in the RAM 9. The video signal of the child screen written in the RAM 9 is read out in accordance with the output timing of the child screen.
【００１２】ＰｉｎＰ制御回路１８に供給させる同期処
理回路３及びクロマ・同期処理回路４からの水平・垂直
同期信号ＭＨＤ，ＭＶＤ，ＳＨＤ，ＳＶＤと子画面表示
サイズ制御回路１５からの子画面表示サイズ制御信号
は、Ｖ−ＲＡＭ９への子画面映像信号の書き込みタイミ
ングと、Ｖ−ＲＡＭ９より子画面の映像信号をＤ／Ａ変
換回路８に読み出す読み出しタイミングをとるために使
われている。即ちＰｉｎＰ制御回路１８における子画面
映像信号の書き込み及び読み出しタイミングを制御する
ことにより子画面の表示サイズを制御するようにしてい
る。The horizontal / vertical synchronization signals MHD, MVD, SHD, SVD from the synchronization processing circuit 3 and the chroma / synchronization processing circuit 4 to be supplied to the PinP control circuit 18 and the small screen display size control from the small screen display size control circuit 15 The signal is used for setting the timing of writing the small-screen video signal to the V-RAM 9 and the timing of reading the small-screen video signal from the V-RAM 9 to the D / A conversion circuit 8. That is, the display size of the small screen is controlled by controlling the timing of writing and reading the small screen video signal in the PinP control circuit 18.
【００１３】以下、子画面表示サイズ制御システム部１
７の動作を説明する。Ａ／Ｄ変換回路６より導出される
子画面の輝度信号Ｙは判定ポイント抽出回路１１に入力
され、図２に示す各領域Ａ，Ｂ，Ｃ，Ｄを測定ポイント
抽出エリアとして、図３のフローチャートに示すように
測定ポイントを抽出する。この場合、それぞれの領域
Ａ，Ｂ，Ｃ，Ｄで同数づつ複数個のポイントをランダム
に抽出する。Hereinafter, the small screen display size control system unit 1
7 will be described. The luminance signal Y of the child screen derived from the A / D conversion circuit 6 is input to the determination point extraction circuit 11, and the areas A, B, C, and D shown in FIG. The measurement points are extracted as shown in FIG. In this case, the same number of points are randomly extracted in each of the areas A, B, C, and D.
【００１４】そして、上記各測定ポイントにおける輝度
信号Ｙのレベルを測定し各領域毎に上記測定レベルの合
計値を求め、その値が予め定めた閾値以上であれば、
“１”若しくは“Ｈｉｇｈ”とし、そうでなければ
“０”若しくは“Ｌｏｗ”としてアスペクト比判定回路
１２に入力する。Then, the level of the luminance signal Y at each of the measurement points is measured, and the total value of the measurement levels is obtained for each area. If the value is equal to or larger than a predetermined threshold,
It is set to “1” or “High”; otherwise, it is input to the aspect ratio determination circuit 12 as “0” or “Low”.
【００１５】アスペクト比判定回路１２に入力された領
域Ａ，Ｂ，Ｃ，Ｄの各信号は、該アスペクト比判定回路
１２で図４に示す真理値表に従って、上方の領域Ａ，Ｂ
と下方の領域Ｄ，Ｃに関し、それぞれアスペクト比が１
６：９のワイドアスペクト画像である場合を示す“ＹＥ
Ｓ”とそうでない場合を示す“ＮＯ”といずれであるか
判断ができない状態を示す“判断できない”の３種合計
６種の出力を導出する。この状態は図３のフローチャー
トにおける“判断１”及び“判断２”に相当する。The signals of the areas A, B, C, and D input to the aspect ratio determination circuit 12 are converted by the aspect ratio determination circuit 12 according to the truth table shown in FIG.
And the lower areas D and C have an aspect ratio of 1
"YE" indicating a case of a 6: 9 wide aspect image
A total of six types of outputs are derived, namely, "S", "NO" indicating otherwise, and "Undetermined" indicating a state in which it cannot be determined, which is "determination 1" in the flowchart of FIG. And "judgment 2".
【００１６】上記“判断１”及び“判断２”の出力は図
３のフローチャートに示す“判断３”のステップに導か
れ、この“判断３”において図５の真理値表に基づきア
スペクト比が１６：９のワイドアスペクトの映像である
か否か、或いはいずれとも判断できないかを判定する。The outputs of the above "Judgment 1" and "Judgment 2" are led to the step of "Judgment 3" shown in the flowchart of FIG. 3, and in this "Judgment 3", the aspect ratio is 16 based on the truth table of FIG. : 9 to determine whether the image is a wide-aspect image or whether it cannot be determined anyway.
【００１７】即ち、図５の真理値表において入力信号ア
は図３のフローチャートにおける“判断１”の出力であ
り、入力信号イは図３のフローチャートにおける“判断
２”の出力であって両入力信号アとイが一致した場合、
即ち“ＹＥＳ”と“ＹＥＳ”，“ＮＯ”と“ＮＯ”及び
“判断できない”と“判断できない”の場合はその一致
した内容を出力する。つまり、“ＹＥＳ”の場合はアス
ペクト比が１６：９のワイドアスペクトの映像信号であ
ると判断し、“ＮＯ”の場合はそれ以外の映像信号であ
ると判断し、“判断できない”の場合はいずれのアスペ
クト比の映像信号か判らないと判断する。That is, in the truth table of FIG. 5, the input signal A is the output of "decision 1" in the flowchart of FIG. 3, and the input signal A is the output of "decision 2" in the flowchart of FIG. If signal A and A match,
That is, in the case of "YES" and "YES", "NO" and "NO", and "cannot determine" and "cannot determine", the matching contents are output. That is, in the case of "YES", it is determined that the video signal is a wide aspect video signal having an aspect ratio of 16: 9, in the case of "NO", it is determined that the video signal is another video signal, and in the case of "cannot be determined", It is determined that the video signal of any aspect ratio is not known.
【００１８】また上記両入力信号アとイが不一致の場合
は“判断できない”と判定する。“判断３”における上
記３種の出力“ＹＥＳ”（アスペクト比が１６：９のワ
イドアスペクトの映像信号であることを示す）と、“Ｎ
Ｏ”（アスペクト比が４：３等１６：９以外のアスペク
ト比の映像信号であることを示す信号）と、“判断でき
ない”（どのアスペクト比の映像信号か判断できないこ
とを示す信号）はアスペクト比判定回路１２の出力とし
て導出され、次段のＲＡＭ１３に一旦記憶される。この
ように子画面のアスペクト比を子画面の所定の領域にお
ける輝度信号のレベルで判別する。If the two input signals A and A do not match, it is determined that "cannot be determined". The three types of output “YES” in “decision 3” (indicating that the video signal is a wide aspect video signal having an aspect ratio of 16: 9) and “N”
"O" (a signal indicating that the video signal has an aspect ratio other than 16: 9, such as 4: 3) and "cannot be determined" (a signal indicating that the video signal cannot be determined as to which aspect ratio) are the aspect ratios. It is derived as an output of the ratio determination circuit 12, and is temporarily stored in the next-stage RAM 13. In this way, the aspect ratio of the child screen is determined based on the level of the luminance signal in a predetermined area of the child screen.
【００１９】上記アスペクト比判定回路１２の判定結果
を用いて誤認識が少なく、且つ認識スピードを上げて子
画面表示サイズを決定する方法について、図６及び図７
に示すフローチャートを用いて説明する。上記アスペク
ト比判定回路１２の判定結果はＲＡＭ１３に一旦書き込
まれているので、該ＲＡＭ１３より時刻ｔ＋Δｔ1から
ｔ＋Δｔmまでに記憶されたｍ個のデータを読み出し、
これを次段の子画面表示サイズ決定回路１４に入力す
る。このｍ個のデータは図６（ａ）に示すように、例え
ば子画面のアスペクト比が１６：９のとき“Ｈｉｇ
ｈ”，アスペクト比が４：３のとき“Ｌｏｗ”，アスペ
クト比が判別できないとき“Ｍｉｄｄｌｅ”の信号とな
る。FIGS. 6 and 7 show a method of determining a small-screen display size by reducing the number of erroneous recognitions and increasing the recognition speed using the determination result of the aspect ratio determination circuit 12.
This will be described with reference to the flowchart shown in FIG. Since the determination result of the aspect ratio determination circuit 12 it is written once in RAM 13, reads out the m pieces of data stored in the time t + Delta] t 1 from the RAM 13 to t + Delta] t m,
This is input to the sub-screen display size determination circuit 14 at the next stage. As shown in FIG. 6A, when the aspect ratio of the child screen is 16: 9, the m pieces of data are “Hig
h "," Low "when the aspect ratio is 4: 3, and" Middle "when the aspect ratio cannot be determined.
【００２０】このように子画面のアスペクト比を或る一
点の時刻で判断するのではなく、一定の期間に生ずるｍ
個の信号を用いて判断するようにしているので誤認識が
少なくなり、判定の精度を向上させることができる。As described above, instead of determining the aspect ratio of the sub-screen at a certain point in time, m which occurs in a certain period is determined.
Since the determination is made using the individual signals, erroneous recognition is reduced, and the accuracy of the determination can be improved.
【００２１】次に上記ＲＡＭ１３より取り出されたｍ個
のデータに図６（ｂ）に示すような重み付けを行い、図
６（ｃ）に示すような重み付けの行われたデータを取り
出す。そして、この重み付けが行われたｍ個のデータの
和をとり、その合計の値が予め定めた閾値と比較して該
閾値以上であれば子画面のアスペクト比が１６：９であ
ると判断し、上記閾値以下であれば子画面のアスペクト
比が４：３であると判断する。Next, the m data extracted from the RAM 13 are weighted as shown in FIG. 6B, and the weighted data as shown in FIG. 6C is extracted. Then, the sum of the m pieces of weighted data is calculated, and the sum is compared with a predetermined threshold. If the sum is equal to or larger than the threshold, it is determined that the aspect ratio of the child screen is 16: 9. If the ratio is equal to or smaller than the above threshold value, it is determined that the aspect ratio of the child screen is 4: 3.
【００２２】上記の重み付けは時刻に比例するので、ア
スペクト比の判断をより速く行うことができる。その結
果は子画面表示サイズ決定回路１４より子画面表示サイ
ズ制御回路１５に入力され、子画面のアスペクト比に合
わせて子画面の出力タイミングを制御する子画面表示サ
イズ制御信号を上記ＰｉｎＰ制御回路１８に供給する。
その結果、ＰｉｎＰ制御回路１８より子画面の出力タイ
ミングに合わせてＶ−ＲＡＭ９より子画面の映像信号が
出力され、Ｄ／Ａ変換回路８でアナログ信号に変換され
た後、上記スイッチング回路ＳＷ2に供給され、Ｐｉｎ
Ｐ制御回路１８からの制御信号でタイミングをとって親
画面の一部に合成し、出力端子Ｔ3より親子両画面を合
成した２画面合成映像信号を導出する。Since the weighting is proportional to the time, the aspect ratio can be determined more quickly. The result is input from the sub-screen display size determination circuit 14 to the sub-screen display size control circuit 15, and the sub-screen display size control signal for controlling the output timing of the sub-screen according to the aspect ratio of the sub-screen is transmitted to the PinP control circuit 18. To supply.
As a result, the output V-RAM 9 Yoriko screen video signal in accordance with the output timing of the PinP control circuit 18 Yoriko screen, converted to an analog signal by the D / A conversion circuit 8, to the switching circuit SW 2 Supplied, Pin
Synthesized part of the parent screen timed by a control signal from P control circuit 18 derives two screen combining video signal obtained by synthesizing the parent-child both screens from an output terminal T 3.
【００２３】[0023]
【発明の効果】本発明は上記の構成であるので、子画面
とする入力映像信号のアスペクト比に表示しようとする
画面のアスペクト比を常時自動的に一致させることがで
き、表示される子画面の上下部が欠けたり、また無信号
部が生じる等の問題がなく子画面を見やすくすることが
できると共に、上記アスペクト比を一致させる操作を使
用者が行う必要がないので機器の操作性を向上させるこ
とができる。Since the present invention has the above configuration, the aspect ratio of the screen to be displayed can always be automatically made to match the aspect ratio of the input video signal to be the child screen, and the displayed child screen It is possible to make the child screen easier to see without any problems such as the lack of upper and lower parts and no signal part, and the operability of the device is improved because the user does not need to perform the operation of matching the aspect ratio. Can be done.
【図１】 本発明の一実施例のブロック図。FIG. 1 is a block diagram of one embodiment of the present invention.
【図２】 本発明における測定ポイントの抽出領域の説
明図。FIG. 2 is an explanatory diagram of a measurement point extraction region according to the present invention.
【図３】 本発明の要部の動作を説明するためのフロー
チャート。FIG. 3 is a flowchart for explaining an operation of a main part of the present invention.
【図４】 本発明の動作説明のための真理値を示す図。FIG. 4 is a diagram showing truth values for explaining the operation of the present invention.
【図５】 本発明の動作説明のための真理値を示す図。FIG. 5 is a diagram showing truth values for explaining the operation of the present invention.
【図６】 本発明における信号処理の説明図。FIG. 6 is an explanatory diagram of signal processing in the present invention.
【図７】 本発明における信号処理のフローチャート。FIG. 7 is a flowchart of signal processing according to the present invention.
【図８】 従来例のブロック図。FIG. 8 is a block diagram of a conventional example.
１１ 判定ポイント抽出回路 １２ アスペクト比判定回路 １３ ＲＡＭ １４ 子画面表示サイズ決定回路 １５ 子画面表示サイズ制御回路 １８ ＰｉｎＰ制御回路 DESCRIPTION OF SYMBOLS 11 Judgment point extraction circuit 12 Aspect ratio judgment circuit 13 RAM 14 Small screen display size determination circuit 15 Small screen display size control circuit 18 PinP control circuit
Claims (1)
れか一方を縮小して子画面とし、この子画面を上記２画
面の他方の親画面内に同時に表示させるようにした２画
面表示機能を備えた映像機器において、上記子画面の輝
度信号を予め定めた複数領域よりランダムに抽出する輝
度信号抽出手段と、該輝度信号抽出手段より抽出した輝
度信号に基づき子画面のアスペクト比を判定するアスペ
クト比判定手段と、該アスペクト比判定手段の判定結果
に基づいて子画面の表示サイズを前記判定結果のアスペ
クト比に一致するように制御する子画面表示サイズ制御
手段とを設けたことを特徴とする２画面表示機能を備え
た映像機器。A two-screen display function is provided in which one of two screens including a wide aspect screen is reduced to a sub-screen, and the sub-screen is simultaneously displayed in the other main screen of the two screens. A luminance signal extracting means for randomly extracting a luminance signal of the child screen from a plurality of predetermined areas, and an aspect ratio for determining an aspect ratio of the child screen based on the luminance signal extracted by the luminance signal extracting means. Determining means and a determination result of the aspect ratio determining means
Asupe the display size of the child screen of the determination result based on
And a small-screen display size control means for controlling the screen size to match the video ratio .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10423692A JP2910884B2 (en) | 1992-04-23 | 1992-04-23 | Video equipment with two-screen display function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10423692A JP2910884B2 (en) | 1992-04-23 | 1992-04-23 | Video equipment with two-screen display function |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05300447A JPH05300447A (en) | 1993-11-12 |
| JP2910884B2 true JP2910884B2 (en) | 1999-06-23 |
Family
ID=14375333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10423692A Expired - Fee Related JP2910884B2 (en) | 1992-04-23 | 1992-04-23 | Video equipment with two-screen display function |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2910884B2 (en) |
-
1992
- 1992-04-23 JP JP10423692A patent/JP2910884B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05300447A (en) | 1993-11-12 |
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