JPS6143080A - Display and control system of television mirror image - Google Patents

Abstract

PURPOSE:To invert the right and left in terms of screen display of a video signal and to display easily a mirror image by specifying an address of one line in the order reverse to the writing at the time of reading out contents of a buffer memory part. CONSTITUTION:An inputted composite video signal is converted into a digital signal by an A/D converter 10, and luminance and chrominance signals are separated from said video signal by a digital luminance signal/chrominance signal separator 11. Outputs of a chrominance signal two-line buffer memory part 17 and a luminance signal two-line buffer memory part 18 are converted into three primary chrominance signals R, G, and B in a matrix part 19, and further converted into analog signals by a D/A converter 20. A memory control part 21 controls reading and writing to a luminance signal main memory 15, a chrominance signal main memory 16 and the memory parts 17 and 18, and specifies an address. When a mirror image display mode is selected, the control part 21 specifies the address in order to read reversely contents of the memory parts 17 and 18.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Description of the field to which the invention pertains The present invention relates to a television mirror image display control system, particularly a mirror image display system that displays a mirror image by reversing the left and right sides of the screen and reading and displaying the image. This relates to a display control method.

(2) Description of conventional technology Conventionally, as a device that displays a screen by reversing the left and right sides of the screen,
This has been achieved by reversing the direction of the horizontal deflection current flowing through the horizontal deflection coil of a television, thereby changing the direction of horizontal scanning. 1 is a block diagram showing an example of this conventional device, in which 1 is a luminance/chrominance signal separation section, 2.3 is a chrominance signal demodulation section, 4 is a matrix section, 5 is a horizontal/vertical synchronization separation section, and 6 is a block diagram showing an example of this conventional device. is a horizontal deflection section, 7 is a vertical deflection section, 8 is a CRT,
9 is a mirror image display control section.

Next, the operation of this prior art will be explained. In the figure, the input decoded video signal is separated into a brightness signal and a color signal by a brightness/color signal separation unit 1, and the separated color signals are sent to a color signal demodulation unit 2.3 as color difference signals R-Y, B. −Y is demodulated. Further, the separated luminance signal Y is combined with the color difference signals RY and B'-Y in the matrix section 4 to output three primary color signals R, G, and B. On the other hand, a horizontal/vertical synchronization separator 5 separates the horizontal and vertical synchronization signals of the decoded video signal.
Generates horizontal and vertical deflection voltages. The horizontal and vertical deflection voltages are input to the horizontal and vertical deflection coils of the CRT8, and
The three primary color signals R, G, and B output from the matrix section 4 are input to the R, G, and β input terminals of the CRT 8, and are displayed on the screen of the CRT 8 according to the deflection current. When the mirror image display mode is selected, the mirror image display control section 9 performs reversal control of the horizontal deflection current, the direction of the horizontal deflection current is reversed, the direction of horizontal scanning is reversed, and a mirror image is displayed.

By the way, in order to reverse the direction of the horizontal deflection current while the television is operating, the resistance of the reversing switch and the resistance of the horizontal deflection output circuit are required, and during switching, other circuits may be adversely affected. In addition, in order to avoid sudden changes in the screen, it is also necessary to control the horizontal deflection current, which has the disadvantage of complicating the configuration.

(3) Purpose of the Invention The present invention uses a digital memory to reversely read out the contents of the memory to display a mirror image, and aims to easily enable mirror image display by introducing digital technology.

(4) Description of structure and operation of the invention The present invention will be described in detail below with reference to the drawings. Figure 2 shows
1 is a block diagram showing an embodiment of a mirror image display television according to the present invention, and the tickets corresponding to those in FIG. 1 are given the same reference numerals and the explanation thereof will be omitted.

In the figure, 10 is an A/D converter, 11 is a digital luminance/chrominance signal separation section, 12.13 is a digital chrominance signal demodulation section (separation section), 14 is a multiplexer section, and 15 is a luminance signal main memory section. , 16 is a color signal main memory section, 17 is a luminance signal 2-line haphazard memory section, 18 is a chrominance signal 2-line buffer memory section, 19 is a matrix section,
20 is a D/A converter, and 21 is a memory control section.

The input decoded video signal is converted into a digital signal by an A/D converter 10, and then converted into a digital signal by a digital luminance/chrominance signal separator 11.
is separated into luminance and color signals. The separated color signal is converted into a color difference signal R by a digital color signal demodulator 12.13.
-'Y, B-Y, which are switched by the multiplexer section 14 and input to the color signal main memory section 26 and the color signal 2-line buffer memory section 18. Further, the separated luminance signal Y is input to the luminance signal main memory section 15 and the luminance signal 2-line buffer memory section 17.

Color and luminance signal 2-line buffer memory section 17.18
The output is converted into three primary color signals R1G and H by the matrix section 19, and converted into an analog signal by the D/A converter 20. The memory control section 21 includes a main memory section 15.16.2 for luminance and color signals, and a line buffer memory section 17.1.
Write to 8, read control, address instructions, etc. , when the mirror image display mode is selected, the memory control unit 2
1, luminance and color signal 2 line buffer memory section 1
The address for reading out the contents of 7 and -18 in reverse is specified. FIG. 3 shows the relationship between time and address for writing and reading Panzer memory. Writing is performed in the order shown in FIG. 3(a), and the contents of the panzer memory section are read out in the reverse order in the order shown by the dotted line in FIG. 3(b) to display a mirror image.

Further, in order to smoothly convert a normal image to a mirror image, control shown in FIG. 4 is performed. However, for the sake of brevity in this figure, it is assumed that the number of samples in one line is 10, and addresses from θ to 9 are sequentially given. When the mirror image mode is selected, the readout start address is increased by 1 address and the readout end address is decreased by 1 address for each frame from the state where the normal side is displayed.
Decrease the display range frame by frame. After that, when the display becomes blank, the mirror image will be displayed from the next frame.
Read the address 4.5 in the center of the screen in reverse. Subsequently, contrary to the above, the read start address is decreased by one address for each frame, and the read end address is increased by one address, thereby increasing the display range for each frame. decrease,
Alternatively, the number of addresses to be increased is determined by the time required for conversion.

(5) Description of Effects As explained above, according to the present invention, instead of displaying a mirror image in analog by modifying the deflection circuit as in the prior art, a digital memory is used and its contents are reversely displayed. Since this is achieved by reading out data from the image memory, it can be easily applied to digital televisions that have image memory. Also,
Natural switching from a normal screen to a mirror image screen is also easily possible by changing the number of pixels read from the two-line buffer memory.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a conventional television with a mirror image display function, Fig. 2 is a block diagram showing an example of a digital television with a mirror image display function, and Fig. 3 is a block diagram showing an example of a digital television with a mirror image display function. FIG. 4 is a diagram showing the relationship between time and address, and FIG. 4 is a schematic diagram showing the read address of the memory when moving from the normal side to the mirror image side. 5...Horizontal and vertical synchronization separation section, 6...Horizontal deflection section,
7... Vertical deflection section, 8... CRT, 9... Mirror image display control section, 10... A/D converter, 11... Digital luminance, color signal separation section, 12... 13...・Digital color signal demodulation section, 14...Multiplexer section, 15...
- Luminance signal main memory section, 16... Color signal main memory section, 17... Luminance signal 2-line buffer memory section, 18... Color signal 2-line expansion memory section, 19.
...Matrix section, 20...D/A converter, 21...
・Memory control unit.

Claims (2)

[Claims] (1) An A/D converter that digitizes the composite video signal, a luminance/color signal separator that separates the luminance signal and color signal of the digitized composite video signal, and the separated luminance signal and color signal. a main memory section that stores signals, a buffer memory section, a memory control section that controls writing and reading of the main memory section and the buffer memory section and instructs a writing/reading address, and the buffer memory section. a matrix section that synthesizes the luminance signal and color signal read from the matrix section to generate three primary color signals, and a D/A converter that converts the three primary color digital signals outputted from the matrix section into analogs, When reading the contents of the buffer memory section, the memory control section instructs an address for one line in an order opposite to the writing order, thereby inverting the left and right sides of the screen display of the video signal and displaying it. 1. A television mirror image display control method, comprising: means. (2) When converting from a normal screen to a mirror image screen, the memory control unit sequentially decreases the number of pixels read in the buffer memory section in the forward direction corresponding to the frame, and the number of pixels read in the reverse direction is changed to the frame. A television mirror image display control system as claimed in claim 1, further comprising means for correspondingly increasing the number in sequence.