JPH0515348B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a two-screen television receiver capable of inserting another video screen into a part of the video on the screen.

Prior Art First, a conceptual diagram of a two-screen television is shown in FIG.
This is an example in which a child screen 302 is combined with a main screen 301.

The two main basic functions of a two-screen TV are as follows.

(a) The synchronization of the synthesized image and the image to be synthesized is unrelated to each other, that is, the phase and frequency are different, so the time axis must be adjusted so that the synchronization of the synthesized image matches the synchronization of the image to be synthesized (in the case of CRT, the deflection synchronization signal). Function to do.

(b) A function to reduce the composite screen from its original size during screen composition.

There is a conventional example in which such a function is implemented using a buffer memory and a one-field memory.

To explain this example, first, the relationship between the two-screen television circuit section and the peripheral circuits will be explained with reference to FIG. The input video switching circuit section 201 selects and switches between the parent (to be combined) video and the child (combined) video. Its input can be, for example, multiple tuners.
VIF circuits 202, 203 and other video equipment 204
(for example, VCR, disk, camera, etc.), one of which is sent to the main video processing circuit 2.
05 and the parent synchronization separation circuit section 206, and another 1
One is supplied to the child video processing circuit section 207 and the child synchronization separation circuit section 208.

In the two-screen TV circuit section 1, the child video processing circuit 2
Basically, the video signal 2 from 07 is written once into the memory with the synchronization signal 3 from the child synchronization separation circuit section 208, and the synchronization signal 4 from the parent synchronization separation circuit section 206 is written once.
By reading from the memory at , the video signal 5 for synthesis is output. This video signal 5 is combined with the parent video from the parent video processing circuit 205 by the output signal switching unit 209 and output to the CRT 210 which is deflected by the synchronization signal from the parent synchronization separation circuit 206 .

FIG. 6 is a block diagram of a conventional example of the two-screen television circuit section 1, focusing on the flow of signals. 2 and 5 correspond to Figure 2, respectively.
This is a child video signal input and a video signal output for compositing.
401 is a buffer memory for horizontal scanning; 402
is a one-field memory that can be read and written in every horizontal period (hereinafter abbreviated as H).

The main basic function 2 of a two-screen TV was mentioned above, but in terms of circuit design, it is not possible to write and read from memory at the same time when aligning the time axes of the parent and child, so how to organize the time relationship. becomes the point.

A case in which the size of the child screen 302 is 1/3 both vertically and horizontally of the main screen 301 will be described with reference to the timing diagram of FIG. 7. First, as shown in FIG. 7a, data is written into the buffer memory 401 in accordance with the child H signal. However, to make it 1/3 vertically, you only need to write 1H in 3H. Since the buffer memory 401 has a capacity of only 1H, the data is sent to the field memory 402, which is the main memory, before the next write (that is, data is read from the buffer memory 401, and the data is sent to the field memory 402, which is the main memory).
) is necessary. The timing is a period when the buffer memory 401 is not performing a write operation and the field memory 402 is not performing a read operation.

The field memory 402 is as shown in FIG. 5c.
During the period when the child screen 302 is output on the screen, reading is performed every H period in accordance with the parent's H signal. However, in order to compress the data to 1/3 in the horizontal direction, the data is read out at approximately three times the speed of writing to the field memory 402. While the child screen 302 is being output, there is little room in the field memory 402, but if
If the writing period of the buffer memory 401 in Figure a is set to 3/4 or less of the H period of the child, the reading period of the field memory 402 in Figure 7c will be approximately 1/3 or 1/4 H period as described above. , field memory 4
There is a margin of about 3/4H between the readings of 02 and 02. In other words, data in the buffer memory 401 can be sent to the field memory 402 using this time.

Problems to be Solved by the Invention However, the above conventional example has the following two problems.

(1) There is a problem that information around the screen cannot be displayed on the child screen 302. Ideally, the main screen 301
I want to make the information display areas of the child screen 302 and the child screen 302 the same.
Considering the sample period within H of the necessary small screen information at that time, the period during which the information actually exists in the horizontal period is about 0.835H period. If 90% of that is displayed on the screen due to the characteristics of the TV receiver, then 0.835H x 0.9 = 0.75H
becomes. Even with the conventional method, if the absolute values of the H period of the parent and child are equal, there is no problem because data of 3/4 of the child's H period can be handled. However, in reality, depending on the operation of the video equipment 204 that is the video signal source for the sub-screen, the normal H period, that is, approximately
Since there is a difference from 63.5 μsec, even when the child's H period is longer than the parent's H period, the field memory 402 explained in FIG.
In order to maintain the relationship between reading and writing, the sampling period within H for child screen information must be designed to be considerably shorter than the 0.75H period. For this reason, the information on the left and right sides of the screen is cut off, especially when
This is a major inconvenience when there is text information in the cut area.

(2) Field memory 402 which is main memory
As such, a fast readout speed is required.

This is because compression in the H direction is performed at the stage of reading from the main memory, as shown in FIG. 7c. High-speed main memory is expensive, so
In order to reduce capacity, instead of storing one frame of data, the memory is half that amount, one frame. However, this is child screen 30
2, the image quality deteriorates significantly when the still image is displayed. That is, when shooting a moving image, there is no problem since the contents of the main memory are always updated, but when shooting a still image, that is, when data writing to the main memory is stopped and the contents of the field memory 402 are repeatedly read, Since the contents of the even field and the odd field are equal, the vertical resolution is halved. There is an inconvenience that if you try to write down certain text information as a still image, you will be told that it cannot be read.

Means for Solving the Problems In the two-screen TV receiver of the present invention, the video signal input for synthesis is first input to a one-field memory that can be read and written for each pixel, and then read and written for each horizontal period. The video signal is output as a video signal to be combined with the video signal to be combined via two sets of writable buffer memories for the horizontal period.

Effect Regarding problem (1) mentioned above, buffer memory 2
This is used to read and write sets alternately, and the sub-screen H
In principle, all data within a period can be imported, and peripheral information on the screen will not be cut off.

Regarding problem (2), data compression in the H direction is not performed in the 1-frame memory, which is the main memory, but is performed in the later buffer memory, so the operating speed of the main memory can be reduced. . In other words, an inexpensive main memory can be used. Buffer memory has a simple operation and a small capacity, so its proportion in cost is small. In the end, even if the main memory capacity is increased to one frame, which is twice the capacity of one field, the cost of the entire system can be lower than that of the conventional method. Furthermore, since the main memory has one frame's worth, there is no deterioration in image quality when a still image is taken.

Embodiment Hereinafter, a screen television receiver according to an embodiment of the present invention will be described with reference to FIG. This diagram is
This corresponds to the two-screen television circuit section 1 in FIG.

The child video signal is inputted from 2 and inputted to a frame memory 101 that can be read and written pixel by pixel.
The output is transmitted from the buffer memory A 102 to the buffer memory B 103, which can be read and written every horizontal period, via the buffer memory input switching circuit section 104. The buffer memory output is output as a composite video signal through the buffer memory output switching circuit section 105.

Writing to the frame memory 101 is controlled by a clock generation circuit section (1) 106, and reading from it is controlled by a clock generation circuit section (2) 107.
The former control output is referred to as a first clock 110, and the latter control output is referred to as a second clock 111. Writing to the buffer memories 102 and 103 is performed using the second clock 111, and reading is performed using the third clock 11 which is the output of the clock generation circuit section (3) 108.
2. The buffer memory read end detection circuit 109 counts the third clock 112 and generates an output 113 when it detects the end of the buffer memory read. The buffer memory input switching unit 104 alternately switches the flow of data to the buffer memory A 102 or the buffer memory B 103 each time this read end detection output 113 is input. The buffer memory output switching circuit section 105 alternately outputs the buffer memory A1 according to the parent H signal input 4.
02 or the data from the buffer memory B103 is output as a video signal for synthesis.

Next, the operation when the size of the child screen 302 is 1/3 both vertically and horizontally of the main screen 301 is as follows.
This will be explained with reference to FIGS. 4 and 5.

FIG. 6a is an output timing diagram of the first clock 110. This indicates that writing to the frame memory 101 is being performed within the range of the child H signal. I only wrote once in the 3H period.
This is because the vertical direction is reduced to 1/3, so it is thinned out.
Since the first clock 110 samples the child video signal 2, it is required to be synchronized with the child H signal 3. A clock having a period corresponding to the number of samples is output during the period shown in FIG. 4a.

On the other hand, the third clock 112 that controls reading of the buffer memories 102 and 103 needs to be synchronized with the parent H signal 4 and is output within the range of the parent H signal 4. Sub-screen 3 on the left side of the screen
02, the third clock 112 is output at the left end of the parent H signal 4 as shown in FIG. 4f. The output period is the first clock 11
1 is compressed to 1/3 of the writing period of the frame memory 101 by 1. That is, in principle, the period of the third clock 112, which is a read clock, is 1/3 that of the first clock 110, which is a write clock.

The read end detection circuit section 109 outputs an output 113 as shown in FIG. 6e. This is input to the clock generation circuit section (2) 107 at the same time as controlling the buffer memory input switching section 104 as described above, and causes the second clock 111 to start outputting. The output period is shown in FIG. 4b.

First clock 110 and second clock 111
The relationship will be explained with reference to FIGS. 5g and 5h, which are enlarged views of the periods P in FIGS. 4a and 4b. As shown in the figure, a first clock 110 and a second clock 11
The periods of 1 are equal to Q, and the phases differ by 180 degrees.
Then, in the first half of the period Q, the frame memory 101
The write operation is performed in the second half, and the read operation is performed in the second half.
Each shall do so. That is, since reading and writing of the frame memory 101 are performed alternately, the fourth
There is no problem even if the output period of the first clock 110 and the output period of the second clock 111 overlap as shown in FIGS. a and b. e read end detection output 113
Reads 1H worth of data from the point at which it hits.

The read data is stored in the buffer memory 102,1.
03 alternately. This situation is shown in Figure 4c and d.
Shown below. The read period of buffer memories 102 and 103 is limited to f. The basic idea is to rewrite the data in the buffer memory of the person who has finished reading. Therefore, writing continues to the same buffer memory that was being read before the read end detection output 113 is output. The switching timing of the buffer memory output switching circuit section 105 is such that the read period of the buffer memory always falls within the parent's H signal.
Switch at signal 4. If the switching timing of the buffer memory input switching circuit section 104 is set to the read detection output 113, the margin can be maximized when the period of the parent H signal 4 becomes relatively small with respect to the child H signal 3. .

Effects of the Invention According to the two-screen television receiver of the present invention, since a frame memory that can be read and written for each pixel is used, when viewed in units of H signals, writing is performed on child H signals.
The readout signal can be adjusted to the parent H signal, respectively.

The post buffer memory performs synchronization at the pixel level and compresses the data output period in the H direction.
The effects will be described in relation to the two problems mentioned in the section of problems to be solved by the invention.

(1) Regarding the peripheral cut-off of sub-screen information.

In the circuit of the present invention, the write period of the small screen signal is limited when the read periods of adjacent H periods of the frame memory overlap. If the child's H period and the parent's H period are equal, it is possible to write all the data in the H period. As the period of the parent's H period becomes smaller relative to the child's H period, the writable period becomes shorter, but the write period is set to 0.75H by the above calculation.
In this case, there is a margin of relative error of 25% per 1H period, which is sufficient. Therefore, peripheral cut-off of child screen information does not occur. According to this circuit, the reading period of the child screen information can be varied up to a ratio of 1:1 with the writing period. Therefore, the size of the child screen can be arbitrarily set up to the maximum size of the parent screen, and is not limited to 1/3 vertical x 1/3 horizontal as used in the explanation.

(2) Regarding the issue of main memory read/write speed.

A comparison will be made between the conventional example and the present invention. It is assumed that the output period in the H direction of the child screen is Th, the number of pixels (number of samples) per 1H is n, and the cycle of reading and writing to the memory is equal to Tc. In the conventional example, Th
The highest speed is when n pieces of data are read during this period, and Tc=Th/n.

In the present invention, reading the frame memory,
The speed is highest when the write periods overlap, and n pieces of data are read and n pieces of data are written in a period of 3 x Th, so Tc = (3 x Th) / (n x 2)=(1.5×Th)/
It becomes n. In other words, the main memory of the present invention is
You can use something that is 1.5 times slower than the conventional example. Here, by substituting a specific value, Th is 0.75H, and Th is 0.75H.
It is 1/3 of that. Although n is a pixel, it is not considered as an actual pixel on the screen, but as a unit of data input/output to the memory.

When storing color video signals in memory, it is common to separate them into luminance and color difference signals in order to reduce memory capacity, and the sampling rate of each should be reduced to 4:1 for such purposes. It is normal to do so. Therefore, in order to match the speed of luminance and color difference data, data is synthesized before being stored in memory. The number of unit data per H at this point is considered to be n. It is advisable to select 2 to the nth power in terms of memory configuration, and in consideration of image quality, n=64. In this way, Tc of the conventional example
is 248n sec, and Tc of the present invention is 37n sec.

The reason why this difference has a large effect on cost is due to the following circumstances. There are two general types of digital RAM: static RAM and dynamic RAM. The former is fast and the latter is slow, and with current technology, the boundary between them is
It is about 250nsec. Considering the design margin, the operating speed required for conventional main memory is:
I have no choice but to use static RAM. On the other hand, in the present invention, the speed may be 1.5 times slower than the conventional example, so the dynamic RAM can be fully used as the main memory. Comparing the memory cost per unit capacity, dynamic RAM has a much smaller circuit scale within the memory due to its simple writing method, and is 1/1/2 that of static RAM.
It is about 4.

In other words, even if the main memory is doubled in capacity to one frame and the image quality of still images is improved, the price of the entire system can be kept lower than in the conventional case, which is extremely practical. It is advantageous.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main parts of a two-screen television receiver according to an embodiment of the present invention, FIG. 2 is a block diagram of the entire two-screen television receiver, and FIG. 3 is a conceptual diagram of the two-screen television receiver. 4 and 5 are operation timing diagrams of a two-screen television receiver according to an embodiment of the present invention, FIG. 6 is a block diagram of the main parts of a conventional two-screen television receiver, and FIG. 7 is a diagram of the conventional two-screen television receiver. FIG. 3 is an operation timing diagram of the screen television receiver. DESCRIPTION OF SYMBOLS 1...Two-screen television circuit section, 2...Composition side video signal input terminal, 3...Horizontal synchronization signal input terminal for composition side video, 4...Horizontal synchronization signal input terminal for composite side video, 5...Composition video signal output terminal, 101
...Frame memory, 102, 103...Buffer memory, 104...Buffer memory input switching circuit section, 105...Buffer memory output switching circuit section, 106...Clock generation circuit section (1), 107...
... Clock generation circuit section (2), 108 ... Clock generation circuit section (3), 109 ... Read end detection circuit section, 1
10...First clock, 111...Second clock, 112...Third clock, 113...Read end detection output.

Claims (1)

[Claims] One frame memory that can be read and written for each pixel, and two sets of buffer memories for a horizontal period that can be read and written for each horizontal period;
A first clock synchronized with the horizontal synchronization signal of the video to be synthesized, a second clock whose phase is 180 degrees different from the first clock, and a third clock synchronized with the horizontal synchronization signal of the video to be synthesized. Writing to the circuit that generates each of these and the frame memory is performed using the first clock in accordance with the horizontal synchronization of the video to be synthesized, and reading from the frame memory is performed using the second clock in accordance with the horizontal synchronization of the video to be synthesized. A clock control means is configured to perform the reading and writing of the two sets of buffer memories alternately in accordance with the horizontal synchronization of the video to be synthesized, and perform writing using the second clock and reading using the third clock. A two-screen television receiver comprising: 2. It has a means for detecting the end of reading of the buffer memory, and the detection output is used to switch which of the two buffer memories data is input to, and the horizontal synchronization signal of the image to be combined is used to switch which one to read data from. 2. The two-screen television receiver according to claim 1, wherein writing is subsequently started in the same buffer memory that was being read before the detection output.