JPS5620391A - Two-screen television receiver - Google Patents

Abstract

PURPOSE:To reduce memory capacity to half and also to reduce cost by writing the video signal of a subordinate video signal in a field memory and then by reading it with a fast clock signal at timing that corresponds to an insertion position on a master screen. CONSTITUTION:Buffer memory 51 consisting of one-field randomaccess memory 41, write clock generating circuit 42, read clock generating circuit 43, and three one- picture-element memories 511-513 is provided to write a video signal for the subordinate screen in memory 41 and at timing that corresponds to an insertion position on the master screen, it is read with a fast clock suitable to the contraction factor of the screen. As for access frequency fM of memory 41, and write frequency fW and read frequency fR of the subordinate screen, when fM fW+fR 4fW, the write operation of the subordinate screen is carried out once for every 4th access period and three times for every 4th read access period. Picture-element information read out of memory 51 at the fixed timing is mixed and displayed on the master screen as the subordinate screen by subordinate-screen inserting circuit 12.