JP3446442B2 - Video signal processing circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver or a video cassette recorder (VCR), a television (T).
V) A video signal processing circuit suitable for a video device such as a charger or an AV (audio / video) switch.

[0002]

2. Description of the Related Art Conventionally, a method of simultaneously displaying a first image composed of a first image signal and a second image composed of a second image signal on a receiver screen is shown in FIG. As shown in FIG. 5, the first image P ₁ is mainly displayed on the screen of the receiver and the second image P ₂ is displayed small in the first image P ₁ , or as shown in FIG. 5B. , A method of mainly displaying the first video P ₁ on the screen of the receiver and displaying the second video P ₂ in a small size outside the first video P ₁ , or as shown in (C) of FIG. There is a method of dividing the upper part into two parts, a first image P ₁ and a second image P ₂ .

Processing for simultaneously displaying at least two images on these receiver screens (hereinafter referred to as two-screen processing)
Is realized by time-axis conversion of one or both of the first video signal and the second video signal by a memory circuit, for example.

In FIG. 6, for example, as shown in FIG. 5C, the screen of the receiver is divided into two and the first image P ₁ and the second image P ₂ are simultaneously displayed. A specific configuration example of the video signal processing circuit is shown.

In FIG. 6, the first analog video signal supplied to the input terminal 101 is converted into a digital video signal by an analog / digital (A / D) converter 103. Is once stored in the memory circuit 105 including a field memory and then read. At the time of reading from the memory circuit 105, the time axis is set so that the first digital video signal already stored is displayed in the left half of the screen of the receiver as shown in FIG. It is compressed and read.

Here, the writing operation and the reading operation of the first digital video signal in the memory circuit 105 for performing the time base compression are performed as shown in FIG.

In FIG. 7, when writing a digital video signal to the memory circuit 105, a solid line L in the figure is used.
As shown by W ₁ , LW ₂ , ..., Writing is performed in real time for each dot in units of one line. That is, for example, the data of each dot forming the first line is shown by a solid line LW _{1 in} the figure, and the data of each dot forming the next second line is shown by a solid line LW _{2 in} the figure. The data of each dot forming each line is sequentially written in the memory circuit 105 every horizontal scanning period (1H). On the other hand, when reading from the memory circuit 105, the dotted line LR in the figure
_As indicated by ₁ , LR ₂ , ..., With a 1 / 2H offset, reading is performed in sequence for each dot at a speed double that at the time of writing. That is, for example, regarding the data of each dot forming the first line, the solid line LR _{1 in the} figure
As shown in the solid line LR _{2 in} the figure, the data of each dot forming the second line has the offset of 1 / 2H when the data of each dot forming each line, The data is sequentially read from the memory circuit 105 for each dot at a double speed. As a result of such writing / reading, a time-axis-compressed video signal corresponding to the left half of the screen is obtained.

The second analog video signal supplied to the input terminal 102 is an analog / digital (A / D) signal.
The converter 104 converts the second digital video signal into a digital video signal, and the second digital video signal is temporarily stored in the memory circuit 106 including a field memory and then read. At the time of reading from the memory circuit 106, it is necessary to display the second digital video signal which is already stored in the right half on the screen of the receiver as shown in FIG. 5C. It is axially compressed and read in synchronization with the first digital video signal.

The writing operation and the reading operation of the second digital video signal in the memory circuit 106 are the same as the case of the first digital video signal described in FIG. in case of,
As a result of writing / reading to / from the memory circuit 106, a time-axis-compressed video signal corresponding to the right half of the screen is obtained.

The digital video signal read from the memory circuit 105 is a digital / analog (D / A) signal.
The digital video signal that is converted into an analog video signal by the converter 107 and read from the memory circuit 106 is converted into an analog video signal by the digital / analog (D / A) converter 108. The first analog video signal and the second analog video signal converted into analog signals by the digital / analog converters 107 and 108 are added by the adder 109, and the result is shown in FIG.
A video signal that divides the screen of the receiver as shown in 2 into the first image P ₁ and the second image P ₂ is output from the output terminal 110 to the receiver.

By the way, conventionally, a process for doubling the scanning frequency (hereinafter referred to as a double speed process) may be performed for the purpose of eliminating flicker (so-called flicker) when an image is displayed on a receiver. . This double-speed processing doubles the horizontal scanning frequency for the purpose of eliminating flicker between lines (hereinafter referred to as line double-speed processing), and doubles the vertical scanning frequency for the purpose of eliminating flicker between fields. Processing (hereinafter referred to as field double speed processing), etc., and each method is realized by performing double scanning (writing the video signal twice).

FIG. 8 shows an example of a concrete configuration of a video signal processing circuit for realizing the above-mentioned field double speed processing.

In FIG. 8, the analog video signal supplied to the input terminal 120 is converted into a digital video signal by the analog / digital converter 121, and the digital video signal is temporarily stored in the memory circuit 122 and then read out. .

Here, the writing operation and the reading operation of the digital video signal in the memory circuit 122 for realizing the field double speed processing are performed as shown in FIG.

In FIG. 9, the solid line F in the figure is used when writing the digital video signal to the memory circuit 122.
As shown by W ₁ , FW ₂ , ..., Writing is sequentially performed line by line in real time. That is, for example, the data of each line forming the first field is indicated by a solid line FW _{1 in} the figure, and the data of each line forming the next second field is indicated by a solid line FW _{2 in} the figure in order. Is written in. On the other hand, when reading from the memory circuit 122, the dotted line FR in the figure
_As indicated by ₁₁ , FR ₁₂ , FR ₂₁ , FR _22, ..., Each line is sequentially read at a speed twice that at the time of writing. That is, the data of the first field written as shown by the solid line FW _{1 in} the figure is shown by the dotted lines FR ₁₁ and FR ₁₂ in the figure, and the data of the second field written as shown by the solid line FW ₂ is the dotted line FR in the figure. _21, as shown in FR _{2 2,} it is read out twice sequentially line by line at a multiple of the speed at the time of writing, respectively. By performing such writing and reading, the video signal for two fields is output from the memory circuit 122 for one field.
In addition, 1V in the drawing of FIG. 9 is one vertical scanning period.

The digital video signal output from the memory circuit 122 is a digital / analog converter 123.
Output terminal 1 after being converted into an analog video signal by
24 outputs as a double-speed video signal that realizes double-speed processing.

As described above, FIG. 6 shows a configuration example of the video signal processing circuit for realizing the dual screen processing for simultaneously displaying two videos on the screen of the receiver as shown in FIG. 5C. FIG. 8 shows a configuration example of a video signal processing circuit for realizing the field double speed processing. However, both the function of simultaneously displaying two videos on the receiver screen and the function of performing the field double speed processing are shown. There is also a video signal processing circuit having a function.

A video signal processing circuit having both such functions is realized, for example, by the configuration shown in FIG. That is, the video signal processing circuit shown in FIG.
After the circuit configuration for the dual screen processing shown in FIG.
The circuit configuration for double speed processing shown in is simply connected.

In FIG. 10, the first analog video signal supplied to the input terminal 101 is converted into a digital video signal by the analog / digital converter 103,
The first digital video signal is once stored in the memory circuit 105 including a field memory and then read. At the time of reading from the memory circuit 105, the digital video signal is timed by the method described in FIG. 7 so that it is displayed in the left half on the screen of the receiver shown in FIG. 5C. It is axially compressed and read. The digital video signal read from the memory circuit 105 is converted into an analog video signal by the digital / analog converter 107. The writing operation and the reading operation of the first digital video signal in the memory circuit 105 are the same as those described in FIG.

The second analog video signal supplied to the input terminal 102 is the analog / digital converter 10
4, the second digital video signal is converted into a digital video signal, and the second digital video signal is once stored in the memory circuit 106 including a field memory and then read. At the time of reading from the memory circuit 106, the digital video signal is timed by the method described in FIG. 7 so that it is displayed in the right half on the screen of the receiver shown in FIG. 5C. It is axially compressed and read in synchronization with the first digital video signal. The digital video signal read from the memory circuit 106 is converted into an analog video signal by the digital / analog converter 108.

The first analog video signal and the second analog video signal converted into analog signals by the digital / analog converters 107 and 108 as described above are
An analog / digital converter is used as a video signal that is added by the adder 109 and divides the image on the screen of the receiver as shown in FIG. 5C into the first image P ₁ and the second image P ₂ . Sent to 121.

The signal converted into a digital video signal by the analog / digital converter 121 is once stored in the memory circuit 122 and then read out. In this memory circuit 122, the digital video signal is sequentially read twice for each line at a speed twice that at the time of writing, as described with reference to FIG. Video signals for two fields are output. The digital video signal output from the memory circuit 122 is converted into an analog video signal by the digital / analog converter 123, and then the output terminal 12
4 is output as a double speed video signal for realizing double speed processing.

[0023]

Here, the above-mentioned FIG.
There are the following two problems with the video signal processing circuit having the configuration of 0.

One is that both the circuit for double screen processing and the circuit for double speed processing are provided with an analog / digital converter and a digital / analog converter, and a video signal passes through these. Therefore, deterioration of the video signal becomes a problem. That is, both the analog / digital converter and the digital / analog converter are provided with a low-pass filter as a measure against aliasing due to sampling, and this frequency band limitation causes deterioration of image quality such as ringing and smear.

The other is that a total of two circuit blocks, that is, a circuit for two-screen processing and a circuit for double-speed processing, uses three memory circuits, and therefore the cost is high.

Therefore, the present invention has been made in view of the above-mentioned problems, and in a video signal processing circuit having both functions of dual screen processing and double speed processing, the video signal is an analog / digital converter and a digital signal. / A video signal processing circuit that can minimize the deterioration of image quality when passing through an analog converter, and can reduce the cost by effectively using the memory circuit and reducing the number thereof. The purpose is to provide.

[0027]

A video signal processing circuit according to the present invention comprises first and second analog / digital conversion means for analog / digital converting first and second analog video signals, respectively. A first and a second memory means for respectively converting the digitally converted first and second digital video signals into a double speed signal, and by controlling the reading of the first and second memory means, a screen is displayed. The above-mentioned problem is solved by performing the time axis compression process for the above compressed display.

That is, in the present invention, by sharing the memory means used for both the two-screen processing and the double speed processing,
The image quality deterioration at the time of passing through the analog / digital converter and the digital / analog converter is minimized, and the number of memory means is reduced.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows the configuration of a television receiver as one configuration example to which the video signal processing circuit of the present invention is applied.

[0031] In FIG 1, a broadcast wave of a first video signal received by the antenna 1 is converted into a video intermediate frequency signal at the tuner 2 _1, it is sent to a video detection circuit 3 _1. In the video detection circuit 3 ₁ demodulates the video intermediate frequency signal, it switches the resulting composite video signal circuit 4
Send to. Meanwhile, the broadcast wave of the second video signal received by the antenna 1 is converted into a video intermediate frequency signal at the tuner 2 ₂ and sent to the video detection circuit 3 _2. The video detection circuit 3 ₂
Then, the video intermediate frequency signal is demodulated and the obtained composite video signal is sent to the switching circuit 4.

The switching circuit 4 is connected to the composite video signal of the first video from the video detection circuit 3 ₁ and the composite video signal of the second video from the video detection circuit 3 ₂ or an external device such as a video deck. One of the external video signals supplied via 19 is selectively switched and output.

The composite video signal of the first video output from the switching circuit 4 is separated by the Y / C separation circuit 5 _{1 into a} luminance signal Y ₁ and a chroma signal C ₁ . The color difference signal C ₁ is demodulated into color difference signals B-Y ₁ and the color difference signals R-Y ₁ by the color difference demodulation circuit _61, the luminance signal Y ₁ is the color difference signal B-Y ₁ and the color difference signals R-Y _It is sent together with ₁ to the double screen processing / double speed processing circuit 7.

Similarly, the composite video signal of the second video output from the switching circuit 4 is separated into a luminance signal Y ₂ and a chroma signal C ₂ by the Y / C separation circuit 5 ₂ . The color difference signal C ₂ is demodulated by chrominance demodulation circuit 6 ₂ to the color difference signal B-Y ₂ and the color difference signals R-Y _2, the luminance signal Y ₂ are the color difference signals B-Y ₂ and the color difference signals R- It is sent to the dual screen processing / double speed processing circuit 7 together with Y ₂ .

The two-screen processing / double-speed processing circuit 7 is a block that performs the two-screen processing and the double-speed processing, which is the point of the present invention, and the details thereof will be described later.

The matrix circuit 8 has a luminance signal Y and a color difference signal B- which are obtained by the dual screen processing / double speed processing circuit 7 as described later by performing both the dual screen processing and the double speed processing.
Y and the color difference signal RY are represented by R (red), G (green), and B.
Converted to (blue) three primary color signals.

The R, G, and B primary color signals from the matrix circuit 8 are sent to the blanking circuit 9. The blanking circuit 9 performs a blanking process on the R, G, and B primary color signals in accordance with the horizontal blanking pulse and the vertical blanking pulse.

The output of the blanking circuit 9 is amplified by the amplifier 10 and sent to the CRT (cathode ray tube) 14.

On the other hand, in the sync separation circuit 11, the horizontal sync signal S is converted from the video signal supplied from the switching circuit 4.
_{The h} and the vertical synchronizing signal S _v are separated and sent to the double screen processing / double speed processing circuit 7. The horizontal synchronizing signal S _H corresponding to the image after the dual screen processing / double speed processing described later from the dual screen processing / double speed processing circuit 7 is sent to the horizontal drive circuit 12, and the horizontal drive circuit 12 outputs the horizontal sync signal S. The horizontal deflection yoke of the CRT 14 is driven according to _H. Also,
The vertical synchronizing signal S _V corresponding to the image after the dual-screen processing / double-speed processing, which will be described later, from the dual-screen processing / double-speed processing circuit 7 is sent to the vertical drive circuit 13.
Drives the vertical deflection yoke of the CRT 14 according to the vertical synchronizing signal S _V. These drive circuits 12,
The electron beam generated by the electron gun of the CRT 14 is deflected by 13.

Next, the two-screen processing and the double-speed processing in the two-screen processing / double-speed processing circuit 7 of FIG. 1 will be described with reference to FIG.

The input terminal 21 is supplied with the luminance signal Y ₁ , the color difference signal B-Y ₁ and the color difference signal R-Y ₁ as the first analog video signal, and the first analog video signal is analog / analog. The digital (A / D) converter 23 converts the digital video signal. This first digital video signal is once stored in the memory circuit 25 and then read out. When reading from the memory circuit 25, the already stored first digital video signal is displayed, for example, in the left half on the screen of the receiver as shown in FIG. 5C. The time axis is compressed and the data is read at double speed. That is, in the memory circuit 25, the read speed for time axis compression and the read speed for double speed processing at the time of two-screen processing are summed up, and reading is performed at a speed four times faster than that at the time of writing.

Here, the writing operation and the reading operation of the first digital video signal for performing the double screen processing and the double speed processing in the memory circuit 25 are performed as shown in FIG.

In FIG. 3, when writing the first digital video signal to the memory circuit 25, as shown by solid lines fw ₁ , fw ₂ , ... Is written in. That is, for example, the data of each line forming the first field is indicated by a solid line fw _{1 in} the figure, and the data of each line forming the next second field is indicated by a solid line fw _{2 in} the figure in order for each line. Is written in. On the other hand, when reading from the memory circuit 25, as shown by dotted lines fr ₁₁ , fr ₁₂ , fr ₂₁ , fr ₂₂ ... The data is read twice, and at each line, the reading speed is doubled. That is, for example, the data of the first field written as indicated by the solid line fw _{1 in} the figure is the dotted lines fr ₁₁ and f in the figure.
The data of the second field written by the solid line fw _{2 as} shown by r ₁₂ and the data of the second field as shown by dotted lines fr ₂₁ and fr ₂₂ in the drawing are doubled at a speed twice that at the time of writing, and 1 Each line is read at twice that speed.

[0044] Similarly, the input terminal 22, as a second analog video signal, the luminance signal Y ₂ and the color difference signal B-Y ₂
And the color difference signal RY ₂ are supplied, and the second analog video signal is supplied to the analog / digital (A / D) converter 24.
Is converted into a digital video signal. The second digital video signal is once stored in the memory circuit 26 and then read out. At the time of reading from the memory circuit 26, the already stored second digital video signal is displayed, for example, in the right half on the screen of the receiver as shown in FIG. 5C. The time axis is compressed, and the data is read at a double speed and in synchronization with the first digital video signal. That is, also in the memory circuit 26, the reading speed for time axis compression and the reading speed for double speed processing during the two-screen processing are summed up, and reading is performed at a speed four times higher than that at the time of writing. The writing operation and the reading operation of the second digital video signal in the memory circuit 26 are the same as those in the case of the first digital video signal as described with reference to FIG.

Here, FIG. 4 is an enlarged view of a portion surrounded by a circle M in FIG. In FIG. 4, M _A shows the case of the first image, and M _B shows the case of the second image. That is, in FIG. 4, the memory circuits 25 and 2
The data of each line of the first video and the second video stored in 6 are alternately read at the timing of 1 / 2H.

The first digital video signal and the second digital video signal read from the memories 25 and 26 as described above are added by the digital adder 27 and are shown in FIG. Such a digital image signal is obtained by dividing the screen of the receiver into the first image P ₁ and the second image P ₂ . This digital video signal is converted into an analog video signal by the digital / analog converter 28 and output from the output terminal 29 to the receiver.

As described above, in the dual-screen processing / double-speed processing circuit 7 which performs dual-screen processing and double-speed processing,
The number of times of passing through the digital converter and the digital / analog converter can be reduced from the conventional two times to one,
Therefore, it is possible to minimize the deterioration of image quality.

Further, by sharing the memory circuit between the two-screen processing and the double speed processing, it is possible to save one memory circuit as compared with the conventional structure, and to use the analog / digital converter and the digital / analog converter. Can also be saved, thus reducing costs. Here, for example, when trying to maintain the band of 8 MHz of the input video signal, the memory circuit 10 of FIG.
5, 106, and also the memory circuit 2 of FIG.
In 5 and 26, the sampling clock for writing is
16 MHz is required. The memory capacity required for this is
If the effective video section of one line is about 60 μsec, 6
0 μsec / (1/16 MHz) = 960, and assuming that this is 8 bits and the effective video section of one field is about 250 lines, 960 × 8 × 250 = 192
0000, about 2M bits are required. At this time, the conventional read in FIG.
0 configuration sampling clock (32MHz)
In this case, the amount of information contained in the memory circuit itself is the same even in the case of the sampling clock (64 MHz) in the structure of FIG. In short, the memory capacity is determined by the frequency of the write clock. Therefore, the memory circuits 105, 106, 122 in FIG. 10 and the memory circuits 25, 26 in FIG. 2 have the same capacity. Therefore, as in the configuration example of the present invention, the cost can be reduced by saving one memory circuit as compared with the conventional configuration. However, in the actual configuration of the present invention, the frequency of the readout clock (32 MHz) is not changed even when the two-screen display is performed or when the two-screen display is stopped and only the first image is displayed. In addition, the clock on the writing side (8 MHz when displaying in two screens, 6 MHz when not displaying in two screens)
Is set to 1/2 of the conventional one (therefore, the sampling clock according to the configuration of the present invention is four times the sampling clock of the conventional configuration) only when displaying two screens. The memory circuit 26 can be half as large as the conventional memory circuit 106.

In the above example, as the two-screen processing,
The first image P is displayed on the screen of the receiver as shown in FIG.
_{Although the case where the first} image P ₁ and the second image P ₂ are divided into _two is described, the first image P ₁ is mainly displayed on the screen of the receiver as shown in FIG. A method of displaying the second image P ₂ in a small size within the first image P ₁ or displaying the first image P ₁ mainly on the receiver screen as shown in FIG. It goes without saying that the present invention can be applied to a method of displaying the second image P ₂ in a small size outside ₁ and various other methods. Further, in the above example, the double speed processing is the field double speed processing, but it is also possible to use the line double speed processing or other double speed processing. Therefore, the combination of each of the two-screen processing and the double speed processing can be another combination, and the same effect as described above can be obtained even with these other combinations.

[0050]

According to the video signal processing circuit of the present invention, first and second analog / digital conversion means for respectively analog / digital converting the first and second analog video signals, and these analog / digital conversions. First done,
It has first and second memory means for respectively converting the second digital video signal into a double speed signal, and by controlling the reading of the first and second memory means, it is possible to perform compression display on the screen. By performing the time axis compression process, the image quality when the video signal passes through the analog / digital conversion means and the digital / analog conversion means in the video signal processing circuit having the functions of both the double screen processing and the double speed processing. Deterioration can be minimized, and by effectively using the memory means, it is possible to save the analog / digital conversion means, the digital / analog conversion means, the memory means, etc., and realize the cost reduction.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an overall configuration of a television receiver to which a video signal processing circuit of the present invention is applied.

FIG. 2 is a video signal processing circuit of the present invention which is a two-screen processing
It is a block circuit diagram which shows the specific structure of a double speed processing circuit.

FIG. 3 is a diagram for explaining operations of a two-screen process and a double speed process according to the present invention.

FIG. 4 is an enlarged view of a part of FIG.

[Fig. 5] Fig. 5 is a diagram for describing a format example on a screen of two-screen processing.

FIG. 6 is a block circuit diagram showing a configuration example of a conventional video signal processing circuit that divides a receiver screen into two parts, a first image and a second image, as an example of dual-screen processing.

FIG. 7 is a diagram for explaining the operation of a conventional video signal processing circuit that divides a screen of a receiver into a first video image and a second video image as an example of dual-screen processing.

FIG. 8 is a block circuit diagram showing a configuration example of a conventional video signal processing circuit that performs field double speed processing as an example of double speed processing.

FIG. 9 is a diagram for explaining the operation of a conventional video signal processing circuit that performs field double speed processing as an example of double speed processing.

FIG. 10 is a block circuit diagram showing a configuration example of a conventional video signal processing circuit that realizes both dual-screen processing and double-speed processing.

[Explanation of symbols]

7 Two-screen processing / double speed processing circuit 23, 24 Analog / digital converter 25,26 memory circuit 27 Digital adder 28 Digital / Analog Converter

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 5/44-5/46 H04N 5/265

Claims (5)

(57) [Claims] 1. A first analog / digital conversion means for converting a first analog video signal into a first digital video signal, and a first memory means for converting the first digital video signal into a double speed signal. A second analog / digital conversion means for converting the second analog video signal into a second digital video signal, and a second memory means for converting the second digital video signal into a double speed signal, A video signal processing circuit characterized by performing a time axis compression process for compression display on a screen by controlling reading of the first and second memory means. 2. The video signal processing circuit according to claim 1, further comprising a synthesizing means for synthesizing the outputs of the first and second memory means. 3. The video signal processing circuit according to claim 1, wherein the first memory means doubles a horizontal scanning frequency to convert the first digital video signal into a double speed signal. 4. The video signal processing circuit according to claim 1, wherein the first memory means doubles the vertical scanning frequency to convert the first digital video signal into a double speed signal. 5. The video signal processing circuit according to claim 1, wherein time axis compression processing is performed on one or both of the first digital video signal and the second digital video signal.