JPS6284665A - Television receiver - Google Patents

Abstract

PURPOSE:To perform a master-slave display without any deterioration in picture quality by providing a deflecting circuit which makes a scan on the whole display part with an aspect ratio c:d at a double speed, making a double-speed display at a master picture part, and also displaying a slave picture part without thinning out. CONSTITUTION:An arrival video signal has its synchronizing signals separated by a synchronous separating circuit 11 and is supplied to a scanning signal generating circuit 14 which generates a double-speed horizontal synchronizing signal of frequency which is twice as high as that of the received horizontal synchronizing signal. The output digital video signal of an A/D converter 3 is written on a storage device 4 with the write signal from a control circuit 13. The time-base converted signal from the storage device 4 is processed by an interpolating circuit 15 to obtain a video signal increased in the number of scanning lines. A video signal for a slave image which is written on the storage device 23 for one vertical period in synchronization with a slave image video signal is read out in synchronization with a master image, sent to a D/A converter 6 for a slave image display period with the signal from the control circuit 15 through a switching circuit 5, and amplified by an output circuit 8 to a desired amplitude; and then a cathode-ray tube 10 is driven to obtain the slave image.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a television receiver that can simultaneously display two types of images on the screen of the television receiver.

Conventional technology In recent years, there has been a demand for higher resolution and higher quality television images, and the number of scanning lines is approximately twice that of the current NTSC and PAL systems, and the frequency band is widened to achieve high resolution. Various television systems have been proposed in which the aspect ratio is wider than the current 4:3, for example 5:3, and television receivers with horizontally long display sections have been put into practical use.

Moreover, a receiver that uses such a horizontally elongated display section with an aspect ratio of 5:3 has a function of displaying images of the current television format with an aspect ratio of 4:3. However, when current television broadcasts are received by a receiver with such functions and displayed on the entire display area with an aspect ratio of 6:3, as shown in Figure 2, the image becomes distorted (Figure 2b). occurs. Therefore, distortion is prevented by controlling the deflection current and displaying an image with an aspect ratio of 4:3 on a part of the display section (FIG. 2C).

However, when trying to add a so-called parent-child screen function that simultaneously displays different images on a part of the screen to a receiver that eliminates distortion by controlling the deflection current, the problem occurs as shown in Figure 2 (d). As shown, the child image causes the inconvenience that the parent image is missing.

Furthermore, since the child images are displayed in a reduced size, they are thinned out both horizontally and vertically, resulting in poor image quality.

Problems to be Solved by the Invention Therefore, the present invention aims to display an image of the current television system on a display section with a wider aspect ratio (for example, 5:3) than the current television system (aspect ratio of 4:3) in a parent-child screen. To effectively use the horizontal display area to minimize the portion of the parent image that is lost due to the child image, and to display the parent image portion at double speed scanning without thinning out the child image portion. The purpose of the present invention is to provide a receiver capable of displaying high-quality parent-child images.

Means for Solving the Problems The present invention includes a deflection circuit that scans the entire display section with an aspect ratio of cod at double speed, a first storage device that stores a first television signal, and a third television signal that stores a first television signal. The television receiver includes a second storage device for storing data.

According to the above-described structure, the present invention displays the parent image area at double speed and displays the child image area without thinning out, thereby performing parent and child display without deteriorating the image quality and making the horizontally long display area effective. The purpose is to minimize the loss of the parent image.

Embodiment FIG. 1 shows a block diagram of a television receiver in an embodiment of the present invention. In Fig. 1, 1 and 20 are input terminals, 2 and 21 are video signal processing circuits, and 3 and 2 are input terminals.
2 is a MU/D converter, 4 and 23 are storage devices, 6 is a switching circuit, 6 is a 1)/A converter, 7 is a matrix, 8 is an amplifier circuit, 9 is a deflection yoke, 10 is a cathode ray tube, 11 and 24 is a synchronization separation circuit, 12 is a deflection circuit, 13 is a control circuit, 14 is a scanning signal generation circuit, and 15 is an interpolation circuit.

Here, for ease of understanding, the aspect ratio of the horizontally long display section is 6:3. The television signal for parent-child display is 4;3. Furthermore, although the size of the child screen displayed with N=2 will be described as A of the main screen, the present invention is not limited to this.

The video signal for the parent image that has arrived at the input terminal 1 is demodulated by the video signal processing circuit 2 into a luminance signal Y and color difference signals RY and B-Y, and then converted into digital video signals by the M/D converter 3. is converted to Furthermore, the incoming video signal is sent to the synchronous separation circuit 1.
1 is also supplied, and the synchronization signal is separated. Synchronous separation circuit 1
The horizontal synchronization signal separated by 1 is supplied to a scanning signal generation circuit 14 that generates a double-speed horizontal synchronization signal having twice the frequency of the received horizontal synchronization signal. The output signal of the scanning signal generation circuit 14 is supplied to the deflection yoke 9 via the deflection circuit 12.
A raster having twice the number of scanning lines is formed on the cathode ray tube 10. The raster formed at this time completely scans the display surface of the cathode ray tube 1o. At the same time, the synchronization signal is also supplied to the control circuit 13. The digital video signal output from the gam/D converter 3 is written into the storage device 4 by a write signal from the control circuit 13. Assume now that the parent image is displayed on the right side of a display screen with an aspect ratio of 5:3, and the child image is displayed on the lower left side of the display screen, as shown in FIG. At this time, the data is read out from the storage device 4 in a phase relationship such that it is closer to the right side of the screen, as shown in FIG. 3, and is read out with the time axis converted so as not to cause image distortion. The operation of the storage device 4 will be explained in more detail using FIG. 4. The arrived video signal (FIG. 4 &) is written into the storage device 4 in a video signal period t, taking t time. (Figure 4b) As mentioned above, the raster is formed with twice the number of scanning lines, so one horizontal scanning period is t/2, and (Figure 4d) the aspect ratio is To eliminate image distortion due to differences, t/2×4/+5=2t
It is read out in a period of 15. Furthermore, as shown in FIG. 3, in order to display on the right side of the display surface, t11
The reading is delayed in time from the horizontal deflection start point. (FIG. 4C) That is, 1. An image signal whose time phase is delayed and whose time axis is converted at time 2t15 is obtained from the storage device 4. The time-base converted signal from the storage device 4 is used in an interpolation circuit 15 to create a video signal of increased scanning lines. That is, as mentioned above, since the number of scanning lines forming a raster is doubled due to double-speed scanning, it is necessary to increase the number of video signals accordingly.
For example, a video signal is created by pre-interpolation, which uses the same video signal twice. The digital video signal from the interpolation circuit 15 is switched by the switching circuit 6 for a period corresponding to the person in FIG. 3 by the control signal from the control circuit 13.
/A converter 6. The signal converted into an analog signal by the D/mu converter e is converted into R, G, B by the matrix circuit 7.
After being converted into a signal and amplified to the desired amplitude by the output circuit 8,
The cathode ray tube 10 is driven to obtain the main image portion of the person shown in FIG. 3 at double speed scanning.

Next, the operation of the child image section will be explained.

The child image video signal that has arrived at the input terminal 20 is demodulated into a luminance signal Y and color difference signals R-Y and B-Y in a video signal processing circuit 21, and then converted into digital signals by an A/D converter 22. and written to the storage device 23. The video signal arriving at the input terminal 20 is also supplied to a synchronization separation circuit 24, where the synchronization signal is separated. The synchronization signal separated by the synchronization separation circuit 24 is supplied to the control circuit 13. Reading from the storage device 23 is performed in synchronization with the parent image video signal from the control circuit 13. As shown in FIG. 3, if the child image is to be displayed at the lower left B of the display section, it will take one vertical period to display the child image on the storage device in synchronization with the child image video signal.
The video signal for the child image (Fig. 6a) written in No. 3 is
It is read out in synchronization with the parent image during the period Tv corresponding to FIG. B. (Fig. 6b) At this time, the horizontal display period TII for displaying the child image without distortion is 'l'I' as shown in Fig. 6.
I=a/cXMXH', and as mentioned above, the aspect ratios are 4/b=4/3. . /d=5/3 and d/1)=N=2, so it can be expressed as TH-15t. That is, a signal with a horizontal effective scanning period of t is written into the storage device 23 over a period of t, and is read out at six times the speed.

Note that the readout start point in the horizontal direction coincides with the horizontal deflection start point in the case of FIG. The child image video signal read from the storage device 23 is sent to the child image display period D/A converter 6 by the switching circuit 5 in response to a signal from the control circuit 13. The signal converted into an analog signal by the D/A converter 6 is converted into R, G, and B signals by the matrix circuit 7, and after amplified to a desired amplitude by the output circuit 8, the cathode ray tube 10 is driven and the sub-image get.

Effects of the Invention As described above, the present invention includes a deflection circuit that generates a double-speed scanning raster that covers the entire display area with an aspect ratio of C:d, and a deflection circuit for displaying a parent image at double speed and without distortion. By providing a storage device with different write speeds and read speeds and a storage device with different write speeds and read speeds for child images, there is no image quality deterioration due to thinning of child images. can be displayed on the left side, and the horizontally long display area can be effectively used to minimize the missing part of the parent image, which has a great practical effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a television receiver according to an embodiment of the present invention, FIG. 2 is a diagram showing a display state of a conventional television receiver, and FIG. 3 is a diagram showing a display state of a television receiver of the present invention. 4 is a waveform diagram for explaining the operation of the storage device for parent images, FIG. 5 is a diagram for explaining the operation of the storage device for child images, and FIG. 6 is a waveform diagram for explaining the operation of the storage device for child images. It is a figure explaining read speed. 1.20...Input terminal, 2.21...Video signal processing circuit, 3,22...A/D converter, 4,23...
...Storage device, 5...Switching circuit, 6...
...D/A converter, 7...matrix, 8...
...Amplification circuit, 9...Deflection yoke, 10...
...Cathode ray tube, 11,2409. ...Synchronization separation circuit,
12...Deflection circuit, 13...Control circuit, 14...Scanning signal generation circuit, 15...
・Interpolation circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person Riku, O 08 Ward

Claims (1)

[Claims] a first television signal having an aspect ratio a:b and a number of scan lines approximately N times that of the first television signal;
and a second television signal with an aspect ratio of c:d (a/b<c/d), the frequency is N times that of the horizontal synchronization signal received when receiving the first television signal. a scanning signal generation circuit that generates a double-speed horizontal synchronizing signal of c:d; a deflection circuit that scans the entire display section with an aspect ratio of c:d; /a×N, and write a third television signal having the same aspect ratio as the first television signal in synchronization with the third television signal. A television receiver comprising a storage device that reads data at a speed of c/a×N^2 in synchronization with a television signal.