JPS58221574A - Detecting circuit of vertical synchronizing signal - Google Patents

Abstract

PURPOSE:To detect accurately the vertical synchronizing signal, by obtaining a timing signal having a delay of a fixed time to a one side timing of the rise or fall of the synchronizing signal in response to a TV synchronizing signal and using the timing signal as a latch signal to latch successively the synchronizing signals. CONSTITUTION:A TV synchronizing signal mixed with horizontal and vertical synchronizing signals is supplied to an input terminal 1 and then to a delay circuit 2 as well as to a latch circuit 3. The one side timing of rise or fall of the synchronizing signal is delayed a prescribed time by the circuit 2 and supplied to the circuit 3 as a latch signal. Then the circuit 3 latches successively the synchronizing signals supplied from the terminal 1 to detect accurately a vertical synchronizing signal VS out of a composite TV synchronizing signal.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a television synchronization signal (hereinafter referred to as " This invention relates to a vertical synchronization signal detection circuit that detects and separates a vertical synchronization signal from a "composite synchronization signal".

[Technical background of the invention]

The so-called PCM recorder, which digitizes audio signals using PCM (pulse code modulation) and records and plays them on a recording medium, has a VTR (video tail recorder) in the recording and playback system, which is also called a PCM encoder/decoder. There are things that are appropriated. This kind of P
Since the CM recorder records and plays back on a VTR, P
The data digitized by commercials is converted into a pseudo video signal having a synchronization signal similar to that of a television signal. In other words, a television broadcast signal is composed of a synchronization signal that is a composite of a horizontal synchronization signal and a vertical synchronization signal (this is referred to as "Composite Synchronization No. 41"), a video signal, etc. A pseudo video signal is one in which digital data, a white level reference signal, etc. are inserted in place of the video signal at the corresponding locations.

In devices that use such pseudo video signals or television signals, when playing back (such as when playing a VTR), the composite synchronization signal in the pseudo video signal or television signal is converted into a video signal or a portion equivalent to it. The vertical synchronization signal was then detected from this composite synchronization signal to generate a vertical synchronization signal.

Conventionally, when detecting and generating a vertical synchronization signal from a composite synchronization signal, as is done in television receivers, the composite synchronization signal separated from the video signal or its equivalent part is integrated using an integrator. It was common to compare the signal with a reference level using a comparator to obtain a vertical synchronization signal.

However, when a vertical synchronization signal is detected using this method, the positions of the detected vertical synchronization signal's front and trailing edges (usually one of them is important) can be greatly affected by even a slight change in the comparator's reference level. It will change.

Further, even if the DC level of the integral signal fluctuates, the same change as described above occurs. Furthermore, in this case, the signal obtained by integrating the composite synchronization signal is compared using a controller or a regulator, but since the integrated signal contains an approximately triangular wave-like ripple due to the horizontal synchronization component, there is a width before and after the original vertical synchronization pulse of the comparator output. Narrow pulses may occur, leading to uncertainty or fluctuations in the position of the trailing edge of the vertical synchronization signal.

In particular, when operating a PLL (phase lock loop f) circuit based on the detected vertical synchronization signal to obtain a reference period or frequency signal that follows changes in the vertical synchronization signal, the above-mentioned fluctuations may occur. This causes the lock position to shift, which poses a major problem.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a vertical synchronization signal detection circuit that can accurately detect a vertical synchronization signal from a composite synchronization signal without being affected by level fluctuations and has a simple configuration.

[Summary of the invention]

The present invention latches the original (undelayed) composite synchronization signal at the rise or fall of the composite synchronization signal delayed by a delay means, and delays the rise or fall by the delay time. It is characterized by obtaining a vertical synchronization signal.

[Embodiments of the invention]

FIG. 1 shows the configuration of an embodiment of the present invention.

In FIG. 1, 1 is an input terminal into which a composite synchronization signal C8 separated from the video signal or its equivalent part is input, and 2 is an input terminal in which the composite synchronization signal C8 input to the input terminal is delayed by a preset delay time TD. This is a delay circuit that causes a delay. 3 is an A latch circuit constructed using, for example, a D-Furi, Gutsulodge, etc., and the composite synchronization signal CS input to the input terminal J is applied to the signal input terminal. The output of the delay circuit 2 is given as a latch signal (2, pulse). 4 is an output terminal for outputting the output of the output terminal Q of the latch circuit 8 to the outside.

Next, the operation in such a configuration will be explained.

The composite synchronization signal CS input to the input terminal 1 is, for example, the second
In the waveform shown in Figure (a), VP is the vertical synchronization pulse portion to be detected, HP is the horizontal synchronization/4' pulse, and EP is the equivalent/IP pulse. This composite synchronization signal C
S is applied to the signal input terminal of the latch circuit 3 and also input to the delay circuit 2, and the delayed synchronization signal DS delayed by the delay time TD is output as the output of the delay circuit 2, as shown in FIG. 2(b). is output. This delayed synchronization signal DS is applied to the clock input terminal CK of the latch circuit 8, and the input to the signal input terminal, that is, the original composite synchronization signal C8, is latched at the falling edge of the illustrated waveform of the line signal DS. Therefore, the output of the child circuit 3, that is, the output of the output terminal 4, is the vertical synchronization signal VS delayed by the delay time TD with respect to the original composite synchronization signal C8, as shown in FIG. 2(c). . At this time, since the latch circuit 3 operates at the falling edge of the illustrated waveform of the delayed synchronizing signal DB, the delay time TD is set to the horizontal synchronizing pulse HP so that this falling position does not overlap with the horizontal synchronizing signal HP and the equivalent pulse EP. Pulse width H
w (A normal Hw = 0.075 H, H: horizontal scanning period)
Equivalent to Dulse EP's Dulse period ET (usually ET=
0.5H) so that the relationship Hw < To < ET is satisfied.

Note that if the latch circuit 3 is operated at the rising edge of the waveform of the delayed synchronization signal DS shown in FIG.
A signal vS' as shown in Figure (d) is obtained. This signal vS' has a /4' pulse width that is slightly different from the original vertical synchronizing signal, but the pulse leading edge (falling edge in the figure) position is equivalent to the equivalent pulse EP.
If the pulse width is set to Ew (normally Ew = 0.04 H), a waveform delayed by exactly To + Ed Ew can be obtained, which is sufficient for use when the leading edge of the arm is used. (
In this case, if the leading edge of this pulse is applied to a monostable multi-pisolator, etc. whose time width is set to be equal to the pulse width of the original vertical synchronizing signal, the trailing edge position of the pulse will also be exactly the vertical synchronizing signal delayed by the above time as its output. I can get a signal. ) In this case, the delay time T of delay circuit 2
D may be set to O<To<(ET EW).

Despite this simple configuration using only delay circuit 2 and latch circuit 3, it is possible to detect vertical synchronization signals whose time difference from the original signal is a clear constant value without being affected by level fluctuations, etc. can do. Generally, the detected vertical synchronization signal is used to obtain standards such as timing, so
Even if time advances or lags, as long as it is a clear constant value, it can be used without any problems. Moreover, in most cases, the vertical synchronization signal uses only one of the leading edge or the trailing edge of the Noculus, so it is sufficient if the time delay is constant only for the leading edge or the trailing edge of the Noculus. Further, since the delay circuit 2 can be constructed from a digital circuit using a shift register or the like, the entire circuit shown in FIG. 1 can be constructed from a digital circuit.1. The configuration can be significantly simplified, and more stable operation against noise and the like can be achieved. Therefore, the PLL circuit is extremely stable even when used in a PLL circuit.
The present invention is not limited to the embodiments described above and shown in the drawings, but can be implemented with various modifications without changing the gist thereof.

For example, the latch circuit 3 in the above embodiment.

In order to obtain the child signal, the composite synchronization signal C8 is delayed as is by the delay circuit 2, but since the latch circuit 3 uses only the rising or falling edge of the latch pulse, the composite synchronization signal C8 is delayed instead of the delay circuit 2. A means for obtaining a timing signal that detects the rising or falling edge of CS and operates the latch circuit 3 at a timing delayed by a predetermined time with respect to that timing, such as a monostable multi-pipe rake delay means or the output of a differentiating circuit. It is also possible to use a delay means for operating a multi-quibrator.

〔Effect of the invention〕

According to the present invention, vertical synchronization can be performed accurately without being affected by level fluctuations, etc., with a simple configuration in which the original composite synchronization signal is latched by the rise or fall of the composite synchronization signal delayed by the delay means. A vertical synchronization signal detection circuit capable of detecting words can be provided.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing the configuration of an embodiment of the present invention, and FIGS. 2(a) to (d) are waveform diagrams of various parts for explaining the operation of the embodiment. 1... Input terminal, 2... Delay circuit, 3... Latch circuit, 4... Output terminal. Applicant's agent Patent attorney Takehiko Suzue Procedural amendment (
7F Rejection Showa 57* 10. g() Japanese Patent Office Commissioner Kazuo Wakasugi 1, Indication of the case, Patent Application No. 1982-104982, 2, Title of the invention, Vertical synchronization signal detection circuit 3, Person making the amendment, Relationship with the case, Patent applicant (240 ) Sansui Denki Co., Ltd. 4, agent, page 10, line I88, "(a) to (d)" are deleted.

Claims (1)

[Claims] In a vertical synchronization signal detection circuit that detects and separates a vertical synchronization signal from a television synchronization signal in which a horizontal synchronization signal and a vertical synchronization signal are combined, the vertical synchronization signal detecting circuit detects and separates a vertical synchronization signal from a television synchronization signal in which a horizontal synchronization signal and a vertical synchronization signal are combined. a delay means for obtaining timing No. 41 delayed by a predetermined time with respect to at least one of the downlink timings; and a latch that sequentially uses the timing signal obtained by the delay means as a latch signal to sequentially clock the original television lightning synchronization signal. A vertical synchronization signal detection circuit characterized by comprising a circuit.