JPS5837165Y2 - Synchronous signal processing device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a circuit system for obtaining sampling pulses of a phase comparator that constitutes an AFC circuit of a color signal synchronization circuit during signal reproduction in a magnetic recording/reproducing device (hereinafter referred to as a VTR) from a composite synchronization signal. It is.

AFC generally used in VTR reproduction color signal synchronization circuit
As shown in Figure 1, the circuit separates a composite sync signal from a composite video signal in a composite sync signal separation circuit 1, and then separates only the horizontal sync signal part from this composite sync signal in a horizontal sync signal separation circuit 2. , and by using this as a sampling pulse for the phase comparator 3, a stable AFC loop is constructed.

As a method for separating a horizontal synchronizing signal from a composite synchronizing signal, a horizontal synchronizing signal separating circuit constructed of two monostable multi-circuits as shown in FIG. 2 has been used.

That is, the composite synchronization signal shown in FIG. 3a is inputted to the terminal 23 by the first monostable multi-channel 21 consisting of the resistor Rzt capacitor C1 and the transistor circuit So7 (here, the dotted line portion indicates an equivalent pulse).

), and further resistors R2,
A second monostable multi-channel circuit 22 comprising a capacitor C2 and a transistor circuit 28 generates a pulse having a constant pulse width as shown in FIG.

Therefore, in the conventional example explained in FIG. 2, two monostable multicircuits are required, and especially when integrated, external terminals 24 and 25 are required because the capacitors C1 and C2 are used as time constant circuits. However, the resistors R1 and R2 of the time constant circuit and the capacitors C1 and C2 are required as external components, and the pulse width is strongly dependent on the temperature of the resistors and capacitors.

Also, when playing back signals recorded on a VTR, etc., tape
The reproduced signal is often deleted due to deterioration of the head or the like.

Now, as shown in FIG.
3.5μs), one horizontal synchronization signal (Fig. 4a)
(shown by the dotted line), the first monostable multi 21 is triggered by the next equivalent pulse of the missing pulse as shown in FIG. It is triggered by an equivalent pulse until the end of the 9H period of the vertical synchronizing signal and the equivalent pulse periods before and after it.

Therefore, the output pulse of the second monostable multi 22 is
As shown in Figure C, when there is no deletion of the horizontal synchronization signal (the fourth
(shown in FIG. d), the state is equivalent to the state in which the phase fluctuation of H2 occurs within the 9H period.

Therefore, the signal obtained in FIG. 4C is converted to V
When used as a sampling pulse for the AFC circuit of the color signal synchronization circuit of the TR, from the time when the horizontal synchronization signal is lost until the end of the 9H period of the equivalent pulse is 1! , H occurs, and the AFC circuit attempts to follow this phase fluctuation so as to correct it.

However, as shown in Figure 4C, unless the response of the AFC circuit is made extremely fast (actually, it cannot be made very fast from the viewpoint of stability) with the horizontal synchronizing signal after the 9H period ends, the color signal insertion period will be delayed. (Generally, the burst signal is inserted immediately after the 9H period, and the color signal is inserted after 12H to 13H.

), since the AFC loop does not recover to a steady state, the color signal after the vertical synchronization signal does not have a normal phase, resulting in a very unsightly image.

The present invention attempts to eliminate the above drawbacks by digitally processing the composite synchronization signal.

In other words, the time constant circuit of the first monostable multi is unnecessary, and even if one horizontal synchronizing signal is missing within the 9H period, the first monostable multi is prevented from operating with the next equivalent pulse. This prevents the AFC loop from being disturbed.

FIG. 5 is a logic diagram showing one embodiment of the present invention, and FIG. 6 is a timing chart when one horizontal synchronizing signal is missing within a 9H period.

In FIG. 5, Q1 to Q7, QIO, and Qll are D-type flip-flops (hereinafter simply referred to as D-FF), Q
8. Q9 is an R-S flip-flop (hereinafter simply R5FF)
), 01 to G3 are AND gates, and G4 is an OR gate.

The operation will be explained below according to FIGS. 5 and 6.

(1) D-FFQ1 to Q7 and R-3FFQ8. A clock signal (clock frequency f.

is 40 times the horizontal synchronizing signal frequency fH) enters the clock input terminal CL of the D-FFQ, the Q output of the D-FFQ6 changes from LOW to HIGH.
i, R3FFQ8 is reset and its Q output goes from OW to Hi level.

(2) When the Q output of R-3FFQ8 becomes Hi level,
Since the Q output of D-FFQl is at Hi level, A
ND gate G2 operates, and D- via OR gate G4.
FF Q to is reset.

At this time, D-FFQIO becomes LOW from the river, but R-
Since the Q output of JFFQ8 is connected to the D input terminal of D-FFQII at the same time (the 233rd pulse D-FF
The Q output of Q1 is inverted from Hi to LOW level, and therefore the ryat state of DFFQlo is about 1.6 μsec.
It will be canceled later.

(3) Next, when the composite synchronization signal of the input terminal 12 applied to the clock input terminal CL of DFFQ+o becomes Hi level, D-FFQ,o is inverted from LOW to Hi level, and at this time, D-FFQ,1 are at LOW level, AND gate G1 operates, and I)-FFQ, ~Q7 and R-JFFQ8. Q9 is set.

(4) When R-JFFQ8 is set, its Q output is inverted to LOW level, and the Q output of R-JFFQ8 is High.
I)-FFQl changes from Hi to LOW due to the clock signal of the clock input terminal 11 immediately after it becomes LOW from D-FFQ1 to Q7 and I)-JFFQ
8. The set state of Q9 is removed after approximately 1.6 μsec.

Next, an explanation will be given of the operation when one horizontal synchronization signal is missing within the 9H period of the vertical synchronization signal and the equivalent pulse period before and after the vertical synchronization signal, as shown in FIG. 4a.

Of the four steps described above, all steps except (2) are the same.

(2) LH to the clock input terminal CL of 'DFFQ, .
(40 clock pulses, 63.5μ5ec) after H
If the i-level input is not supplied, D-FFQI to Q7 continue to divide the frequency, and when the 56th pulse is received, the 5-man power AND gate G3 is activated, and becomes Hi until the 64th pulse is received. The ryat terminal of period D FFQIO becomes Hi, and the equivalent pulse input to the clock input terminal CL of D FFQIO becomes invalid within that period, and R-FFQ,o does not change.

The following steps (3) and (4) are performed to restore the original state.

The output signal (I) of the first monostable multifunction device processed as described above (output of FFQlo) is shown in FIG. 4e.
This output signal passes through the second monostable multi 13, and a sampling pulse as shown in FIG. 4f is obtained at the output terminal 14.

With this sampling pulse, one pulse is missing from the pulse train in the normal state, and there is no phase fluctuation of H after the 9H period as in the conventional case, and the previous state is generally held by the sample and hold capacitor, so the AFC loop continues to operate without significant disturbance.

As explained in the above embodiment, by digitally processing the composite synchronization signal, the first monostable multi-time constant circuit can be made unnecessary, and the vertical synchronization signal and the 9H period of the equivalent pulse period before and after it can be made unnecessary. H2 caused by the first monostable multi being triggered with an equivalent pulse in the absence of the horizontal sync signal within.

Since phase fluctuation can be prevented, it is possible to stably operate the AFC loop, which is highly effective.

Furthermore, the number of terminals can be reduced by performing signal processing in a digital circuit and eliminating the need for a time constant circuit, making it suitable for integrated circuit implementation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram configuring an AFC circuit, FIG. 2 is a diagram showing a conventional example of a horizontal synchronization signal processing circuit, FIGS. 3 and 4 are operational waveform diagrams, and FIG. A logic diagram showing one embodiment of the signal processing device, and FIG. 6 is a timing chart diagram for explaining its operation. Q1 to Q7 and QIQ, Qll...D type flip-flop, Q8. Q9...R-J type flip-flop, G1-G3...NAND gate, G4...OR gate, 13...
Second monostable multivibrator.

Claims (2)

[Scope of utility model registration request] (1) A composite synchronization signal is input to the clock input terminal, and D
A D-type flip-flop whose input terminal is fixed at bi-level generates a pulse within a period of -(H (H is approximately 63.5 μs in one horizontal scanning time)) after the composite synchronization signal is input. and a time t after inputting the composite synchronization signal is at least (=H-1t)<t<(ヱH+Jt)2.
a second pulse generating means that generates a pulse during a period of 2 (O<, at<-); and an output signal of the first pulse generating means and an output signal of the second pulse generating means are inputted. and a means for inputting the output signal of the OR gate to the reset input terminal of the D-type flip-flop, and a means for inputting the output signal of the OR gate to the reset input terminal of the D-type flip-flop, and inputting the signal from which the equivalent pulse portion included in the composite synchronization signal is removed to the D-type flip-flop. A synchronous signal processing device characterized in that the signal is obtained from an output terminal of the synchronous signal processing device. (2) The first pulse generating means has a frequency f higher than the horizontal synchronizing signal frequency. is a clock input signal, and a first flip-flop whose output polarity is inverted by the mth (m is a positive integer 9 time h < t = fo < H) lock signal of this clock input signal; The output signal of the flip-flop No. 1 is input to the D input terminal, and the frequency f is input to the clock input terminal. A utility model registration claim 1, characterized in that the utility model is comprised of a second D-type flip-flop to which a signal is input, the first flip-flop, and the second D-type flip-flop. synchronous signal processing device.