JPH0427014Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a synchronization signal extraction circuit, and more specifically, to extracting data synchronization pulses from a digital signal in a digital signal recording and reproducing device that uses a magnetic recording and reproducing device such as a VTR as a data storage means. related to circuits.

For example, in a digital signal recording and reproducing apparatus using a VTR as a digital data storage means, the digital signal is converted into a signal form suitable for recording and reproducing by the VTR, that is, a pseudo video signal equivalent to a video signal. As for the signal conversion format, vertical synchronizing pulses, horizontal synchronizing pulses, etc. necessary for the video signal are added, and information words and redundant bits for error control are added to the portion corresponding to one horizontal scanning period as shown in Figure 1. , a data synchronization pulse, and a white reference pulse are added, and one horizontal scanning period consists of 168 bits including 128 data pulses.

When recording and reproducing this pseudo video signal, the reproduced pseudo video signal is shaped into a pulse waveform based on a predetermined DC level (slice level),
Regenerate the original pseudo video signal, use the data synchronization pulse in the pseudo video signal to form a bit synchronization clock for reproducing digital data, read the shaped pseudo video signal at the timing of the bit synchronization clock, and reproduce digital information. do.

However, when recording and reproducing pseudo video signals, if the VTR's recording and reproducing tape speed is set to a long-time mode, that is, at a slower speed than the standard tape speed, the VTR's recording and reproducing frequency characteristics deteriorate, so the dotted line in Figure 2 As shown in Figure 2, because the data synchronization pulse response within the horizontal scanning period that must be reproduced is slow, the DC signal level of the first wave of the synchronization pulse fluctuates as shown by the solid line in Figure 2, and the waveform is shaped at a predetermined slice level. However, the data synchronization pulses could not be accurately reproduced due to time lag, making normal reproduction impossible. Furthermore, the amount of variation in this DC signal level differs among individual VTRs.

The present invention solves the above-mentioned conventional drawbacks, and makes it possible to adjust the slice level for waveform shaping during the period in which the data synchronization pulse in the pseudo video signal arrives. The arrival of the data synchronization pulse and its duration are detected to obtain a detection pulse having the same pulse width as the data synchronization pulse period, and this detection pulse and a pulse with the opposite polarity of the detection pulse are added at a predetermined ratio, and this ratio is so that it can be cut variablely,
The resulting addition pulse is added to the reference signal (slice level setting) terminal of the comparator for shaping the pseudo video signal, and the slice level can be adjusted to an appropriate value only during the data synchronization pulse period. The present invention provides a synchronization signal circuit that performs the following steps.

The present invention will be described in detail below based on the illustrated embodiments.

FIG. 3 shows the synchronization signal extraction circuit of the present invention.
is a horizontal sync separation circuit, and the VTR (not shown)
Only the horizontal synchronizing signal in the pseudo video signal reproduced from the input terminal IN is separated. 2
is a counter, and the horizontal synchronization signal output from the horizontal synchronization separation circuit 1 is supplied to its set input terminal S via the differentiating circuit E1, and is set by the trigger pulse obtained at the rising edge of the horizontal synchronization signal, and the clock input is Count the reference clock (2.6MHz) input to terminal CK. This counter sets the period from the rising edge of the horizontal synchronizing signal to the rising edge of the data synchronizing pulse in the horizontal scanning period signal shown in Figure 1, and the number of bits in this period is specified as 15 bits (time Converted to 6 μs bit synchronous clock = 2,
6MHz), and after counting the reference clock for 15 clocks, it outputs a counting pulse. Reference numeral 3 denotes a monostable multivibrator, which is triggered by the counting pulse from the counter 2 and operates to output a detection pulse whose pulse width is the data synchronization pulse period. In other words, the pulse width of the detection pulse is 4 bits, which is the same as the data synchronization pulse period, and in terms of time, it is
It will be 1.5μ seconds. 4a and 4b are an inverter and a buffer, respectively, to which detection pulses are supplied, and each output has the same pulse width and opposite polarity.

The output of inverter 4a is capacitor C1 and resistor
Via R1, the output of buffer 4b is supplied to summing regulator VR through capacitor C2 and resistor R2.

The detection pulse from the monostable multivibrator 3 is also applied to the reset terminal R of the counter 2 via the differentiating circuit E2, and the counter 2 is reset at the rising edge of the detection pulse.

Next, the addition processing by the addition regulator VR will be explained.

FIG. 4 shows an equivalent circuit of the circuit configuration after the inverter 4a and buffer 4b.
Let A be the output signal from the buffer 4b, and B be the output signal from the buffer 4b. R4 and R5 are parts that act on the signals A and B of the addition regulator VR, respectively, and vary the addition ratio of the output signals A and B by increasing or decreasing according to the adjustment position of the addition regulator VR.

In other words, the output signal is A'=R3・A/(R1+R3+R4)...(1) On the other hand, the output signal B is B'=R3・B/(R2+R3+R5)...(2) are added as follows.

Therefore, by adjusting the addition regulator VR, (1),
If the denominators of equation (2) are equal, the addition pulse will be A'+B'=0, if R1+R4>R2+R5, A'+B'>0, if R1+R4<R2+R5, A'+B'<0.

The summed pulse obtained as described above is supplied to the reference signal terminal (-) of the comparator 5.

A pseudo video signal is applied to a comparison input terminal (+) of the comparator 5, and waveform shaping of the pseudo video signal is performed at a slice level defined by a reference voltage applied to a reference signal terminal (-).

In the case of this embodiment, a slice level correction voltage is supplied to the reference signal terminal (-) via the amplifier 7 for correcting the slice level to an appropriate value in response to DC signal level fluctuations of the pseudo video signal.

The configuration is as described above, and its operation will be explained next.

The pseudo video signal (Fig. 5a) reproduced from the VTR is supplied to the comparison input terminal (+) of the comparator 5, and part of it is supplied to the horizontal synchronization separation circuit 1, where only the horizontal synchronization signal H is separated. Ru.

Next, the separated horizontal synchronizing signal H is sent to the differentiating circuit E1
is applied to the set terminal S of the counter 2 via
The number of arrivals of the reference clock supplied to the clock is counted. The point in time when 15 clocks have been counted from the reference clock, that is, the rising time of the data synchronization pulse
A counting pulse F (FIG. 5b) is output at t1 and applied to the monostable multivibrator 3.

Upon application of the counting pulse F, the monostable multivibrator 3 outputs a detection pulse G that lasts for a data synchronization pulse arrival period D as shown in FIG. 5c. Next, the detection pulse G is applied to the inverter 4a and the buffer 4b.
are respectively supplied to obtain output signals A and B having a pulse width of D and opposite polarities.

Next, output signals A and B are supplied to the summing regulator VR via resistors R1 and R2 to obtain a summing pulse, which is used to adjust the slice level. For example, if the reference voltage is at the level shown by dotted line 01 in Figure 5a, if waveform shaping is performed at this slice level, the first waveform of the data synchronization pulse will disappear, making it difficult to accurately determine the data synchronization pulse. Playback becomes impossible. Therefore, by adjusting the addition regulator VR, the addition ratio of the output signals A and B is adjusted, and an addition pulse having a polarity and level that reduces the reference signal level, that is, the slice level is formed, and the reference input to the comparator 5 is Apply to terminal (-) (5th
Figure d).

Therefore, since the previous slice level 01 is lowered to 02 only during the data synchronization pulse period in the pseudo video signal, the waveform shaping of the data synchronization pulse can be performed accurately.

In this case, whether the slice level is an appropriate value can be determined based on whether the information is being reproduced accurately. For example, in digital audio reproduction, normal reproduction is performed from the speakers within the error correction range, and no reproduction is performed from the speakers if the error correction range is even slightly exceeded.

As described above, the present invention slices a digital signal reproduced by a magnetic recording/reproducing device at a predetermined slice level and performs waveform shaping to reproduce the original digital signal. Since the slice level for waveform shaping can be adjusted to an appropriate value during the data synchronization pulse period in response to Synchronization pulses can be reliably reproduced, allowing stable digital signal reproduction.

[Brief explanation of the drawing]

FIG. 1 shows the signal format in one horizontal scanning period of the pseudo video signal, and FIG. 2 shows the reproduced waveform of the data synchronization pulse in the pseudo video signal.
FIG. 3 is a block diagram showing one embodiment of the present invention, FIG. 4 is a partial equivalent circuit diagram of the block diagram shown in FIG. 3, and FIG. 5 is a waveform diagram for explaining the operation of this embodiment. Explanation of symbols, 1...Horizontal synchronization separation circuit, 2...
Counter, 3... Monostable multivibrator, 4
a...Inverter, 4b...Buffer, 5...Comparator.

Claims (1)

[Scope of utility model registration request] In a digital signal recording and reproducing device that detects pulse intervals at a predetermined slice level of a digital signal reproduced by a magnetic recording and reproducing device and performs waveform shaping to reproduce the original digital signal, the data synchronization pulse in the digital signal is a synchronization pulse period detection circuit that outputs a detection pulse having a pulse width equal to the data synchronization pulse period in response to the arrival of the data synchronization pulse; a polarity inversion circuit that generates an inverted detection pulse having an opposite polarity and equal pulse width to the detection pulse; a slice that generates an addition signal by adding the pulse and the inversion detection pulse at a predetermined ratio, and includes an addition adjuster that can vary the addition ratio, and provides the slice level during the data synchronization pulse period in the digital signal. A synchronous signal extraction circuit characterized in that a slice level can be adjusted by adding the addition signal to a voltage.