JPS6261Y2 - - Google Patents

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Publication number
JPS6261Y2
JPS6261Y2 JP14782779U JP14782779U JPS6261Y2 JP S6261 Y2 JPS6261 Y2 JP S6261Y2 JP 14782779 U JP14782779 U JP 14782779U JP 14782779 U JP14782779 U JP 14782779U JP S6261 Y2 JPS6261 Y2 JP S6261Y2
Authority
JP
Japan
Prior art keywords
signal
circuit
playback
synchronization
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP14782779U
Other languages
Japanese (ja)
Other versions
JPS5664523U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14782779U priority Critical patent/JPS6261Y2/ja
Publication of JPS5664523U publication Critical patent/JPS5664523U/ja
Application granted granted Critical
Publication of JPS6261Y2 publication Critical patent/JPS6261Y2/ja
Expired legal-status Critical Current

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  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Description

【考案の詳細な説明】 本考案は動作の安定な読取パルス発生回路に関
する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a read pulse generating circuit with stable operation.

円板状記録媒体に音声信号をPCM信号として
記録する場合は、通常、PCM信号を映像信号化
して記録しており、再生PCM信号の読取は、周
期性があり再生PCM信号の時間的変動成分を有
する再生水平期信号を同期入力とする発振回路の
発振出力を読取パルスとして利用している。しか
し、斯る発振回路も水平同期信号に混入するドロ
ツプアウトノイズによつて同期乱れを生じ、ドロ
ツプアウト発生部に続く正常な水平同期区間に於
ける読取誤りをも招来することが確認された。
When recording an audio signal as a PCM signal on a disc-shaped recording medium, the PCM signal is usually converted into a video signal and recorded, and the readout of the reproduced PCM signal is periodic and involves the temporal fluctuation components of the reproduced PCM signal. The oscillation output of an oscillation circuit whose synchronous input is a regenerated horizontal period signal having . However, it has been confirmed that such an oscillation circuit also causes synchronization disturbances due to dropout noise mixed into the horizontal synchronization signal, leading to reading errors in the normal horizontal synchronization section following the dropout occurrence area. .

そこで、本考案は上述の点に鑑み、水平同期分
離出力よりノイズ成分を解消しノイズによる誤動
作のない読取パルス発生回路を提案せんとするも
のである。
Therefore, in view of the above-mentioned points, the present invention aims to propose a read pulse generation circuit that eliminates the noise component from the horizontal synchronization separated output and is free from malfunctions due to noise.

以下本考案を図示せる一実施例に従い説明す
る。本実施例の特徴は水平同期信号中に混入する
ドロツプアウトノイズが、多くの場合水平同期信
号の同期先端より低いレベルに達すると云う事実
に着目し斯るノイズの導出を阻止すると共に、加
えて水平同期信号の幅に相当する出力のみ判別導
出してPCM信号読取用の同期発振回路に対する
同期入力としている。即ち、本実施例では、ビデ
オデイスクより再生されるFMPCM信号をFM復
調して導出される再生PCM信号(第2図a)
を、水平同期先端より僅か高いレベルを設定レベ
ルとする第1電圧比較回路1と、同期先端より僅
か低いレベルを設定レベルとするドロツプアウト
検出回路(第2電圧比較回路)2に入力し、ドロ
ツプアウト検出出力(第2図b)を前記第1電圧
比較回路1の制御入力として印加することによ
り、該第1電圧比較回路1よりドロツプアウト出
力が導出されることを阻止する。しかし前記第1
電圧比較回路1より導出される比較出力(第2図
c)は、ドロツプアウト出力の発生を阻止するも
のの阻止部分にパルス状ノイズを残す。そこで本
実施例は前記比較出力cを更にパルス幅判別回路
に入力し水平同期パルスのパルス幅以外のノイズ
パルスの導出を阻止し、該判別出力dを同期入力
として読取パルス発生用の同期発振回路4に入力
してPCM信号読取パルスの位相コントロールを
為している。
The present invention will be described below with reference to an illustrative embodiment. The feature of this embodiment is that it focuses on the fact that dropout noise mixed into the horizontal synchronization signal often reaches a level lower than the synchronization tip of the horizontal synchronization signal, and prevents the derivation of such noise. In addition, only the output corresponding to the width of the horizontal synchronization signal is determined and derived, and is used as the synchronization input to the synchronization oscillation circuit for reading the PCM signal. In other words, in this embodiment, the reproduced PCM signal (FIG. 2a) derived by FM demodulating the FMPCM signal reproduced from the video disc is
is input to a first voltage comparator circuit 1 whose set level is slightly higher than the horizontal synchronization tip, and a dropout detection circuit (second voltage comparator circuit) 2 whose set level is slightly lower than the synchronization tip. By applying the output (FIG. 2b) as a control input to the first voltage comparator circuit 1, a dropout output is prevented from being derived from the first voltage comparator circuit 1. However, the first
Although the comparison output (FIG. 2c) derived from the voltage comparison circuit 1 prevents the generation of dropout output, it leaves pulse-like noise in the blocked portion. Therefore, in this embodiment, the comparison output c is further inputted to a pulse width discrimination circuit to prevent the derivation of noise pulses other than the pulse width of the horizontal synchronization pulse, and the discrimination output d is used as a synchronization input to a synchronous oscillation circuit for generating read pulses. 4 to control the phase of the PCM signal reading pulse.

尚第2図より明らかな如く、前記判別出力dに
は、ドロツプアウトによる水平同期信号の欠落部
分もあるが、同期発振回路4に対する同期入力が
1〜2欠落しても読取パルスの位相が変動するこ
とはなく、むしろ、位相の僅か外れる擬似水平同
期信号を同期発振回路4に入力する方が読取パル
スの位相を大きく乱す惧れがあることも確認され
た。
As is clear from FIG. 2, the discrimination output d includes a missing portion of the horizontal synchronizing signal due to dropout, but even if one or two synchronizing inputs to the synchronous oscillation circuit 4 are missing, the phase of the read pulse will fluctuate. It was also confirmed that inputting a pseudo-horizontal synchronization signal whose phase is slightly out of phase to the synchronization oscillation circuit 4 may greatly disturb the phase of the read pulse.

よつて上述せる本考案によれば、ドロツプアウ
トの発生にも拘らず、動作の安定な読取パルスの
発生が可能となりその効果は大である。
Therefore, according to the present invention described above, it is possible to generate a read pulse with stable operation despite the occurrence of dropout, and the effect is great.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施回路ブロツク図、第2
図は同波形説明図をそれぞれ顕わす。 主な図番の説明、1……電圧比較回路、2……
ドロツプアウト検出回路、3……パルス幅判別回
路、4……同期発振回路。
Figure 1 is a block diagram of an implementation circuit of the present invention;
The figures each show the same waveform explanatory diagram. Explanation of main figure numbers, 1... Voltage comparator circuit, 2...
Dropout detection circuit, 3... Pulse width discrimination circuit, 4... Synchronous oscillation circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 映像信号化したPCM信号を記録媒体より再生
し、負の再生同期信号に同期した読取パルスによ
つてPCM信号を読取るPCM再生回路に於て、再
生PCM信号より再生同期信号の同期先端より低
レベルのドロツプアウトノイズを検出するドロツ
プアウト検出回路と、再生PCM信号より再生同
期信号を含む低レベルの信号を検出すると共にド
ロツプアウト検出出力によつてドロツプアウトノ
イズの導出を阻止する電圧比較回路と、該電圧比
較出力より同期信号のパルス幅に一致する出力の
みを導出するパルス幅判別回路と、該判別出力に
同期してPCM信号読取パルスを導出する同期発
振回路を配して成る読取パルス発生回路。
In a PCM playback circuit that plays back a PCM signal converted into a video signal from a recording medium and reads the PCM signal using a read pulse synchronized with a negative playback synchronization signal, the level of the playback PCM signal is lower than the synchronization tip of the playback synchronization signal. a dropout detection circuit that detects dropout noise, and a voltage comparison circuit that detects low-level signals, including the playback synchronization signal, from the playback PCM signal and prevents dropout noise from being generated by the dropout detection output. , a pulse width discrimination circuit that derives only an output that matches the pulse width of the synchronization signal from the voltage comparison output, and a synchronous oscillation circuit that derives a PCM signal read pulse in synchronization with the discrimination output. generation circuit.
JP14782779U 1979-10-24 1979-10-24 Expired JPS6261Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14782779U JPS6261Y2 (en) 1979-10-24 1979-10-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14782779U JPS6261Y2 (en) 1979-10-24 1979-10-24

Publications (2)

Publication Number Publication Date
JPS5664523U JPS5664523U (en) 1981-05-30
JPS6261Y2 true JPS6261Y2 (en) 1987-01-06

Family

ID=29378970

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14782779U Expired JPS6261Y2 (en) 1979-10-24 1979-10-24

Country Status (1)

Country Link
JP (1) JPS6261Y2 (en)

Also Published As

Publication number Publication date
JPS5664523U (en) 1981-05-30

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