JPS5836546B2 - Doukibunri Cairo - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a sync separation circuit, and more particularly to a sync separation circuit used in a device that inputs a fluctuating composite video signal, such as a ζVTR (video table recorder).

In a VTR, a vertical synchronizing signal in a recorded composite video signal is separated and the frequency-divided output is used as a reference signal for a rotating head servo system.

Therefore, is the synchronization signal disturbance simply a recording/playback video? Not only is the signal disturbed, but the rotational phase of the rotary head is also disturbed, which seriously affects the reproduced image quality.

Conventionally, as this type of synchronous separation circuit, a grounded-edge type transistor circuit has been used, for example, which has a large-capacity capacitor in the base input circuit and is configured to apply a small bias current to the base. Regardless of when handling a composite video signal with a relatively stable level, such as in a vision receiver, the composite video signal may contain sag or noise, or there may be moments when a video signal portion is missing, such as during a commercial period in a commercial television broadcast signal. This method cannot be used in a VTR that handles composite signals that may be deleted due to the above-mentioned drawbacks due to the random deletion of synchronizing signals.

The present invention has been made in view of this point.

The details of the present invention will be explained below with reference to drawings showing an example of an embodiment of the circuit.

The synchronous separation circuit of the present invention is comprised of an input section 1, a clamp amplification section 2, and a synchronous separation section 3.

The input section 1 is connected in series to a capacitor 11 having a very small capacitance (for example, 0.01 μF) as opposed to that of a conventional example (usually about 33 μF).
Noise suppression circuit 14 consisting of a parallel circuit of 2 and resistor 13
Equipped with.

Further, the clamp amplifying section 2 includes a clamp diode 21.
and a large capacity capacitor 22 (for example, 100 μF) connected in series, and a resistive voltage divider circuit 2 that provides a constant voltage to the connection midpoint 23.
4.25, an inductance 26 whose purpose is to prevent fluctuations in the clamp level due to minute noises applied through the input circuit, and an emitter follow connection transistor 27 which receives the clamped composite video signal as input. .

On the other hand, the synchronous separator 3 has its base 31 directly connected to the emitter 28 of the emitter-follow-connection transistor 27 (NPN type), and is in the form of a cross-grounded structure. Actuated complementary (
PNP type) transistor 32, and a resistor 35 which together with a semi-fixed resistor 33 provides a constant voltage to the terminal 34 of the transistor 32 is connected to a large capacitor (approximately 100 μF) 3.
6 is omitted, and care is taken to avoid alternating current fluctuations.

The semi-fixed resistor 33 is used to adjust the emitter voltage of the transistor 32 to be slightly higher (approximately 0.4 V) than that of the factory follower transistor 27.

Next, the operation of the synchronous separation circuit of the present invention will be explained with reference to FIG. 2 showing waveforms of each part.

Suppose that a composite video signal V as shown in FIG. 2A, including sag S noise (f), etc., is applied to terminal (2) of the human-powered circuit 1.

As mentioned above, the coupling capacitor 11 has a 0.0.
Since it is selected to have an extremely small value of 0.05 to 0.01 .mu.F, the charging time is short, and in combination with the post-read Klumph intensifier, such sag is completely eliminated.

On the other hand, the largest noise in the composite video signal is
The small noise that remains after being removed by the noise suppression circuit 14 is also blocked by the inductance 26? Therefore, it does not affect the clamp level.

Therefore, the emitter of the emitter follower transistor 27, that is, the base 31 of the synchronous separation transistor 32, has the following characteristics:
Contains sag and high level noise as shown in Figure 2! No composite video signal is applied.

As described above, in combination with the fact that the emitter potential of the transistor 32 which operates in the ground-grounded manner is stabilized, the collector O of the transistor 32 has a voltage of
As shown in FIG. 2C, a stable synchronization signal that is not affected by zag, noise, or video signal omission is extracted.

[Brief explanation of the drawing]

The drawings all relate to the synchronization separation circuit of the present invention, with FIG. 1 showing an example of an implementation circuit, and FIG. 2 showing an explanatory diagram of operating waveforms. Explanation of main figure numbers, 11... Capacitor, 24,
25... Resistor voltage divider circuit, 21... Clamp diode, 22... Capacitor, 27...
...Emituta follower transistor, 32...
...Transistor for synchronous separation.

Claims (1)

[Claims] An input section consisting of a capacitor of about 10.01 to 0.05 μF and a noise suppression circuit connected in series with the capacitor and configured with a parallel circuit of the capacitor and resistor; a clamp intensifier including an emitter follower transistor supplied through an inductance connected in series with the diode, the output of the input section serving as a base input of the emitter follower transistor; A synchronous separator circuit comprising a synchronous separator having a transistor whose base is directly connected to the emitter of the transistor and a transistor having a complementary polarity and which operates in a common ground type.