JPS5919508Y2 - VIR signal removal circuit - Google Patents

VIR signal removal circuit

Info

Publication number
JPS5919508Y2
JPS5919508Y2 JP4970578U JP4970578U JPS5919508Y2 JP S5919508 Y2 JPS5919508 Y2 JP S5919508Y2 JP 4970578 U JP4970578 U JP 4970578U JP 4970578 U JP4970578 U JP 4970578U JP S5919508 Y2 JPS5919508 Y2 JP S5919508Y2
Authority
JP
Japan
Prior art keywords
circuit
signal
black level
connection point
vir
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP4970578U
Other languages
Japanese (ja)
Other versions
JPS5553371U (en
Inventor
盛弘 久保
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP4970578U priority Critical patent/JPS5919508Y2/en
Publication of JPS5553371U publication Critical patent/JPS5553371U/ja
Application granted granted Critical
Publication of JPS5919508Y2 publication Critical patent/JPS5919508Y2/en
Expired legal-status Critical Current

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  • Picture Signal Circuits (AREA)
  • Processing Of Color Television Signals (AREA)

Description

【考案の詳細な説明】 本考案はVIR信号除去回路に関する。[Detailed explanation of the idea] The present invention relates to a VIR signal removal circuit.

海外の放送チャンネルには、各フィールドの第19H目
にVIR信号(Vertical Interval
Referencesignal)を挿入するチャンネ
ルがある。
Overseas broadcast channels have a VIR signal (Vertical Interval) on the 19th H of each field.
There is a channel that inserts the reference signal).

VIR信号は第1図に図示せる如く、クロマファレンス
信号Cと輝度リファレンス信号Yと黒リファレンス信号
Bより成り、VIR信号をVIR検出回路にて検出する
と共にカラー信号の利得を輝度リファレンス信号Yとク
ロマリファレンス信号Cによって、またカラー信号の位
相をクロマリファレンス信号Cにより、更に輝度信号の
利得を輝度リファレンス信号Yと黒リファレンス信号B
によってそれぞれ調整している。
As shown in Fig. 1, the VIR signal is composed of a chroma reference signal C, a luminance reference signal Y, and a black reference signal B. The VIR signal is detected by a VIR detection circuit, and the gain of the color signal is calculated by combining the luminance reference signal Y and the chroma reference signal B. The phase of the color signal is determined by the reference signal C, the phase of the color signal is determined by the chroma reference signal C, and the gain of the luminance signal is determined by the luminance reference signal Y and the black reference signal B.
Each is adjusted accordingly.

一方NTSC方式の放送信号を録画再生する場合には、
通常カラー信号を低域輝度信号とインターリ−ピング関
係になるように低域変換すると共に、一方のフィールド
のキャリアをLH(Hは水平走査区間)毎に反転記録し
て、再生後再びキャリアを元の状態に戻すと共に低域輝
度信号を含む低域カラー信号を再び高域に変換して櫛形
フィルタに入力している。
On the other hand, when recording and playing back NTSC broadcast signals,
Normally, the color signal is low-frequency converted so that it has an interleaving relationship with the low-frequency luminance signal, and the carrier of one field is inverted and recorded every LH (H is a horizontal scanning section), and after playback, the carrier is used again as the original. At the same time, the low-frequency color signal including the low-frequency luminance signal is converted back to a high-frequency signal and is input to the comb filter.

櫛形フィルタでは、NTSC信号のサブキャリアが1H
毎に反転していることを利用して原信号と1H遅延出力
の反転出力を平均してインターリ−ピング関係にある低
域輝度信号成分の除去と隣接トラックとのクロストロー
ク成分の解消を同時に行なっている。
In the comb filter, the subcarrier of the NTSC signal is 1H.
By taking advantage of the fact that the signal is inverted every time, the original signal and the inverted output of the 1H delayed output are averaged to simultaneously remove the low-range luminance signal component that is in an interleaving relationship and eliminate the cross-stroke component with the adjacent track. ing.

よってNTSC方式のカラー信号を低域変換して録画す
る方式のVTRに配される櫛形フィルターは、vIR信
号を含むNTSC方式の放送信号を録画再生する場合に
、クロマリファレンス信号Cの振幅を半分にする。
Therefore, a comb filter installed in a VTR that records NTSC color signals by converting them to low frequency halves the amplitude of the chroma reference signal C when recording and playing back NTSC broadcast signals including vIR signals. do.

よって変形したVIR信号は、基準信号となり得なくな
るばかりか、正常な画像を乱すことになる。
Therefore, the deformed VIR signal not only cannot serve as a reference signal, but also disturbs a normal image.

そこで従来より櫛形フィルタを介して再生出力を導出す
る方式のVTRにはVIR信号を解消するVIR信号除
去回路が配されている。
Therefore, a VIR signal removal circuit for eliminating the VIR signal is conventionally provided in a VTR that derives the reproduced output through a comb-shaped filter.

第2図は従来のVIR信号除去回路のブロック図を顕わ
し、ビデオ信号aを入力せるクランプ回路1のクランプ
出力すを一人力、黒レベル設定回路2の黒レベル出力C
を他人力とすると共に、同期分離回路3より導出される
ビテ゛オ信号aの(水平)同期分離出力dを計数してV
IR信号の多重走査区間を検出する19H抜取パルス発
生回路4の抜取出力eを制御入力として、スイッチング
回路5に人力している。
FIG. 2 shows a block diagram of a conventional VIR signal removal circuit, in which the clamp output of the clamp circuit 1 to which the video signal a is input is controlled by one person, and the black level output C of the black level setting circuit 2 is controlled by one person.
, and count the (horizontal) synchronization separation output d of the video signal a derived from the synchronization separation circuit 3 to calculate V.
The sampling output e of the 19H sampling pulse generation circuit 4 for detecting the multiple scanning section of the IR signal is input to the switching circuit 5 as a control input.

該スイッチング回路5は、前記抜取出力eの発生に伴っ
て前記クランプ回路すに代え前記黒レベル出力Cを選択
することによりVIR信号を除去したスイッチング出力
fを導出している。
The switching circuit 5 selects the black level output C in place of the clamp circuit upon generation of the sampling output e, thereby deriving a switching output f from which the VIR signal is removed.

以下更に斯る従来例のクランプ回路1と黒レベル設定回
路2の回路の回路接続に付き第2図に従い説明する。
The circuit connection between the conventional clamp circuit 1 and black level setting circuit 2 will be further explained below with reference to FIG.

図示せる如くクランプ回路1は直流電圧を第1抵抗R1
と第2抵抗R2にて分割し、アース側の該第2抵抗R2
と並列に充放電用の第1コンデンサC1を配すると共に
面抵抗R,,R2の接続点Gよりビデオ信号線路に向け
て順方向に第1ダイオードD1を接続することにより、
ビデオ信号の同期先端を、接続点Gの電位より前記第■
ダイオードD1の電圧降下分を減じた電位にクランプし
て前記スイッチング回路5に入力しており、また前記黒
レベル設定回路2では直流電位を分割すべく可変ボリュ
ームVRを配して摺動子とアース間に充放電用の第2コ
ンデンサC2を接続することにより摺動子を調整して摺
動子電位をペデスタルレベルと−にして前記スイッチン
グ回路5に黒レベル出力Cとして入力している。
As shown in the figure, the clamp circuit 1 connects the DC voltage to the first resistor R1.
and the second resistor R2, and the second resistor R2 on the ground side
By arranging a first capacitor C1 for charging and discharging in parallel with and connecting the first diode D1 in the forward direction from the connection point G of the sheet resistances R, , R2 toward the video signal line,
The synchronization tip of the video signal is set from the potential of the connection point G to the
It is clamped to a potential obtained by subtracting the voltage drop of the diode D1 and inputted to the switching circuit 5. In addition, in the black level setting circuit 2, a variable volume VR is arranged to divide the DC potential between the slider and the ground. By connecting a second capacitor C2 for charging and discharging between them, the slider is adjusted so that the slider potential is at the pedestal level and -, and is inputted to the switching circuit 5 as a black level output C.

尚ビテ゛オ信号路に配された第3コンテ゛ンサC3は直
流成分阻止用のコンテ゛ンサである。
Note that the third capacitor C3 arranged in the video signal path is a capacitor for blocking DC components.

本考案は、斯る従来例に於て、前記分割点aの電イ立を
黒レベル出力として利用することにより、回路部品の削
減を可能にした新規且有効なVIR除去回路を提案せん
とするものである。
The present invention proposes a new and effective VIR removal circuit that makes it possible to reduce the number of circuit components in the conventional example by using the voltage at the dividing point a as a black level output. It is something.

以下本考案を第4図に図示せる一実施例に従い説明する
The present invention will be explained below according to an embodiment shown in FIG.

本実施例は、直流電圧を分割する第1抵抗R1及び第2
抵抗R2の接続点Gの電位をペデスタルレベルに設定す
ると共にダイオードD1.D2の順方向の電圧降下をペ
デスタルレベルと同期先端の電位差を一致せしめてクラ
ンプ回路を構成し、前記接続点Gの電位を黒レベル出力
Cとしてスイッチング回路5に入力している。
In this embodiment, the first resistor R1 and the second resistor R1 divide the DC voltage.
The potential at the connection point G of the resistor R2 is set to the pedestal level, and the diode D1. A clamp circuit is constructed by making the voltage drop in the forward direction of D2 match the pedestal level and the potential difference at the synchronization tip, and the potential at the connection point G is inputted to the switching circuit 5 as a black level output C.

よって本実施例回路によれば、抜取パルスeが発生して
いないとき、前記第1第2抵抗R1,R2と、縦続接続
されたダイオードDI、D2、及び充放電用の第1コン
デンサC1がクランプしたビデオ信号を前記スイッチン
グ回路5より導出し、また抜取パルスeが発生したとき
前記第1、第2抵抗R1,R2の接続点Gの電位をVI
R信号に代えて導出する。
Therefore, according to the circuit of this embodiment, when the extraction pulse e is not generated, the first and second resistors R1 and R2, the cascade-connected diodes DI and D2, and the first capacitor C1 for charging and discharging are clamped. When the sampling pulse e is generated, the potential at the connection point G between the first and second resistors R1 and R2 is derived from the switching circuit 5.
It is derived in place of the R signal.

従って本実施例回路によればクランプ回路が黒レベル発
生回路としても機能するため接続作業の減少と部品点数
の削減が可能になりその効果は大である。
Therefore, according to the circuit of this embodiment, since the clamp circuit also functions as a black level generating circuit, it is possible to reduce connection work and the number of parts, which is highly effective.

尚本考案回路は、ビテ゛オテープレコーダの記録側回路
に設けても再生側回路に設けても効果上の相違はない。
It should be noted that there is no difference in effectiveness whether the circuit of the present invention is provided in the recording side circuit or the reproduction side circuit of a video tape recorder.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はVIR信号の波形説明図、第2図は従来回路の
ブロック図、第3図は同要部回路図、第4図は本考案の
一実施回路例をそれぞれ顕わす。 主な図番の説明 1・・・・・・クランプ回路、4・・
・・・・19H抜取パルス発生回路、5・・・・・・ス
イッチング回路、G・・・・・・接続点、b・・・・・
・クランプ出力、e・・・・・・抜取パルス(抜取出力
)、C・・・・・・黒レベル出力。
FIG. 1 is an explanatory diagram of the waveform of the VIR signal, FIG. 2 is a block diagram of a conventional circuit, FIG. 3 is a circuit diagram of the main part thereof, and FIG. 4 is an example of an implementation circuit of the present invention. Explanation of main drawing numbers 1... Clamp circuit, 4...
...19H sampling pulse generation circuit, 5...Switching circuit, G...Connection point, b...
- Clamp output, e... Sampling pulse (sampling output), C... Black level output.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] カラー信号を低域輝度信号とインターリ−ピング関係に
して低域変換記録すると共に再生時櫛形フィルタを介し
てカラー信号を分離して高域に再変換する方式のビデオ
テープレコーダに於て、分割抵抗の接続点を黒レベル電
位に設定すると共に、該接続点よりビテ゛オ信号線路に
順方向に接続したダイオードの順方向電圧降下を黒レベ
ルと同期先端の電位差に一致せしめたクランプ回路と、
水平同期信号を計数してVIR信号検出用の抜取パルス
を発生する19H抜取パルス発生回路と、該抜取パルス
の発生に伴ってクランプ出力に代え黒レベル出力を導出
するスイッチング回路を備え、前記クランプ回路の接続
点の電位を黒レベル出力として前記スイッチング回路に
人力することを特徴とするVIR信号除去回路。
In a videotape recorder that records a color signal in an interleaving relationship with a low-frequency luminance signal and converts it to a low frequency range, it also separates the color signal through a comb filter during playback and reconverts it to a high frequency range. a clamp circuit that sets the connection point of the connection point to a black level potential, and makes the forward voltage drop of a diode connected in the forward direction from the connection point to the video signal line equal to the potential difference between the black level and the synchronization tip;
The clamp circuit includes a 19H sampling pulse generation circuit that counts horizontal synchronizing signals and generates a sampling pulse for VIR signal detection, and a switching circuit that derives a black level output instead of a clamp output in response to the generation of the sampling pulse. A VIR signal removal circuit characterized in that a potential at a connection point of is inputted to the switching circuit as a black level output.
JP4970578U 1978-04-12 1978-04-12 VIR signal removal circuit Expired JPS5919508Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4970578U JPS5919508Y2 (en) 1978-04-12 1978-04-12 VIR signal removal circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4970578U JPS5919508Y2 (en) 1978-04-12 1978-04-12 VIR signal removal circuit

Publications (2)

Publication Number Publication Date
JPS5553371U JPS5553371U (en) 1980-04-10
JPS5919508Y2 true JPS5919508Y2 (en) 1984-06-05

Family

ID=28935791

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4970578U Expired JPS5919508Y2 (en) 1978-04-12 1978-04-12 VIR signal removal circuit

Country Status (1)

Country Link
JP (1) JPS5919508Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0136380Y2 (en) * 1981-03-04 1989-11-06

Also Published As

Publication number Publication date
JPS5553371U (en) 1980-04-10

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