JP3149695B2 - Video signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus for a video tape recorder (hereinafter abbreviated as "VTR") which uses a modulation frequency discrimination technique of a reproduction frequency modulation luminance signal.

[0002]

2. Description of the Related Art In recent years, in a consumer VTR, a luminance signal is frequency-modulated (hereinafter abbreviated as FM modulation), and a chrominance signal is recorded after being subjected to low-frequency conversion.
Signal processing is performed in which the M color is demodulated and the chrominance signal is converted back to the original frequency. Also, high-end machines can switch between multiple recording systems with different FM modulation frequencies, frequency shifts, etc., and can record on these types of tapes when signals of different recording systems are mixed on the same tape. There is. To reproduce these tapes, the recording system is automatically determined based on the reproduction signal, and the processing is performed by switching various characteristics of the reproduction processing circuit to characteristics corresponding to each recording system. For example, an S-VHS compatible VTR uses two methods, VHS recording (FM modulation frequency in a sync chip of 3.4 MHz in NTSC) and S-VHS recording (FM modulation frequency in a sync chip of 5.4 MHz), which are predecessors. Selectable recording is possible, and the recording method is automatically determined at the time of reproduction.

[0003] A VTR capable of reproducing VHS and S-VHS systems will be described below as an example of a conventional video signal processing apparatus.

FIG. 6 is a block diagram showing a part of a reproduction system luminance signal processing circuit of a conventional video signal processing apparatus.
6, 1 is an input terminal, 2 is a reproduction amplifier circuit, 3
Is a limiter circuit, 4 is a peak detector, 5 is an integrating circuit, 6
Is a comparator, 7 is an FM demodulator, 8 is a de-emphasis circuit, 9 is a synchronization separation circuit, 10 is a low-pass filter (hereinafter referred to as LPF), 11 is a reproduced luminance signal output terminal,
Reference numeral 12 denotes an output terminal for outputting a signal for determining whether the data is VHS-recorded or S-VHS-recorded (hereinafter, abbreviated as S / V determination).

The operation of the video signal processing circuit configured as described above will be described below. First, when an FM-modulated luminance signal reproduced by the video head is input from the input terminal 1, the signal is amplified by the reproduction amplifier circuit 2, the peak detector 4 performs peak detection of about 6 to 7 MHz, and the VHS is recorded. (The modulation frequency is 3.4 MHz in the VHS / NTSC system specified by the standard)
From 4.4 MHz) to S-
Those recorded by VHS (modulation frequency is 5.4 MHz to 7.0 MHz in the S-VHS / NTSC system defined by the standard) are peaked. When peaking occurs, the signal is integrated by the integrating circuit 5 and converted to a high-level voltage and output. When peaking is not performed, a low-level voltage is output. After this voltage is compared by the comparator 6, the voltage is output from the output terminal 12 and input to the FM demodulator 7.

On the other hand, the reproduced luminance signal passes through the reproduction amplifier circuit 2 and then passes through the limiter circuit 3 to be compatible with either the VHS or S-VHS system based on the comparison result of the comparator 6 by the FM demodulator 7. Demodulated as follows. Then, after being processed by the de-emphasis circuit 8 and the LPF 10, it is output from the output terminal 11 and mixed with the color signal.

FIG. 7 shows an example of a circuit diagram of the peak detector 4, the integrating circuit 5, and the comparator 6 in FIG. 7, reference numeral 50 denotes a terminal connected to a power supply, 55 denotes an input terminal,
6 is a ground (hereinafter referred to as GND), 57 is an output terminal,
C1 and C2 are capacitance elements, R1 to R8 are resistance elements, Q1
To Q6 are transistors, and L1 is an inductance.

First, when a signal recorded in S-VHS recording is reproduced, a reproduced FM modulated luminance signal is inputted from 55, passed through an emitter follower of Q1, inputted to the base of Q2, and supplied to the collector of L1. , C1 (approximately 6 to 7 MHz), the impedance of the collector increases, and the collector output voltage of Q2 decreases.
With this voltage, Q3 is turned on, and the charge charged in C2 is discharged. When the potential decreases and the base potential of Q4 falls below the base potential of Q5, Q5 turns on, and current flows to the base of Q6 and the collector flows from the collector. A high-level voltage is output.

Considering the case where a VHS-recorded signal is reproduced, the resonance frequencies of L1 and C1 (about 6M to 7M) are considered.
Hz), the collector output voltage of Q2 rises, Q3 turns off, charge is charged to C2 through R3, and the potential rises, causing Q5 to rise when the base potential of Q4 rises above the base potential of Q5. Is turned off, no current flows to the base of Q6, and the collector is opened .

[0010]

However, in the above-mentioned conventional configuration, the determination is made in the entire band of the reproduced FM modulated luminance signal. For example, when a signal with a wide band is recorded in VHS, that is, the center frequency of VHS recording Is 4.4M
When there is a carrier of 2 MHz above and below the center in Hz, the upper carrier (6.4 MHz) enters the S-VHS band (5.4 to 7 MHz), so that it is peaked and S-VHS recording is performed. Has been erroneously determined.

The present invention solves the above-mentioned conventional problems. The present invention counts the reproduction FM modulation frequency in a sync chip, and makes it possible to determine VHS recording or S-VHS recording with extremely high accuracy. It is an object to provide a signal processing device.

[0012]

In order to achieve this object, a video signal processing apparatus according to the present invention generates a first pulse having a predetermined time width from a leading edge of a horizontal synchronization pulse obtained from a synchronization separation circuit. A pulse generator, a first counter that counts a reproduced FM modulated luminance signal as a clock during a pulse period, and outputs a second pulse whose count value of the first counter is 1 to a first predetermined period. A first decoder, a crystal oscillator having a subcarrier frequency substantially as an oscillation frequency, a multiplier for increasing an output signal frequency of the crystal oscillator by a predetermined integer, and a switch circuit for passing an output signal of the multiplier through a second pulse period A second counter that counts during the first pulse period using the output signal of the switch circuit as a clock, and a second counter that decodes the output signal of the second counter. A signal generating circuit that outputs an error signal based on a decoded value of the second decoder, and an integrating circuit that integrates the signal. And the second recording method.

[0013]

With this configuration, a pulse is generated in inverse proportion to the reproduction FM modulation frequency in the sync chip, and a count value of a clock obtained by multiplying the output signal of the crystal oscillation circuit oscillating at the subcarrier frequency during this pulse period And V
It is possible to determine whether the data is HS-recorded or S-VHS-recorded.

[0014]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, 1 is an input terminal to which a reproduced video signal is input, 2 is a reproduction amplifier circuit for amplifying a signal input from the input terminal 1, 3 is a limiter circuit for limiting the amplitude of the signal amplified by the reproduction amplifier circuit 2, 7. Is an FM demodulator, 8 is a de-emphasis circuit, 9 is a sync separation circuit for separating a sync signal from a playback video signal, 10 is an LPF, 11 is a playback luminance signal output terminal, 12 is an S / V discrimination output terminal, and 13 is a pulse. A generator, 14 is a first counter, 15 is a first decoder,
Reference numeral 18 denotes a crystal oscillator (hereinafter abbreviated as VXO) which is phase-synchronized with the subcarrier of the input signal, 17 denotes a multiplier for multiplying the subcarrier signal output from the VXO 18, 16 denotes a switch circuit, 19 denotes a second counter, 20 is the second decoder, 2
1 is an S / V discrimination signal generation circuit, 22 is an integration circuit, and 23 is a comparator. In the present embodiment, VHS, S-VHS, N
In accordance with the TSC system, the multiplier 17 has a multiplier of 2.

The operation of the video signal processing device configured as described above will be described below.

First, the reproduction FM input from the input terminal 1
The modulated luminance signal is amplified by the reproduction amplifier circuit 2, processed by the limiter circuit 3, the FM demodulator 7, and the de-emphasis circuit 8, and then separated by the synchronization separation circuit 9. The obtained sync separation pulse is a signal as shown in FIG. Here, the first pulse (FIG. 2B) having a width of 50 μsec from the leading edge of the horizontal synchronization pulse is generated for each horizontal synchronization pulse except the vertical blanking period. In the pulse period of the first pulse, the measurement is started by releasing the reset of the first counter 14, the second counter 19, and the S / V discrimination signal generation circuit 21, respectively. Note that FIG.
FIG. 2C is an enlarged view of one pulse in FIG.

When the reset is released, the first counter 14 receives the reproduced frequency modulated luminance signal (FIG. 2d), which is the output signal of the limiter 3, and starts counting the number of rising edges. In the period 2c), the second pulse (FIG. 2e) is created by the first decoder 15 until the number of edges becomes nine. That is, FM
A second pulse having a time width nine times as long as one cycle of the modulation frequency is created. The second pulse is input to the switch 16.

On the other hand, the subcarrier signal (about 3.58 MHz) output from the VXO 18 is
After being multiplied (approximately 7.16 MHz) (FIG. 2f), it is mixed with the second pulse by the switch 16 and the number of rising edges of the subcarrier signal in the second pulse period (FIG. 2e) is counted by the second counter 19. To count. The counted number of edges is decoded by the second decoder 20, and S / V
It is input to the discrimination signal generation circuit 21.

Here, in the S / V discrimination signal generation circuit 21, the second decoded value (the number of edges of the sub-carrier signal) is not less than the first predetermined value (12) and not more than the second predetermined value (13). At the time, an S-VHS determination signal is generated, and when the second decoded value is equal to or more than the third predetermined value (18) and equal to or less than the fourth predetermined value (20), a VHS determination signal is generated. In the case of FIG. 2, since the number of edges of the subcarrier signal (FIG. 2F) is 18, VH
An S discrimination signal is generated.

When the input video signal is S-VHS, the FM modulation frequency in the sync chip is 5.4.
MHz, which is higher than 3.4 MHz of VHS, the second pulse width (FIG. 2e) created by the first decoder 15 is shorter than VHS. Therefore, the number of edges of the subcarrier signal generated between the second pulses is reduced.

The discrimination signal is integrated by an integrating circuit 22, VHS is converted to a voltage of 0V, and S-VHS is converted to a voltage of 5V. After comparing the voltages by a comparator 23, the comparison result is output from an output terminal 12. I do. At the same time, the comparator 23
Is not input to the FM demodulator 7, the output signal of the limiter 3 is demodulated as it is, and is output from the output terminal 11 via the de-emphasis 8 and the LPF 10 to output a color signal. Mixed. Also, if the determination result is S-VHS, that corresponds to the S-VHS voltage,
That is, a voltage of 5 V is input to the FM demodulator 7 and the S-V
Is demodulation in the demodulation sensitivity corresponding to HS, via a de-emphasis circuit 8 and LPF 10, is output from the output terminal 11 is mixed with the color signal.

Hereinafter, the present embodiment will be described in detail with reference to a circuit diagram. FIG. 3 shows the first counter 14 of the present embodiment,
FIG. 2 shows a circuit diagram of a first decoder 15, a switch circuit 16, a second counter 19, and a second decoder 20.

In FIG. 3, reference numerals 30 and 31 denote output terminals,
2 to 34 are input terminals, G1 to G4 are T-type flip-flops, G5 to G7 are NAND elements, G8 is D-type flip-flops, G9 to G13 are T-type flip-flops, G14 to G17 are AND elements, G18
G21 is an inverter, G22 is an OR element, and G23 is
It is a NOR element.

The output signal of the limiter 3 is connected to the input terminal 32, and a clock of about 7.16 MHz, which is twice the subcarrier, is input from the multiplier 17 to the input terminal 33. To the input terminal 34, a pulse which is an output signal of the pulse generation circuit 13 and is at a high level for 50 μs from the leading edge of the horizontal synchronization pulse is input. When the input terminal 34 is at a low level, the flip-flops G1 to G4 and G8 to G13 are in a reset state. Therefore, N
The outputs of the AND elements G6 and G7 are at a high level, and the switch circuit 16 is off.

The operation of the embodiment constructed as described above will be described below. In the horizontal synchronization period,
The input terminal 34 becomes high level, and reset of all flip-flops is released. Since the output of the NAND element G6 is at a high level, the first counter 14 counts the number of rising edges of the FM modulated wave input from the input terminal 32 after reset release. On the other hand, D
Since the D input of the type flip-flop G8 is at the high level, the D-type flip-flop G8 is set at the first rising edge of the FM modulation wave after the reset is released, and the Q output becomes the high level. This allows input terminal 3
The clock of the subcarrier signal (7.16 MHz) input from 3 is counted by the second counter 19 via the NAND element G7.

When the count number of the first counter 14 is 9 (T
When the type flip-flops G1 to G4 become “1001”, the output of the NAND element G6 becomes low level, and the clock is not input to the first counter 14 by the NAND element G5. On the other hand, since the D input of the D-type flip-flop G8 becomes low level,
Next rising edge of FM modulated wave (1 after reset release)
At the (0th pulse), the Q output becomes low level, and the switch circuit 16 constituted by the NAND element G7 is turned off.
Therefore, the switch circuit 16 is turned on from the first rising edge of the FM modulation wave to the rising edge of the tenth pulse after reset release, and passes the clock of the subcarrier signal for a period of nine times one cycle of the FM modulation wave. It will be.

The value counted by the second counter 19 is decoded by the second decoder 20, and the decoded value becomes the first predetermined value (12 = G9 to G13 is "01100").
As described above, the second predetermined value (13 = G9 to G13 is “0110
1)), the output terminal 31 goes high, the output terminal 30 goes low, and the S-VHS determination is made. The decoded value is a third predetermined value (18 = G9 to G
13 is equal to or greater than “10010” and is a fourth predetermined value (20 = G
When 9 to G13 are "10100" or less, the output terminal 30
Is at a high level, the output terminal 31 is at a low level, and a VHS determination is made.

FIG. 4 shows an example of a circuit diagram of the S / V discrimination signal generation circuit 21. In FIG. 4, 34 and 40 to 42 are input terminals, 43 , 44 and 45 are output terminals, the input terminal 40 is the output terminal 30 of FIG. 3, the input terminal 41 is the output terminal 31 of FIG. The terminal 34 is connected to a pulse rising at the rising edge of the horizontal synchronizing pulse, and resets the D-type flip-flops G31 and G32 constituting the output latch of the non-pulse section error pulse. Further, a pulse (burst section detection pulse) which is synchronized with the horizontal synchronization pulse and rises with a delay of several μs from the horizontal synchronization pulse is input to the input terminal 42.

The operation of the S / V discrimination signal generating circuit having the above-described configuration will be described below.

When the decoded value of the second counter 19 is equal to or more than the third predetermined value (18) and equal to or less than the fourth predetermined value (20), the input terminal 40 becomes high level and the D-type flip-flop G31 receives the D signal. When the input goes high and the pulse input from the input terminal 42 falls, the output terminal 4
3 becomes high level and 45 becomes its inverted output. When the decoded value of the second counter 19 is equal to or more than the first predetermined value (12) and equal to or less than the second predetermined value (13), the input terminal 41 becomes high level, and the D input of the D-type flip-flop G32 becomes low. The output terminal 44 becomes high level when the pulse inputted from the input terminal 42 falls to a high level.

Accordingly, by setting the output terminals 43 and 45 to signal outputs determined to be VHS recording and output terminals 44 to signal outputs determined to be S-VHS recording, the S / V determination signal generation circuit 21 When the decoded value of the counter 19 is equal to or more than the third predetermined value (18) and equal to or less than the fourth predetermined value (20), V
A signal determined to be HS recording is output, and a signal determined to be S-VHS recording when the decoded value of the second counter is equal to or more than the first predetermined value (12) and equal to or less than the second predetermined value (13) is integrated by the integration circuit 22. Output to

FIG. 5 shows an example of a circuit diagram of the integration circuit 22. In FIG. 5, reference numeral 50 denotes a terminal connected to a power supply, to which a voltage of 5 V is input. 51 is an input terminal to which the output terminal 44 in FIG. 4 is connected, 52 is an input terminal to which the output terminal 45 in FIG. 4 is connected, 53 is ground (hereinafter referred to as GND), 54 is an output terminal, R10 to R17 are resistance elements, C10 is a capacitance element, and Q10 to Q1
4 is a transistor.

The operation of the integrating circuit configured as described above will be described below. First , Q10, Q
11 constitutes a push-pull circuit, the input terminal 51
When 52 to the high level of the signal (S over VHS discrimination) is entered if, integrates the output of its in R12 and C10, Q12
Becomes higher than the base potential of Q14 and Q1
2 is turned on, and a high-level signal (a voltage of 5 V) is output to the comparator 23 at the output terminal 54.

When a low level signal (VHS determination) is input to the input terminals 51 and 52, the base potential of Q12 becomes lower than the base potential of Q14, and Q13
An open signal is output to the comparator 23 at the FF output terminal 54.
Is output.

The voltage input from the integrating circuit is checked by the comparator 23. If the voltage is open, no signal is input from the comparator 23 to the FM demodulator 7 and the FM modulated signal from the limiter 3 is demodulated as it is. Then, it is input to the de-emphasis circuit 8. If the voltage is 5 V, the voltage is FM
The FM modulated signal from the limiter 3 is input to the demodulator 7, demodulated as S-VHS, and input to the de-emphasis circuit 8.

[0037]

As is apparent from the above description, according to the present invention, the reproduction FM modulation frequency in the sync chip is counted, and it is determined whether the data is VHS-recorded or S-VHS-recorded. It is possible to realize an excellent video signal processing device that can eliminate erroneous determination as in the related art.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a video signal processing device according to the present invention.

FIG. 2 is a characteristic diagram of each unit in the video signal processing device according to the embodiment;

FIG. 3 is a circuit diagram of a first counter, a first decoder, a switch circuit, a second counter, and a second decoder in the embodiment.

FIG. 4 is a circuit diagram of an S / V discrimination signal generation circuit in the embodiment.

FIG. 5 is a circuit diagram of an integrating circuit in the embodiment.

FIG. 6 is a block diagram of a conventional video signal processing device.

FIG. 7 is a circuit diagram of a conventional S / V discrimination circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2 Reproduction amplifier circuit 3 Limiter circuit 7 FM demodulator 8 Deemphasis circuit 9 Synchronization separation circuit 10 LPF 11 Reproduction luminance signal output terminal 12 S / V discrimination signal output terminal 13 Pulse generation circuit 14 First counter 15 First 16 Switch circuit 17 Multiplier 18 VXO 19 Second counter 20 Second decoder 21 S / V discrimination generation circuit 22 Integration circuit 23 Comparator

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/91-5/956 H04N 9/79-9/898

Claims (2)

(57) [Claims] 1. A frequency-modulated luminance signal obtained by frequency-modulating a luminance signal and a low-frequency converted chrominance signal obtained by frequency-converting a carrier chrominance signal to a low frequency band are respectively frequency-division multiplexed and recorded and reproduced.
A video signal processing device capable of reproducing signals recorded by a first recording method and a second recording method in which a modulation frequency of a luminance signal is different, wherein a predetermined amount is determined from a front edge of a horizontal synchronization pulse obtained by a synchronization separation circuit. A pulse generator that generates a first pulse having a time width, a first counter that counts a reproduction frequency-modulated luminance signal as a clock during the period of the first pulse, and a count value of the first counter is first. A first decoder that outputs a second pulse corresponding to a predetermined period of time, a crystal oscillator having a subcarrier frequency substantially as an oscillation frequency, a multiplier that increases the output signal frequency of the crystal oscillator by a predetermined integer, a switch circuit for the output signal of the multiplier is passed through the second pulse period, a second that counts the first pulse period as the clock output signal of said switching circuit A counter, a second decoder that decodes an output signal of the second counter, and a signal generator that outputs a determination signal corresponding to the first recording method or the second recording method based on a decoded value of the second decoder. Circuit, and an integrating circuit for integrating the discrimination signal, wherein the reproduction frequency modulated luminance signal is recorded by a first recording method or recorded by a second recording method by an output signal of the integrating circuit. A video signal processing device configured to determine whether a signal is a signal. 2. The signal generating circuit according to claim 1, wherein the decoded value of the second decoder is smaller than a first predetermined value, larger than a second predetermined value and smaller than a third predetermined value, and larger than a fourth predetermined value. In this case, the discrimination signal is not output.If the signal is not less than the first predetermined value and not more than the second predetermined value, the discrimination signal corresponding to the first recording method is output. 2. The video signal processing device according to claim 1, wherein a determination signal corresponding to the second recording method is output when the value is equal to or less than the fourth predetermined value.