JP3282441B2 - Video signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus used for a video tape recorder (hereinafter, abbreviated as VTR), and more particularly to a technique for a dropout compensation circuit.

[0002]

2. Description of the Related Art In recent years, in a consumer VTR, a luminance signal is frequency-modulated (hereinafter abbreviated as FM modulation), and a chrominance signal is recorded after being subjected to low-frequency conversion.
Signal processing is performed in which the M color is demodulated and the chrominance signal is converted back to the original frequency.

An example of a conventional video signal processing device will be described below. FIG. 4 is a block diagram showing a part of a conventional video signal processing apparatus. In FIG. 4, 1 is an input terminal, 2 is a double limiter circuit, 3 is an FM demodulator, 4 is a de-emphasis circuit, 5 is a first low-pass filter (hereinafter abbreviated as LPF), and 6 is a dropout compensation circuit. , 7 is a dropout detector, 8 is a detection circuit, 9
Is an amplitude detector, 10 is a switch circuit, 11 is a sync separation circuit, 12 is a luminance / color signal mixer, 13 is an output terminal, 21
Is a second LPF, 22 is an automatic gain control circuit (hereinafter, AC
Abbreviated as C. ) And 23 are first balanced modulators, 24 is a bandpass filter (hereinafter abbreviated as BPF), 25.
A comb filter, 26 is a third LPF, 27 is a second balanced modulator, 28 is a first frequency divider, 29 is a voltage controlled oscillator (hereinafter abbreviated as VCO), and 30 is a phase comparator. , 31 are a second frequency divider, 32 is a crystal oscillator, and 33 is a frequency detector.

[0004] The operation of the reproduced video signal processing circuit configured as described above will be described below.

In the luminance signal processing, a reproduced FM signal is inputted from a tape / head system from an input terminal 1, the amplitude is adjusted in a double limiter circuit 2, and then inputted to an FM demodulator 3. The signal demodulated here is supplied to a de-emphasis circuit 4 and a first LPF for limiting a luminance signal band.
5, and is returned to the luminance signal.
Is input to On the other hand, the dropout detector 7 outputs a dropout pulse during a section where the amplitude of the reproduced FM signal is equal to or less than the first predetermined value, and is input to the dropout compensation circuit 6 via the switch circuit 10. Here, drop-out compensation is performed by replacing the image signal with a video signal delayed by one horizontal synchronization period in a drop-out pulse section, a CCD, a line memory, or the like. In a noise screen such as a non-recording tape playback, if dropout compensation is performed, the dropout compensation operates continuously for a long time, resulting in a very uncomfortable screen.
, A long time constant is detected, and the amplitude detector 9 detects a no-signal state by comparing with a second predetermined value, and turns off the switch circuit 10 to stop the dropout compensation.

In the color signal processing, the low-pass conversion color signal superimposed on the reproduced FM signal input from the input terminal 1 is extracted by the second LPF 21, the burst amplitude is made uniform by the ACC circuit 22, and then the first Are input to the balanced modulator 23. Here, after being converted to the color subcarrier frequency by the balance modulation, the BPF 24 having the color subcarrier frequency as a pass band is used.
Then, the color signal is demodulated through the comb filter 25. On the other hand, the VCO 29 is controlled by the phase comparator 30 and the frequency detector 33, and oscillates at a first predetermined integer multiple of the sum of the low-band conversion color frequency and the color subcarrier frequency. The frequency is divided by a frequency divider 28 into a first predetermined integer and input to the balanced modulator 23.

FIG. 5 shows an example of a circuit diagram of a conventional dropout detector, detection circuit, amplitude detector, and switch circuit. In FIG. 5, Q1 to Q12 are transistors, R
1 to R17 are resistors, C1 to C3 are capacitors, I1
To I7 are current sources, 40 is an input terminal, and 41 is an output terminal. The input terminal 40 receives a reproduced FM signal that has passed through a double limiter circuit. This signal is amplified by an operational amplifier composed of Q3 and Q4, and then full-wave rectified by Q5 and Q6. This signal is input to an integrating circuit composed of R8 and C2 and an integrating circuit composed of R17 and C3. Since C2 has a small capacitance value and a fast integration time constant, C2 operates as peak detection. The potential of C2 is R
Q10, Q, the first predetermined value made by R14 and R15
A pulse which becomes high when the potential of C2 is low is output through Q12 after being compared by the comparison circuit constituted by 11. On the other hand, since C3 has a large capacity, it cannot respond to the lack of a reproduced FM signal due to a normal dropout or an instantaneous input due to noise when there is no reproduced FM signal. Therefore, this potential is set to the second predetermined voltage generated by R10 and R11. Value and Q7, Q8
Are compared. When there is no signal, Q9 is turned on.
The output of the output terminal 41 can be turned off (low level) regardless of the output of Q12.

The above operation will be described in detail below with reference to the waveform diagram of FIG. FIG. 6A shows an envelope waveform of the reproduced FM signal input from the input terminal 40. FIG. 6B shows the potential of C2 obtained by peak detection of this waveform. In the figure, V1 is a first predetermined value created by R14 and R15. The result of comparison with this potential is shown in FIG. In this state, a high level (dropout state) is always detected in a non-input state, and also responds to an instantaneous input (waveform A in FIG. 6A) due to noise or the like. On the other hand, the potential of C3 is shown in FIG. In the figure, V2 is R1
0 and R11, which are the second predetermined values, and the result of comparison with this potential is shown in FIG. In this waveform, the normal dropout and the effect of the waveform A in FIG. 6A are eliminated, and by switching the waveform in FIG. 6C with this pulse, the output in FIG. And output from the output terminal 41. As is clear from the waveform of FIG. 6H, in the non-input state exceeding the maximum dropout compensation period width W usually set to several hundred μs, the dropout compensation pulse is off.

[0009]

However, in the above-mentioned conventional configuration, a time constant of about several hundred μs is required for the detection circuit in order to detect the reproduction no-signal state, so that the capacitance of the capacitor of the detection circuit is large. It is difficult to incorporate the IC. For this reason, the IC has a problem that it is necessary to provide a dedicated pin and connect a detection capacitor externally.

The present invention solves the above-mentioned conventional problems. In order to detect a reproduction no-signal state without a detection circuit,
It is an object of the present invention to provide a video signal processing device that can easily incorporate an IC.

[0011]

In order to achieve the above object, a video signal processing apparatus according to the present invention comprises a dropout detection device for outputting a first pulse when the amplitude of a reproduced FM signal is at most a first predetermined value. And an amplitude detector that outputs a second pulse when the amplitude of the reproduced FM signal is at least a second predetermined value. A non-pulse section of the second pulse is reset when a pulse having a substantially horizontal synchronization frequency is input as a clock. A second counter, a second decoder that outputs a fourth pulse when the count value of the second counter is less than a fourth predetermined value,
A pulse having a substantially horizontal synchronization frequency as a clock input, a first counter that is reset during a non-pulse period of a fourth pulse, and a third pulse when the count value of the first counter is less than a third predetermined value. A first decoder that outputs
A switch circuit that receives the first pulse and passes only the pulse section of the third pulse, and a demodulated luminance signal that receives the demodulated luminance signal and is delayed by one horizontal synchronization period that is the pulse period of the output pulse of the switch circuit. It is configured by a dropout compensation circuit that performs dropout compensation by replacement.

[0012]

With this configuration, during the period in which the pulses of the substantially horizontal synchronizing frequency obtained from the reproduction color signal processing circuit are respectively counted for a predetermined number, the reproduction FM signal is continuously present or absent, or reproduced without a large-capacity capacitor. The presence or absence of the FM signal can be detected, and the O
N and OFF can be switched.

[0013]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, 1 is an input terminal, 2 is a double limiter circuit, 3 is an FM demodulator, 4 is a de-emphasis circuit, 5
Is a first LPF, 6 is a dropout compensation circuit, 7 is a dropout detector, 9 is an amplitude detector, 10 is a switch circuit, 11 is a sync separation circuit, 12 is a luminance / color signal mixer, and 13 is an output terminal. , 14 is a first counter, 15 is a first decoder, 16 is a second counter, 17 is a second decoder, 21 is a second LPF, 22 is an ACC, 23 is a first balanced modulator, 24 Is a BPF, 25 is a comb filter, 26 is a third LPF, 27 is a second balanced modulator, 2
8 is a first frequency divider, 29 is a VCO, 30 is a phase comparator,
31 is a second frequency divider, 32 is a crystal oscillator, and 33 is a frequency detector. The difference from the prior art FIG. 4 is that the detection circuit which requires a large-capacity capacitor is deleted, and
, A first decoder, 15 second decoders, 16 second counters, and 17 second decoders.

The operation of the video signal processing device configured as described above will be described below. A reproduction FM signal is input from an input terminal 1 from a tape / head system, and the amplitude is adjusted in a double limiter circuit 2.
Is input to The signal demodulated here is supplied to a de-emphasis circuit 4 and a first LPF 5 for limiting a luminance signal band.
, And is input to the dropout compensation circuit 6. On the other hand, the dropout detector 7 outputs a first pulse during a section in which the amplitude of the reproduced FM signal is equal to or less than the first predetermined value. Out compensation is made. Further, the amplitude detector 9 outputs a second pulse during a section where the amplitude of the reproduced FM signal is equal to or larger than a second predetermined value. Each of the first counter 14 and the second counter 16 receives a pulse of a substantially horizontal synchronization frequency obtained by color signal processing as a clock, and outputs a non-pulse section of the second pulse obtained by the amplitude detector 9. Then, when the count of the first counter advances, and the first decoder decodes the third predetermined value or more, the switch circuit 10 is turned off. As a result, it is possible to stop the dropout compensation in a state where the reproduced FM signal is not input. When the second pulse rises, the second counter 16 starts counting. By resetting the first counter only when the pulse period of the second pulse is continuous until the second decoder 17 decodes the fourth predetermined value or more, noise or the like in a reproduction FM non-input state or the like is obtained. Prevents the no-input detection state from being reset by mistake.

FIG. 2 shows a dropout detector, an amplitude detector, a first counter, a first decoder,
FIG. 4 shows an example of a circuit diagram of a switch circuit, a second counter, and a second decoder. In FIG. 2, Q1 to Q12 are transistors, R1 to R16 are resistors, C1 to C2 are capacitors, I1 to I7 are current sources, G1 to G3 are AND elements, G4 to G5 are NAND elements, and G6 to G11 are D.
A type flip-flop, 40 is an input terminal, and 41 is an output terminal. In this circuit diagram, the circuits of the dropout detector and the amplitude detector are partially shared.

The input terminal 40 receives a reproduced FM signal that has passed through a double limiter circuit. This signal is Q3, Q
Q5, Q6 after being amplified by the operational amplifier composed of
Is full-wave rectified. This signal is peak-detected by an integrating circuit composed of R8 and C2. The potential of C2 is R
Q10, Q, the first predetermined value made by R14 and R15
A pulse which becomes high when the potential of C2 is low is output through a switch circuit composed of AND elements of G3, which is compared by a comparison circuit composed of G3. Also, C
And the second predetermined value generated by R10 and R11 and Q
7, a pulse which becomes high when the potential of C2 is high is output. A pulse having a substantially horizontal synchronization frequency is input from the input signal 42 from the color signal processing circuit.
1, a first counter consisting of G6 to G9;
2. The clock is input to a second counter composed of G10 to G11. G4 constitutes a first decoder, and decodes "8" as a third predetermined value. G5 constitutes a second decoder, and decodes "3" as a fourth predetermined value. When the dropout occurs, the output of the amplitude detector 9 becomes low level, and the flip-flops G10 and G11 are reset. Therefore, the output of G5 becomes high level, the reset of the flip-flops G6 to G9 is released, and the first counter starts counting. When the drop-out state is maintained, the count is advanced. When "8" is counted, the output of G4 becomes low level, and the gate of G3 constituting the switch circuit is closed. When the reproduced FM signal is input, the output of the amplitude detector 9 becomes high level, so that the reset of the flip-flops G10 and G11 is released, and the count of the second counter starts. When the second counter counts 3, the output of G5 goes low, the first counter is reset, the output of G4 goes high, and the gate of G3 opens. Also, if the second counter enters the drop-out state again before counting "3", the second counter is reset.
The output of 5 remains high, and the first counter is not reset.

The above operation will be described in detail below with reference to the waveform diagram of FIG. FIG. 3A shows an envelope waveform of the reproduced FM signal input from the input terminal 40. FIG. 3B shows the potential of C2 obtained by peak detection of this waveform. In the figure, V1 is a first predetermined value created by R14 and R15. The result of comparison with this potential is shown in FIG. In this state, a high level (dropout state) is always detected in a non-input state, and also responds to an instantaneous input (waveform A in FIG. 3A) due to noise or the like. On the other hand, V2 shown in FIG. 3B is a second predetermined value formed by R10 and R11, and the result of comparison with this potential is shown in FIG.
(D). In this waveform, as in FIG. 3C, a low level is always detected in the non-input state, and instantaneous input due to noise or the like (waveform A in FIG. 3A)
Is also responding. FIG. 3E shows a pulse having a substantially horizontal synchronization frequency input from the input terminal 42. The waveform output from the second decoder G5 at the time of these inputs is shown in FIG.
(F) of FIG. 3 shows a waveform output from the first decoder G4 in (g) of FIG. According to FIG. 3G, FIG.
Are switched by G3, and finally the pulse shown in FIG. 3 (h) is output as a dropout pulse. FIG.
As can be seen from FIG.
Therefore, the maximum dropout compensation section W is a period (about 44 times) of 7 to 8 times the cycle of the pulse of the substantially horizontal synchronization frequency.
5 μs to 508 μs), and it is possible to perform switching for several hundred μs without using a large-capacity capacitor. Also, since the decode value of the second decoder is “3”,
The input of the reproduced FM signal less than twice to three times (127 μs to 131 μs) the period of the pulse of the substantially horizontal synchronization frequency such as the waveform A in FIG. 3A can be removed at the output.

[0019]

As described above, the present invention provides a dropout detector that outputs a first pulse when the amplitude of a reproduced FM signal is equal to or less than a first predetermined value, An amplitude detector that outputs a second pulse when the value is equal to or more than a value, a second counter that is reset by resetting a non-pulse section of the second pulse using a pulse of a substantially horizontal synchronization frequency as a clock input, and a count value of the second counter A second decoder that outputs a fourth pulse when is less than a fourth predetermined value, a pulse having a substantially horizontal synchronization frequency as a clock input, and a first counter that is reset during a non-pulse period of the fourth pulse, A first decoder that outputs a third pulse when the count value of the first counter is less than a third predetermined value, and a switch circuit that receives the first pulse as an input and passes only the pulse section of the third pulse And Reproduction without large-capacity capacitors by using a dropout compensation circuit that receives a luminance signal as input and replaces the pulse period of the output pulse of the switch circuit with a demodulated luminance signal delayed by one horizontal synchronization period and performs dropout compensation Since the non-input detection of the FM signal can be performed, an excellent effect that the number of dedicated pins for the external capacitor can be reduced in the case of an integrated circuit can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a video signal processing device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a dropout detector, an amplitude detector, a first counter, a first decoder, a switch circuit, a second counter, and a second decoder according to one embodiment of the present invention.

FIG. 3 is a waveform chart in the video signal processing device according to one embodiment of the present invention;

FIG. 4 is a block diagram of a part of a conventional video signal processing device.

FIG. 5 is a circuit diagram of a dropout detector, a detection circuit, an amplitude detector, and a switch circuit in a conventional video signal processing device.

FIG. 6 is a waveform diagram in a conventional video signal processing device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2 Double limiter circuit 3 FM demodulator 4 Deemphasis circuit 5 First LPF 6 Dropout compensation circuit 7 Dropout detector 8 Detection circuit 9 Amplitude detector 10 Switch circuit 11 Synchronous separation circuit 12 Addition circuit 13 Output terminal 14 First Counter 15 First Decoder 16 Second Counter 17 Second Decoder 21 Second LPF 22 ACC 23 First Balanced Modulator 24 BPF 25 Comb Filter 26 Third LPF 27 Second Balance Modulator 28 First frequency divider 29 VCO 30 Phase comparator 31 Second frequency divider 32 Crystal oscillator 33 Frequency detector

Claims (1)

(57) [Claims] 1. A crystal oscillator having a color subcarrier frequency substantially as an oscillation frequency, and a voltage control for oscillating with a first predetermined integer multiple of a sum of a low-band carrier color frequency and the color subcarrier frequency as a substantially center frequency. An oscillator, a first frequency divider for dividing an output signal of the voltage controlled oscillator to a first predetermined integer, and an output signal of the first frequency divider and an output signal of the crystal oscillator. A balanced modulator that performs balanced modulation; a low-pass filter that uses only the low-band carrier chrominance frequency in the output signal components of the balanced modulator as a pass band; and divides the output signal of the low-pass filter into a second predetermined integer. And a second frequency divider that outputs a pulse having a substantially horizontal synchronization frequency and a second frequency divider, wherein the amplitude of the reproduced frequency modulation luminance signal is at most a first predetermined value, Dropout detector that outputs pulses An amplitude detector that outputs a second pulse when the amplitude of the reproduction frequency modulation luminance signal is at least a second predetermined value; and a non-pulse of the second pulse with the pulse having the substantially horizontal synchronization frequency as a clock input. A second counter that is reset in a section, a second decoder that outputs a fourth pulse when a count value of the second counter is less than a fourth predetermined value, and a clock of the pulse having the substantially horizontal synchronization frequency. A first counter that is reset as a non-pulse period of the fourth pulse as an input, and a first decoder that outputs a third pulse when the count value of the first counter is less than a third predetermined value. A switch circuit that receives the first pulse as an input and is in a pass state only in a pulse section of the third pulse, and receives a demodulated luminance signal as an input and outputs a pulse during a pulse period of an output pulse of the switch circuit. A video signal processing apparatus characterized by being constituted by a dropout compensation circuit for performing dropout compensated by substituting one horizontal synchronizing period delayed demodulated luminance signal was that.