JPS6251015B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is designed to generate a clock signal synchronized with a PCM signal reproduced from a magnetic tape or video disk.

Such a clock signal is required to extract data from a reproduced PCM signal that contains time base variations. FIG. 1 shows an example of a conventional clock signal forming circuit, in which a PCM signal reproduced from, for example, a magnetic tape is supplied to an input terminal indicated by 1. This PCM signal has a signal format similar to that of a television signal, and is compatible with existing VTRs.
(video tape recorder), and one horizontal section corresponding to 168 bits defined by the synchronization signal HD corresponding to the horizontal synchronization signal has the signal arrangement shown in Figure 2. has been done. That is, after 13 bits of synchronization signal period, 13
A back pouch worth a bit is located, followed by 4
A bit data synchronization signal DS is inserted, followed by a total of 6 sampling words (14
A data block consisting of a 2-word error correction word (14 bits), P and Q, and a 16-bit error detection (CRC) code is arranged, followed by a front porch corresponding to 10 bits that corresponds to the white level. A reference signal WR with a peak value is inserted.

The reproduced PCM signal supplied from the input terminal 1 is supplied to the synchronization separation circuit 2, and the synchronization signal HD is separated. This synchronization signal HD is supplied to the AFC circuit 3. AFC circuit 3 uses synchronization signal HD and 1/N frequency divider 4
The phase comparator 6 compares the phase with the output of the VCO (voltage controlled oscillator) 5 which is passed through the oscillator.
The configuration is such that it is supplied to the VCO 5 as a control voltage. The AFC circuit 3 generates a signal with the same time axis fluctuation as the reproduced signal and a frequency of Nfh (fh is the horizontal frequency), which is supplied to the 1/n frequency divider 8.
A clock signal with a frequency (bit frequency) of N/nfh is formed. Furthermore, by supplying the horizontal synchronization signal HD from the synchronization separation circuit 2 to the frequency divider 8 as a reset pulse, a clock signal with more accurate synchronization is generated.

A reproduced PCM signal from the input terminal 1 is supplied to the data separation circuit 9, where the signal is amplitude-separated and supplied to the (0, 1) discrimination circuit 10. A clock signal formed as described above is supplied to this discrimination circuit 10, and data is extracted.
This data is supplied to a decoder 11 that performs error detection, error correction, PCM demodulation, etc., and a reproduced audio signal is obtained at its output terminal 12.

In the above configuration, the clock signal generated by the AFC circuit 3 uses a synchronization signal with a horizontal period, and has low accuracy in tracking time axis fluctuations, and at the end of the horizontal period, the data This has the drawback that a difference occurs between the clock signal and the clock signal, making it impossible to extract data correctly. This drawback cannot be eliminated even by resetting the frequency divider 8 with a synchronizing signal.

SUMMARY OF THE INVENTION An object of the present invention is to provide a clock signal forming circuit which eliminates such drawbacks and is capable of generating a clock signal highly precisely synchronized with a reproduced signal.

Hereinafter, one embodiment of the present invention will be described with reference to FIG. In this example, the present invention is applied when a PCM signal having a signal arrangement as shown in FIG. ) is supplied to the discrimination circuit, and (0, 1)
It is adapted to form a clock signal for the discrimination circuit.

The AFC circuit 3 in FIG. 3 has the same configuration as in FIG.
The HD generates an output with a frequency of Nfh' (1+δ). Here, δ represents an error between the reproduced signal and the reproduced signal. A signal with a frequency of Nfh is generated by the crystal oscillator 13, and this and the output of the AFC circuit 3 are supplied to the frequency converter 14, and the output is passed through the bandpass filter 15 to generate a signal of N[fh
+fh'(1+δ)] is obtained.

Further, a reproduced PCM signal is supplied from the terminal 17 to the gate circuit 16 . As shown in Fig. 2, the gate circuit 16 is designed to open the gate only in the period of the data synchronization signal DS, which is [100, 10], and an intermittent signal with a frequency of Nfh' appears at its output. , to the converter 18. The output of the VCO 19 is supplied to this converter 18 . Further, the output of the converter 18 is supplied to a phase comparator 21 via a bandpass filter 20,
The comparison output is passed through the low-pass filter 22.
It is supplied to the VCO 19 as a control voltage. VCO1
9 forms a signal with a frequency of N [fh + fh'δ], and the output of the bandpass filter 20 has a frequency of N
A signal with a frequency of [fh+fh'(1+δ)] will appear.

Since the VCO 19 is controlled by the comparison output of the phase comparator 21, the output of the VCO 19 includes the error component δ contained in the output of the AFC circuit 3. Therefore, by supplying the output of the VCO 19 and the output of the bandpass filter 15 to the converter 23, a frequency conversion of {N[fh+fh′(1+δ)]−N[fh+fh′δ]} is performed, Does not include error component δ
A clock signal of Nfh' will appear at output terminal 24. By multiplying this clock signal by n times, a clock signal at the bit clock frequency can be obtained.

Note that a gate circuit for extracting the data synchronization signal DS may be provided on the output side of the frequency converter 18. Furthermore, the connection positions of the crystal oscillator 13 and the tuning circuit 16 may be switched with respect to the converters 14 and 18.

As understood from the description of one embodiment above,
According to the present invention, the AFC error component is detected by comparing the phases of the clock signal formed by the AFC circuit and the data synchronization signal separated from the reproduced signal, and is further frequency-converted. Since the error component is cancelled, the reproduced PCM
It is possible to form a clock signal that is highly precisely synchronized with the clock signal, and it is possible to extract reproduced data without error.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a PCM signal reproducing circuit, FIG. 2 is a schematic diagram showing an example of a signal arrangement of PCM signals, and FIG. 3 is a block diagram of an embodiment of the present invention. 3 is the AFC circuit, 13 is the crystal oscillator, 14,1
8 and 23 are converters, 19 is a VCO, and 21 is a phase comparator.

Claims (1)

[Claims] 1 Synchronization signal and data synchronization signal added
Regenerate the PCM signal and separate the above synchronization signal.
forming a first signal by mixing the output of the AFC circuit with a predetermined oscillator output; taking the data synchronization signal and combining the data synchronization signal with the output of the voltage controlled oscillator forming a second signal by mixing said first signal;
and a second signal, the voltage controlled oscillator is controlled by the comparison output, and a clock synchronized with the reproduced PCM signal is generated by mixing the first signal and the output of the voltage controlled oscillator. A clock signal forming circuit that forms signals.