JP3263890B2 - Synchronous signal extraction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing signal extracting device applied to, for example, a MUSE signal reproducing device for extracting a synchronizing signal contained in a reproducing signal from a recording medium.

[0002]

2. Description of the Related Art Hi-vision signals are recorded,
As a method of band compression at the time of transmission, MUSE (m
ultiple sub-Nyquist sampling encoding) system has been proposed. The baseband signal bandwidth of the HDTV system is 22 MHz for the luminance signal and 7 MHz for each of the two color difference signals. MUSE can compress this baseband signal to a bandwidth of about 8 MHz.

MU formed by MUSE encoder
FIG. 15 shows the transmission format of the SE signal. The MUSE signal is
It is a kind of pulse amplitude modulation signal and has a line number [1-1
125] and the sample numbers [1-480] in each line define signal assignment. The sampling frequency is 16.2 MHz.

As shown in FIG. 15, the sample numbers [1 to 12] of each line are horizontal synchronizing signals (HD). The horizontal synchronizing signal has a waveform as shown in FIG. That is, the waveform is an 8-bit quantization level and has a level of (64 to 192), and the first and 2n-th lines (where n ≧ 2) and the second and 2n + 1-th lines (where, n ≧ 1), the waveform is inverted. Sample number [6] is the horizontal reference phase point. This horizontal reference phase point is a point at which the sampling phase is detected when resampling is performed.

[0005] A VIT (vertical interval test) signal and a frame pulse for vertical synchronization are inserted into the first and second lines of the MUSE signal. The VIT signal is a reference signal for equalizing the transmission path. further,
The edge of the 473 samples in the second line is set as the frame reference phase point.

The details of the assignment of the C signal, the Y signal, and the voice / data are not particularly relevant to the present invention.
Shows the format of the assignment, and a description thereof will be omitted. However, as shown in FIG. 17, the level of the Y signal is defined such that the black level is defined as (16) and the white level is defined as (239). Although the line number [564] is a free area in the standard, a control address signal is inserted into this line in an example in which a MUSE signal is recorded on an optical disk. The control address signal is a code signal that the player can use for controlling special functions and displaying time information.

The above-mentioned MUSE signal is FM-modulated and recorded on an optical disk. FIG. 18 is a frequency spectrum diagram of a signal recorded on an optical disc. S _M is a FM-modulated MUSE signal. The 8-bit quantization level 16 of the MUSE signal has a frequency f ₁ (= 10.6 MHz), and the 8-bit quantization level 128 has a frequency f ₂ (= 1).
The MUSE signal is FM-modulated so as to be 4.4 MHz. Further, the low frequency side of the FM-modulated signal S _M, the digital signal S _EFM and the pilot signal S _P are frequency-multiplexed.

The digital signal S _EFM has a signal form similar to that of a compact disk, and is an EFM-modulated digital audio or video signal. The pilot signal _SP is a signal of the frequency f _P and is a time base reference signal. This pilot signal _SP is continuously recorded on the optical disk. The frequency f _P is _equal to the horizontal frequency f
_H and the following relationship are selected. f _P = 135/2 × f _H (= 2278125 Hz)

When reproducing the optical disk on which the MUSE signal is recorded, a horizontal synchronization signal is extracted from the reproduced MUSE signal for a TBC (Time Base Corrector), and a clock signal synchronized with the extracted horizontal synchronization signal is extracted. P
It needs to be generated by LL.

[0010]

As shown in FIG. 17, the level of the reproduced horizontal synchronizing signal HD in the reproduced MUSE signal is lower than other signal levels, and it is difficult to extract it. As in the conventional case, it cannot be easily extracted by clamping or slicing the reproduced horizontal synchronizing signal HD. Errors or omissions in the synchronization signal lead to malfunctions in the reproduction system of the MUSE signal (TV monitor, MUSE decoder, etc.), and also in the reproduction device of the same signal (LD player, etc.), malfunction of the spindle motor control, T
This has a large effect on performance such as a malfunction of the BC.

The reproduced horizontal synchronizing signal H in the reproduced MUSE signal
D (FIG. 16) is used for controlling the spindle motor, processing the TBC, etc. after being extracted, and has a great influence on the reproduction system. In the control of the spindle motor, the lack of the reproduction horizontal synchronization signal HD causes
A problem occurs in the rotation control, and the stability of the time axis of the reproduction MUSE signal is lost. Similarly, in the TBC, the phase comparator is operated by using the reproduced horizontal synchronization signal HD, and the comparison output is supplied to the VCO through the loop filter.
Since the write clock WCLK is generated by the CO, the erroneous detection of the reproduction horizontal synchronization signal HD affects the generation of the write clock WCLK, and further results in erroneous various timings for reproduction processing control by the write clock WCLK. Becomes

Accordingly, an object of the present invention is to provide a synchronous signal extracting device capable of extracting a synchronous signal in a reproduced signal without error.

[0013]

According to the present invention, there is provided an apparatus for extracting a synchronization signal included in a reproduction signal from a recording medium, comprising: means for generating a clock signal synchronized with the reproduction signal; Control based on reference points
Control signal generating means for generating a control signal, and a clock signal
And a control signal and a first signal corresponding to the position of the synchronization signal.
A timing generating means for generating a second window corresponding to the law of the window and the synchronization signal; and a first window.
Synchronization signal that extracts the synchronization signal from the playback signal using the dough
A first extracting means using an extracting means and a second window;
The horizontal reference phase point from the synchronization signal extracted by the
A synchronization signal extracting device comprising a reference point extracting means for extracting .

[0014]

According to the present invention, the reproduction horizontal synchronization signal HD is reproduced by using a window synchronized with the reproduction signal corresponding to the position of each line and the rising and falling, which is the rule of the reproduction horizontal synchronization signal HD of the reproduction MUSE signal. This is a device that converts the signal into a falling (or rising signal) signal delayed by a certain amount and extracts the signal. As a result, the reproduced horizontal synchronizing signal HD, which has a small signal level and is difficult to extract with the conventional technique, can be accurately extracted.

[0015]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the entire configuration of this embodiment, and 1 is an optical disk. This optical disc 1 includes
As described above, MUSE signal S _M, which is FM-modulated, the digital signal S _EFM and signal pilot signal S _P is frequency-multiplexed has been recorded. The optical disc 1 is rotationally driven by a spindle motor 2 in a CAV (constant angular velocity) or CLV (constant linear velocity) system. 3
Is a spindle control circuit for controlling the rotation speed and rotation phase of the spindle motor 2.

The recording signal on the optical disk 1 is read by an optical pickup 4. Although not shown, a feed mechanism for moving the pickup 4 in the radial direction of the disk 1 is provided. Conventionally known rotary driving of the optical disc 1, the structure of the pickup 4, the feeding mechanism of the pickup 4, and the like can be adopted.

A reproduction signal read by the pickup 4 is supplied to bandpass filters 6 and 7 via a reproduction amplifier 5. By the band pass filter 6,
FM-modulated MUSE signal S _M is separated by a band-pass filter 7, the pilot signal S _P is separated. The signal S _M is FM-demodulated by the FM demodulation circuit 8, and the reproduced MUSE signal generated at the output thereof is sent to the A / D converter 9, the synchronization separation circuit 10, the horizontal synchronization signal extraction circuit 17, and the TBC signal generator 12, respectively. Supplied. Pilot signal S _P output from the band-pass filter 7 is also supplied to the TBC signal generator 12. Also, for these circuits, VC
The write clock WCLK is supplied from O15.

The A / D converter 9 has a write clock WCL
Using K, the reproduced MUSE signal is sampled at a frequency of 16.2 MHz or an integral multiple thereof, and a digital MUSE signal having one sample of 8 bits is output. The synchronization separation circuit 10 detects a frame pulse inserted in the line numbers [1] and [2] in the MUSE signal,
As described later, the load signal LD as a timing reference
Generate S. The load signal LDS and the write clock WCLK are supplied to the timing generator 11, and the timing generator 11 generates various timing signals necessary for the reproduction process. The details of the timing generator 11 will be described later.

The TBC signal generator 12 generates a signal synchronized with the reproduced MUSE signal for the TBC, and supplies this signal to the phase comparator 13. As a signal synchronized with the reproduction MUSE signal, a reproduction pilot signal or a reproduction horizontal synchronization signal HD can be used. A phase comparator 13 generates a comparison output corresponding to a phase difference between a reproduction pilot signal or a reproduction horizontal synchronizing signal, a signal obtained by dividing the frequency of the write clock WCLK, or a signal generated by the timing generator 11 in synchronization with the MUSE signal. The comparison output is applied to a VCO (Voltage Controlled) through a loop filter 14.
Oscillator) 15 is supplied as a control voltage.
The VCO 15 changes the oscillation frequency according to the control voltage,
A write clock WCLK is generated at the output. Depending on the configuration of the phase comparator 13, a window generated by the timing generator 11 from the write clock WCLK may be used instead of the write clock WCLK.

A PLL is constituted by the phase comparator 13, the loop filter 14, and the VCO 15, and the PLL is synchronized with the signal from the TBC signal generator 12, that is, reproduced M.
A write clock WCLK synchronized with the USE signal is generated. The write clock WCLK is supplied to the memory 16 for TBC, and a digital signal from the A / D converter 9 is supplied to the memory 16 by the write clock WCLK.
Is written to. The memory 16 includes a RAM, a FIFO, and the like.

The reproduction MUSE signal supplied to the horizontal synchronizing signal extracting circuit 17 is extracted with the horizontal synchronizing signal by the timing generated by the timing generator 11. The extracted horizontal synchronizing signal is supplied to a TBC hold circuit 18 to detect whether a horizontal synchronizing signal is missing due to dropout or the like using the window generated by the timing generator 11 by the TBC hold circuit 18. Is done. If a horizontal sync signal dropout is detected, a TBC hold signal is supplied to the TBC phase comparator 13, and the control voltage from the loop filter 14 to the VCO 15 is held at a value immediately before entering the hold section.

On the other hand, by the read clock RCLK,
Data is read from the memory 16. This read clock RCLK is formed by dividing the master clock generated by the crystal oscillator, and is a stable clock. Therefore, the time axis fluctuation included in the reproduced MUSE signal is removed by the TBC including the memory 16, and the data read from the memory 16 does not include the time axis fluctuation. Although not shown, the signal read from the memory 16 is returned to an analog MUSE signal by the D / A converter, and further supplied to a MUSE decoder.
A reproduced color video signal is obtained by the MUSE decoder.

Next, an example of the configuration of the timing generator 11 will be described. This timing generator 11
Is a two-stage counter operated by the write clock WCLK. This write clock WCLK
Is supplied from the VCO 15 as described above. FIG. 2 shows the configuration of the timing generator 11. Reference numeral 31 denotes a first counter, which is here called a sample counter. Reference numeral 32 denotes a load signal input terminal of the sample counter 31. 33 is a clock signal input terminal of the sample counter 31. Reference numeral 34 denotes a carry signal output terminal of the sample counter 31. Reference numeral 35 denotes a second counter, which is here called a line counter. 36
Is a load signal input terminal of the line counter 35. 3
Reference numeral 7 denotes a clock signal input terminal of the line counter 35. Further, reference numeral 40 denotes an output terminal of the sample counter 31, and reference numeral 41 denotes an output terminal of the line counter 35.

An external load signal LDS is supplied to the load signal input terminal 32 of the sample counter 31 and the load signal LDS input terminal 36 of the line counter 35, respectively. The carry signal output terminal 34 of the sample counter 31 is connected to the signal input terminal ET of the line counter 35.

When the load signal LDS is input to the load signal input terminal 32 and the load signal input terminal 36, the sample counter 31 and the line counter 35 load the load data into the counter 31 and the counter 35, respectively. Further, the sample counter 31 is incremented by the write clock WCLK supplied to the clock input terminal 33. When the count value reaches the maximum value preset in the sample counter 31,
Carry signal CA is output from carry signal output terminal 34, and the count value returns to [1]. This carry signal CA
Is supplied to the signal input terminal ET of the line counter 35. Thereby, the line counter 35 is incremented. When the count value reaches the maximum value preset in the sample counter 35, the count value returns to [1].

The load signal LDS input to the load signal input terminal 32 and the load signal input terminal 36 described above is shown in FIG.
Is generated from the frame pulse in the MUSE signal separated by the sync separation circuit 10 of FIG. That is, as shown in FIG. 3, the sync separation circuit 10 extracts the frame pulse of the line number [1] and the line number [2] from the signal supplied from the A / D converter 9. However, FIG. 3 shows only the waveform of the line number [2]. Then, a frame reference phase point included in the frame pulse of the line number [2] is detected, and a load signal LDS having this point as a pulse falling is generated.

Here, an example of the operation of the timing generator 11 will be described with reference to the timing chart of FIG. FIG. 4A shows the write clock WCLK supplied to the clock signal input terminal 33 of the sample counter 31. FIG. 4B shows the load signal LDS described above,
It is supplied from the synchronization separation circuit 10. Sample counter 3
1 and the line counter 35, when supplied with the load signal LDS of FIG. 4B from the synchronization separation circuit 10, sets the preset load data 38 and load data 39, respectively.
Will be loaded. In this example, corresponding to the fact that the load signal LDS is generated at the frame reference phase point in the reproduced MUSE signal, the load data 38 has a value representing [473], and the load data 39 has a value representing [2]. Have been.

By loading these load data, the sample counter 31 and the line counter 3 are loaded.
5 outputs the same value as the load data from the respective data output terminals 40 and 41 as shown in FIGS. 4C and 4D. The counting timing after loading the load data is determined by the sample counter 31 as described above.
In the line counter 35, the timing is the timing of the carry signal CA supplied from the sample counter 31.

From the outputs of the sample counter 31 and the line counter 35, for example, a window pulse for timing extraction can be generated. As an example, FIG.
As shown in E, a window can be generated at the position of the sample number [473 to 475] of the line number [2] in the reproduction MUSE signal. The timing of the window generated in this manner is such that the load signal LDS is
Synchronization separation circuit 1 from frame pulse included in SE signal
0 and the write clock WCL
Since K is formed so as to synchronize with the reproduced MUSE signal, it is synchronized with the reproduced MUSE video signal.

Next, the operation of the TBC hold circuit 18 will be described with reference to the drawings. FIG. 5 shows an example of the configuration of the TBC hold circuit 18, and FIG. 6 shows a timing chart of the operation. Reference numeral 51 denotes a D flip-flop, which is supplied as a data input from the horizontal synchronizing signal extracting circuit 17 in FIG. 1 and a window EDW from the timing generator 11 as its clock input. With this window EDW
Is also supplied as a clock input of the D flip-flop 52. The inverted output HL of the D flip-flop 51
D1 is supplied as a data input of a D flip-flop 52 and is also supplied to one input of an AND circuit 53. The non-inverted output of the D flip-flop 52 is AND
It is supplied to the other input of the circuit 53. The output of the AND circuit 53 is the output of the TBC hold circuit 18 as shown in FIG.
Is supplied to the TBC phase comparator 13.

This circuit monitors the input reproduced horizontal synchronizing signal HD based on the window generated by the timing generator 11. When the reproduction horizontal synchronizing signal HD is lost, a pulse of 1H to 2H is generated.
The error output of the phase comparator 13 is stopped. As a result, V
CO15 input voltage is held and the write clock WCLK
Abnormal fluttering can be prevented. Thus, the write clock WCL due to the loss of the reproduction horizontal synchronization signal HD
Synchronous loss from the reproduced MUSE signal of K and the output of the timing generator 11 is prevented, and a stable reproduced output is possible.

As shown in FIG. 16, the reproduced horizontal synchronizing signal HD of the reproduced MUSE signal has a rule. That is, the rise and fall are repeated at the horizontal reference phase point (sixth sample). However, the first to fourth lines
The part of the line is irregular. Therefore, the timing generator 11 synchronizes with the playback MUSE signal and generates a window which has the above-described rule of the playback horizontal synchronization signal HD and a playback MU corresponding to the position of the playback horizontal synchronization signal HD.
By using a window synchronized with the SE signal and extracting the one within the window, the reproduced horizontal synchronization signal HD is accurately extracted.

FIG. 7 shows a configuration of a horizontal synchronizing signal extracting circuit 17 to which the present invention is applied. The horizontal synchronizing signal extracting circuit 17 includes a sampling circuit 61, a waveform shaping circuit 62, and a conversion circuit 63. The sampling circuit 61 includes a reproduction MUSE signal and a window HD.
ETWIN is supplied. This window HDETWI
N is supplied from the timing generator 11. The output of the sampling circuit 61 is supplied to the conversion circuit 63 via the waveform shaping circuit 62. Also, the timing generator 1
1 to the conversion circuit 63, HDPHASE, HDRST
And AHDWIN.

The sampling circuit 61 is controlled by a window HDETWIN, as shown in FIG. It comprises a switch 81, an amplifier 82 and a smoothing circuit 83.
The reproduced MUSE signal supplied to the sampling circuit 61 is supplied to the amplifier 82 and the smoothing circuit 83 via the terminals ac of the switch 81. The output of the smoothing circuit 83 is supplied to the terminal b of the switch 81 and to the waveform shaping circuit 62. The output signal of the amplifier 82 is also supplied to the waveform shaping circuit 62.

The sampling circuit 61 converts a signal of more than tens of samples (a period slightly wider than the period of the reproduction horizontal synchronization signal HD) including the rising and falling sections of the reproduction horizontal synchronization signal HD from the reproduction MUSE signal into the reproduction MUSE signal. Window HDETW from synchronized timing generator 11
This is a circuit extracted by IN. Reproduction horizontal synchronization signal HD
The switch 81 operates so as to select a period of more than tens of samples including the center (6 samples) by the window HDETWIN, and to output the output voltage of the smoothing circuit 83 during the other periods.

FIG. 9A shows a reproduction MUSE signal. FIG.
B is a window HDETWIN, and FIG. 9C is an output of the smoothing circuit 83. FIG. 9D shows the reproduction horizontal synchronization signal HD.
9E shows the actual output of the switch 81. Sampling circuit 6 shown in FIG.
The signal extracted by 1 is the signal shown in FIG. 9D. The signal including the reproduced horizontal synchronizing signal HD extracted by the sampling circuit 61 is not accurate yet,
As shown in FIG. 9E, in the case of the actual output waveform, a plurality of risings and fallings occur, and it is not known where the reference is for the reproduced horizontal synchronization signal HD.

Therefore, the windows HDPHASE and AHDWIN generated by the timing generator 11 are used. FIG. 10 shows a waveform of a signal supplied from the timing generator 11 to the horizontal synchronizing signal extracting circuit 17. As can be seen from FIG. 10, the window HDP
HASE is a window synchronized with the reproduction MUSE signal and having the above-described rule. That is, each line has a level of “H” when the horizontal reference phase rises and “L” when the horizontal reference phase falls. The window HDPHASE is changed in the middle of each line by the window HDRST so as to be within the range of the window AHDWIN shown in FIG. That is, the window HDRST is
Sample N that changes HDPHASE for each line
o. A window is created as shown in FIG. The window AHDWIN is synchronized with the playback MUSE signal,
A window corresponding to the position of the reproduction horizontal synchronization signal HD. As shown in FIG. 12, AHD1, AHD2, DL
This is a window in which the change points of AHD1 and DLAHD2 are located at the center. Furthermore, this window AH
Only the change within the width of DWIN is converted to the fall of the output pulse signal XAHDEDG of the conversion circuit 63.

FIG. 11 shows an example of the waveform shaping circuit 62. The waveform shaping circuit 62 includes a comparator 91, a resistor 92
And an inverter 9 in the integrating circuit composed of
6, a delay circuit to which a resistor 93 and a capacitor 9 are added.
5 and a delay circuit in which an inverter 97 is added to the integrating circuit. Amplifier 82 of sampling circuit 61
The output of the smoothing circuit 83 is supplied to the comparator 91. The comparator 91 has AH at one end of its output terminal.
D1 and outputs DLAHD1 through a delay circuit.
Is output. In addition, the comparator 91 outputs AHD2 to the other output terminal, and outputs DHD via a delay circuit.
Outputs LAHD2.

FIG. 12A shows the rising edge of the reproduction horizontal synchronizing signal HD. FIG. 12B shows the falling edge of the reproduction horizontal synchronization signal HD. When the rising edge of the reproduction horizontal synchronizing signal HD is extracted by the sampling circuit 61, FIG.
AHD1, DLAHD1, AHD2, and DLAHD2 as shown in FIG. Also,
When the falling edge of the reproduction horizontal synchronizing signal HD is sampled by the sampling circuit 61, A as shown in FIG.
HD1, DLAHD1, AHD2 and DLAHD2 are generated from the waveform shaping circuit 62.

The conversion circuit 63, as shown in FIG.
ND circuits 112 and 113, NOR circuits 114 and 115,
It comprises inverters 111 and 116. AND circuit 1
12 is supplied with DLAHD1, AHD1, HDPHASE and AHDWIN. DLA to AND circuit 113
HD2, AHD2, HDPHASE to inverter 111
AHDWIN and AHDWIN are supplied. NO
The output of the AND circuits 112 and 113 and the output of the NOR circuit 115 are supplied to the R circuit 114. The NOR circuit 115 has the output of the NOR circuit 114 and the HDRST
Is supplied. The output of the NOR circuit 115 is supplied to the NOR circuit 114 and the inverter 116. Inverter 116 generates output pulse signal XAHDEDG. NOR circuits 114 and 115 form an RS flip-flop. That is, AND circuits 112 and 113
Are set inputs and HDRST is a reset input.

For convenience of explanation, the AND circuit 1
13 and a second path through AND circuit 112
Let's consider the path. Waveform shaping circuit 6 in FIG.
2, a signal obtained by delaying the reproduction horizontal synchronizing signal HD is generated, and only when these signals satisfy the following conditions, a falling signal is obtained by the conversion circuit 63 shown in FIG. FIG. 14 is a time chart showing the operation of the conversion circuit 63.

Here, at the point indicated by ta in FIG.
An output is generated by the AND circuit 113, whereby the falling of the reproduction horizontal synchronizing signal HD is determined by the output pulse signal XAHD.
Convert to the falling edge of EDG. At time tb,
The rising edge of the reproduction horizontal synchronization signal HD (rising edge of AHD2) is converted to the falling edge of the output pulse signal XAHDEDG.

Referring to FIGS. 12, 13 and 14, the conditions under which the falling edge of the reproduced horizontal synchronizing signal HD can be converted into the falling edge of the output pulse signal XAHDEDG by the first pass will be described below. HDPHASE "L" AHDWIN "H" AHD2 and DLAHD2 both become "H" edge

Referring to FIGS. 12, 13 and 14, the conditions under which the rising edge of the reproduced horizontal synchronizing signal HD can be converted into the falling edge of the output pulse signal XAHDEDG by the second pass will be described below. HDPHASE “H” AHDWIN “H” AHD1 and DLAHD1 are both “H” edges

After converting the falling edge of the reproduced horizontal synchronizing signal HD and the rising edge of the reproduced horizontal synchronizing signal HD into a falling edge, HDRST is performed at the center of each line by HDRST.
The output pulse signal XAHDEDG is set to “H”
Return to The timing of this signal is shown in FIG. 10, and the input position on the circuit is shown in FIG.

Thus, the reproduced horizontal synchronizing signal HD can be accurately converted to the falling edge of the output pulse signal XAHDEDG, and each block of the reproduced MUSE signal reproducing system can be operated with high accuracy. The conversion circuit 63
Is not limited to the conversion to the falling edge, but can also be converted to the rising edge of the output pulse signal AHDEDG as shown by the broken line in FIG. Further, the present invention is not limited to the above-described embodiment, and can be applied to extraction of a synchronization signal such as an NTSC or PAL signal.

[0047]

According to the present invention, it is possible to obtain an output pulse signal that accurately represents phase information of a synchronization signal in a reproduction signal. That is, a window is generated based on the clock synchronized with the reproduction signal, and the horizontal reference phase point can be extracted from the window. As a result, the reproduction system (TV monitor, MUSE decoder, etc.) of the MUSE signal can operate stably and with high precision without causing an error or loss of the synchronization signal.
D player, etc.) can also improve performance such as spindle motor control operation and TBC operation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a timing generator according to an embodiment of the present invention;

FIG. 3 is a timing chart for explaining generation of a load signal in a timing generator.

FIG. 4 is a timing chart for explaining a timing generator.

FIG. 5 is a block diagram illustrating an example of a TBC hold circuit according to an embodiment of the present invention;

FIG. 6 is a timing chart for explaining a TBC hold circuit.

FIG. 7 is a block diagram illustrating an example of a horizontal synchronizing signal extracting circuit according to an embodiment of the present invention;

FIG. 8 is a circuit diagram of an example of a sampling circuit in the horizontal synchronizing signal sampling circuit.

FIG. 9 is a waveform diagram for explaining a sampling circuit in the horizontal synchronizing signal extracting circuit.

FIG. 10 is a waveform diagram for explaining a window in the horizontal synchronizing signal extracting circuit.

FIG. 11 is a circuit diagram of an example of a waveform shaping circuit in a horizontal synchronizing signal extracting circuit.

FIG. 12 is a waveform chart for explaining the waveform shaping circuit.

FIG. 13 is a circuit diagram of an example of a conversion circuit in the horizontal synchronizing signal sampling circuit.

FIG. 14 is a time chart for explaining the operation of one embodiment of the present invention.

FIG. 15 is a schematic diagram illustrating a signal format of a MUSE signal.

FIG. 16 is a waveform diagram for explaining a horizontal synchronization signal in a MUSE signal.

FIG. 17 is a schematic diagram for explaining a level of a horizontal synchronization signal.

FIG. 18 is a frequency spectrum diagram for explaining a recording signal of an optical disk to which the present invention can be applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Optical disk 4 Pickup 8 FM demodulator 11 Timing generator 13 Phase comparator 15 VCO 17 Horizontal synchronizing signal extraction circuit 18 TBC hold circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/76-5/956 H04N 5/08-5/12

Claims (2)

(57) [Claims] 1. An apparatus for extracting a synchronization signal included in a reproduction signal from a recording medium, comprising: means for generating a clock signal synchronized with the reproduction signal; and control based on a frame phase reference point of the reproduction signal. signal
A synchronizing signal from the clock signal and the control signal.
Window corresponding to the position of
Timing generating means for generating a second window corresponding to the rule of the following, synchronizing signal extracting means for extracting the synchronizing signal in the reproduction signal using the first window, and using the second window The first extracting means
The horizontal reference phase point is extracted from the synchronization signal
And a reference point extracting means for extracting the synchronization signal. 2. A MUSE signal on the recording medium is recorded, claims, characterized in that for generating the window from the reproduced horizontal synchronizing signals for the first and second in the MUSE signal reproduced from said recording medium 2. The synchronizing signal extracting device according to 1.