JPH0327144B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] The synchronization separation circuit of the present invention detects a level change of a composite synchronization signal input from an image display device for each horizontal scanning period, and detects a pulse width after the level change. is larger than the pulse width of the horizontal synchronization signal included in the composite synchronization signal, and when it is determined that the pulse width after the change is larger than the pulse width of the horizontal synchronization signal, vertical synchronization means for starting and terminating signal generation, thereby digitally separating the horizontal and vertical synchronizing signals from the composite synchronizing signal;
The synchronous separation circuit and the CRT controller can be integrated into one chip by inputting the signal to the CRT controller.

[Industrial application field]

The present invention relates to a synchronization separation circuit, and in particular, when synchronizing an image display control device (CRT controller) with an image display device such as a television device, a horizontal synchronization signal and a vertical synchronization signal are extracted from a composite synchronization signal taken out from the image display device. The present invention relates to a synchronous separation circuit for digitally separating a signal and inputting it to the CRT controller.

[Conventional technology]

Traditionally, in order to overlay predetermined characters, images, etc. on the screen of an image display device such as a television device,
A character and image adding device consisting of a CRT controller, video RAM, dot output device, etc. is being considered.

FIG. 4 schematically shows the entire system for adding such characters and images, where 1 is a television device, and 2 is a composite SYNC signal extracted from the television device. Separate horizontal and vertical synchronization signals
A synchronous separation circuit for inputting to the CRT controller 3, 5 a video RAM, 6 a dot output circuit,
7 is a clock generator, 8 is a frequency divider, and the dot clock generated by the clock generator 7 is input as is to the dot output circuit 6;
The frequency of the dot clock is divided by the frequency divider 8 (eg, 1/8) and inputted to the CRT controller 3 as a character clock. As a result, the CRT controller 3 uses the video RAM 5.
The read character/image information is converted into dots by the dot output circuit 6 and inputted to the television device 1.
The information is displayed in a predetermined display area on the screen of the television device 1 based on the display timing signal output from the CRT controller.

In this case, in order to superimpose text/image information read out from the video RAM on the screen of the television device, it is necessary to synchronize the CRT controller with the television signal. Horizontal synchronization signal (HSYNC signal) and vertical synchronization signal (VSYNC signal) from composite synchronization signal (composite SYNC signal) in synchronization equipment, etc.
It is necessary to separate the data and input it to the CRT controller. However, television equipment and video equipment generally use composite synchronization signals as they are, so
It is desirable that the CRT controller can also be synchronized using the composite synchronization signal, and for this purpose, the character/image adding device must have a synchronization separation circuit ( SYNC separator) is required.

FIG. 5 shows a conventional example of this type of synchronous separation circuit. As shown in the figure, an integrating circuit 21' and a differentiating circuit 22' are provided in parallel, and each of these circuits receives a composite synchronous signal ( composite SYNC) is input. The integrating circuit 21' and the differentiating circuit 2
2′ is each composed of CR elements,
By appropriately setting the time constant of the CR element,
Vertical synchronizing signal from the output side of the integrating circuit 21'
VSYNC is taken out, and the horizontal synchronization signal HSYNC is taken out from the output side of the differentiating circuit 22'. Note that 23' and 24' are waveform shaping circuits connected to the output sides of the integrating circuit 21' and the differentiating circuit 22', respectively.

However, the analog type synchronous separation circuit as described above includes a CR element, and therefore it is difficult to configure the synchronous separation circuit together with a CRT controller on a single chip. However, there is a problem in that the synchronous separation circuit must be externally attached.

[Problem that the invention seeks to solve]

The present invention was made to solve the above problems, and takes advantage of the characteristics of the composite synchronization signal and the fact that the CRT controller is programmable.
The synchronous separation circuit is configured as a digital type, and the CRT
This enables integration with a controller into one chip.

[Means for solving problems]

In order to solve the above problems, in the present invention, a first input terminal and a second input terminal receiving a composite synchronization signal are provided.
an exclusive OR circuit having an input terminal of the clock; and an exclusive OR circuit that starts clock counting in response to a first level change of the output of the exclusive OR circuit, and starts counting in response to a subsequent second level change. a counter to be terminated; a detection means for detecting that the count value of the counter is larger than a count value corresponding to the pulse width of the horizontal synchronization signal; and an inversion means for inverting the output level in response to the detection output of the detection means. The output of the inverting means is input to the first input terminal of the exclusive OR circuit, the input of the exclusive OR circuit is used as a vertical synchronization signal, and the output of the exclusive OR circuit is input to the first input terminal of the exclusive OR circuit. A synchronization separation circuit characterized in that it uses a horizontal synchronization signal.

[Effect]

According to the above configuration, it is determined in each horizontal scanning period that the pulse width that is sustained after the output of the exclusive OR circuit causes a first level change is larger than the pulse width of the horizontal synchronization signal. The horizontal and vertical synchronization signals can be separated from the composite synchronization signal by starting and terminating the generation of the vertical synchronization signal at a point in time, and thus generating the vertical synchronization signal.

〔Example〕

FIG. 1 shows the configuration of a synchronization separation circuit as an embodiment of the present invention. Reference numeral 21 is an exclusive NOR circuit, and one input side of the exclusive NOR circuit receives a composite synchronization signal (composite SYNC) from the television device 1. 2a) is input, and the other input side receives a vertical synchronizing signal VSYNC (see Figure 2c) generated at the output side of a toggle flip-flop 26, which will be described later. A horizontal synchronizing signal HSYNC (see FIG. 2b) is output from the output side of the circuit 21. 22 is a counter, each time the horizontal synchronizing signal HSYNC rises from a low level to a high level (that is, each time the composite synchronizing signal changes in level from time t ₁ to t ₅ , etc., which will be described later) in each horizontal scanning period. It enters the count enable state and starts counting the character clock generated in the CRT controller.

24 is a comparison circuit which compares the count value of the counter 22 with a predetermined digital value 23 programmed in the CRT controller (in this embodiment, the digital value is 2 of the HSYNC pulse width).
(compared with the value corresponding to double length) and the counter 22
If the count value exceeds the digital value (that is, if the level after the level change of the composite synchronization signal exceeds twice the HSYNC pulse width in each horizontal scanning period), the 2
A pulse P shown in Figure e is output. Reference numeral 25 denotes an edge detection circuit which detects the rising edge of the pulse P from the comparator circuit 24, and detects the rising edge of the pulse P from the output side of the toggle flip-flop 26 every time the detection signal is input to the toggle flip-flop 26. produces an alternately inverted output signal as shown in FIG. 2d, which is input to the CRT controller as the vertical synchronization signal VSYNC (see FIG. 2c).

The vertical synchronization signal VSYNC generated as described above is also supplied to the other input side of the exclusive NOR circuit 21 to which the composite synchronization signal (composite SYNC) is input from one input side. The exclusive NOR circuit 21 has a high level when the two input signal levels match, and a low level when they do not match, so that the exclusive NOR circuit 21
As shown in FIG. 2b, a horizontal synchronizing signal HSYNC having the same polarity as the vertical synchronizing signal VSYNC is generated from the output side of the horizontal synchronizing signal VSYNC, and is input to the CRT controller together with the vertical synchronizing signal VSYNC.

Hereinafter, a state in which a digital value corresponding to twice the HSYNC pulse width described above is programmed into the CRT controller will be explained using FIG. 3.

FIG. 3 schematically shows the circuit configuration related to the horizontal scanning system inside the CRT controller 3. Reference numeral 31 denotes a horizontal counter, which receives the character clock input from the clock generator 7 for each horizontal scanning period. count. 32 is a display width register in which the horizontal display area width on the display screen of the television device 1 is set by a predetermined number of characters (digital value). 33 is
In the HSYNC position register, the position on the display screen corresponding to the time when HSYNC occurs is also set by the character clock number. Furthermore, 34 is a period register in which the number of character clocks corresponding to one horizontal scanning period is set, and the digital values set in each of these registers 32, 33, and 34 are compared with the count value of the horizontal counter 31, respectively. A comparison is made in circuits 35, 36 and 37. A display timing signal indicating the display period on the display screen is output from the output side of the comparison circuit 35.

Next, the count value of the horizontal counter 31 is
When it matches the setting value set in the HSYNC position register 33, the flip-flop 38 is set by the output of the comparison circuit 36, and starts generating HSYNC pulses from its output side.
Counting operation of the counter 39 for counting the pulse width of the HSYNC using the character clock is started. 40 is a register in which the pulse width of the HSYNC is set by the character clock number (digital value);
When the count value of the counter 39 matches the set value of the register 40, the flip-flop 38 is reset by the output of the comparison circuit 41, and the pulse width of the HSYNC pulse is set to the set value. Furthermore, when the count value of the horizontal counter 31 matches the set value set in the period register 34, the horizontal counter 31 is reset by the output of the comparison circuit 37, and the same process is performed corresponding to the next horizontal scanning period. The operation is repeated.

As described above, inside the CRT controller, the number of character clocks corresponding to the HSYNC pulse width is set as a digital value of a predetermined bit, and the digital value is transferred to the shift register 42.
By shifting one bit to the upper bit side, the digital value is doubled (i.e.,
A digital value corresponding to HSYNC pulse width x 2) can be set, and this constant value is input to the comparator circuit 24 shown in FIG. 1 above.

Since the synchronous separation circuit 2 according to the present invention is configured as described above, the exclusive NOR circuit 2
For example, the composite SYNC signal input to the exclusive NOR circuit ₂₁ becomes a low level at time t1 (corresponding to the generation of the horizontal synchronization signal included in the composite SYNC signal), and the output side of the exclusive NOR circuit 21 becomes a high level. In this case, the counter 22 starts counting, but when the count reaches a value corresponding to the pulse width of the horizontal synchronization signal, the composite SYNC signal becomes high level (the exclusive NOR circuit 21 Since the output of the comparator circuit 24 becomes low level) and the counting operation is completed, no output is produced from the comparator circuit 24.

On the other hand, when the composite SYNC signal becomes low level at time _t2 (corresponding to the generation of the vertical synchronization signal included in the composite SYNC signal) and the output side of the exclusive NOR circuit 21 becomes high level, In the same manner, the counter 22 starts counting, and the count number is determined by the comparison circuit 2.
4, the comparison circuit 2
4 to produce the pulse output P shown in FIG. 2e,
Thereafter, the high level vertical synchronizing signal VSYNC shown in FIG. 2c is generated from the output side of the toggle flip-flop 26 as described above. Therefore, the horizontal synchronization signal on the output side of the exclusive NOR circuit
HSYNC becomes low level, and the counter 22 ends its counting operation. Then, at time t ₃ and t ₄
When the composite SYNC signal becomes high level (corresponding to the generation of the horizontal synchronization signal within the period of the vertical synchronization signal) (in this case, the VSYNC signal input to the exclusive NOR circuit 21 becomes high level). As a result, the HSYNC signal on the output side also becomes high level), the counter 22 once starts counting operation as in the case at time _t1 , but no output is produced from the comparison circuit 24. do not have. The operation of the counter 22 in this case is as follows:
The operation is similar to that at time _t1 . and time t ₅
When the composite SYNC signal becomes high level (corresponding to the end of the vertical synchronization signal included in the composite SYNC signal) and the output side of the exclusive NOR circuit 21 also becomes high level,
As in the case at time t ₂ above, the counter 22
When the count value reaches a value corresponding to twice the HSYNC pulse width, a pulse output P is generated from the comparator circuit 24, thereby inverting the output of the toggle flip-flop 26 from high level to low level. , terminate the vertical synchronization signal VSYNC.
The operation of the counter 22 in this case is as follows at the above-mentioned time t ₂
The operation is similar to that in . (However, counter 2
At the end of count operation 2, the vertical synchronization signal
VSYNC becomes low level, and the horizontal synchronization signal HSYNC on the output side of the exclusive NOR circuit also becomes low level. ) The output signal of the exclusive NOR circuit 21 is shown in FIG. 2b, and as described above, this output signal is used as the horizontal synchronization signal HSYNC.

As described above, the counter 22 is connected to the output side of the exclusive NOR circuit (i.e., the horizontal synchronization signal
The character clock starts counting at the rising edge of HSYNC, and ends at the falling edge of the character clock. Although the exclusive NOR circuit 21 is used in the embodiment described above, this may also be an exclusive OR circuit, in which case the horizontal synchronizing signal HSYNC appears inverted. That is, in that case, the counting operation is started at the falling edge of the horizontal synchronizing signal HSYNC, and is ended at the rising edge thereof. That is, the counter circuit 22 used in the present invention starts a counting operation when one level of the output from the exclusive OR circuit changes, and ends (resets) the counting operation when the other level changes.

The vertical synchronization signal VSYNC generated by the synchronization separation circuit of the present invention is different from the vertical synchronization signal included in the composite SYNC signal in FIG. 2a, as shown in FIG. It has a phase shift equivalent to twice that of
Furthermore, as shown in Fig. 2b, the pulse width of the horizontal synchronization signal HSYNC is twice the normal pulse width at times t ₂ and t ₅ within the blanking period, but these points are different from the above conventional pulse width. The same problem occurs in analog type synchronous separation circuits (in this case as well, there is a delay equal to the CR constant), and it does not cause any problem in practice.

Furthermore, in the embodiment shown in FIG. 1, a value corresponding to twice the HSYNC pulse width is set as a constant value (digital value) input to the comparator circuit 24, but this is not necessarily limited to twice the HSYNC pulse width. It is clear that as long as it is possible to determine whether or not the pulse width is larger than the HSYNC pulse width, an appropriate value larger than the pulse width may be set as the constant value.

〔Effect of the invention〕

According to the present invention, it is possible to configure the synchronization separation circuit digitally and realize one-chip integration with the CRT controller (in other words, synchronization detection within the CRT controller).

Furthermore, according to the present invention, it is possible to separate the horizontal and vertical synchronization signals from the composite synchronization signal with a relatively simple circuit, and even if the cycle of the composite synchronization signal varies, the pulse width of the horizontal synchronization signal remains vertical. Since the spread at the start and end of the synchronization signal is detected, there is no risk of malfunction.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a synchronous separation circuit as an embodiment of the present invention, FIG. 2 is a timing diagram explaining the operation of the circuit shown in FIG. 1, and FIG. 3 is a synchronous separation circuit shown in FIG. Figure 4 is a block diagram of the main parts of the horizontal scanning circuit inside the CRT controller, which together with the circuit constitutes an image addition device. , is a block diagram illustrating a conventional synchronous separation circuit. (Explanation of symbols), 21: Exclusive NOR circuit, Composite SYNC: Composite synchronization signal, HSYNC: Horizontal synchronization signal, VSYNC: Vertical synchronization signal.

Claims (1)

[Claims] 1. A first input terminal, and a second input terminal receiving a composite synchronization signal.
an exclusive OR circuit having an input terminal; and in response to a first level change of the output of the exclusive OR circuit, starts counting the clocks, and
a counter that completes counting in response to a change in the level of the signal, a detection means that detects that the count value of the counter is larger than a count value corresponding to the pulse width of the horizontal synchronization signal, and a detection means that responds to the detection output of the detection means. and an inverting means for inverting the output level, inputting the output of the inverting means to the first input terminal of the exclusive OR circuit, and making the input of the exclusive OR circuit a vertical synchronization signal, A synchronization separation circuit characterized in that the output of the exclusive OR circuit is a horizontal synchronization signal.