JPH0127326Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a circuit for detecting a vertical synchronization signal from a composite synchronization signal of a high definition television signal.

[Background of the idea]

High-definition television is being proposed, led by NHK. This high-definition television system has 1125 scanning lines and a field frequency of 60Hz. In addition, the composite synchronization signal is, as shown in C in Figures 2 and 3, especially the vertical synchronization signal is a conventional NTSC synchronization signal (see C in Figure 4).
It's different.

To measure a television (TV) signal with an oscilloscope or the like, it is necessary to detect the vertical or horizontal synchronization signal of the TV signal and apply a trigger based on the detected synchronization signal. Conventionally, an integrating circuit was used to detect the vertical synchronization signal from the composite synchronization signal of the NTSC signal. However, in the case of high-definition TV signals, the difference between the "low" level and "high" level periods in the vertical synchronization period is small, so an integrating circuit cannot be used to detect the vertical synchronization signal. Furthermore, it is desirable for measuring instruments such as oscilloscopes to be versatile enough to detect vertical synchronization signals not only from high-definition TV signals but also from NTSC signals.

[Purpose of invention]

Therefore, one of the purposes of this invention is to provide high-definition TV.
The present invention provides a circuit for detecting a vertical synchronization signal from a composite synchronization signal of signals.

Another purpose of this invention is to provide high-definition TV signals and NTSC signals.
The present invention provides a circuit that can detect a vertical synchronization signal from both composite synchronization signals of a TV signal.

[Summary of the idea]

This invention allows one line period of high-definition TV signal to
It is 29.66 microseconds (μs), and utilizes the fact that the horizontal synchronization signal width is 0.46μs and that each line of the vertical synchronization period has a pulse of 9.3μs.
The monostable multivibrator is triggered by the leading edge of the composite sync signal and generates a pulse that is wider than the horizontal sync signal width. A D (delayed) flip-flop receives a composite sync signal at its D input, is clocked by the trailing edge of the output pulse of the monostable multivibrator, and is reset by the trailing edge of the composite sync signal. A shift register having a predetermined number of bits receives the output pulse of the D flip-flop, and generates a pulse whose leading edge and trailing edge are controlled by the output pulse and the output pulse of the shift register, respectively, by the flip-flop. Obtain vertical sync signal. Note that by changing the number of bits in the shift register, the vertical synchronization signal of the NTSC signal can also be detected.

[Example of idea]

Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. A high-definition TV signal is supplied to a conventional sync separation circuit 10 to separate a sync signal component, ie, a composite sync signal C. The falling edge, or leading edge, of this composite synchronization signal C triggers the monostable multivibrator 12. This monostable multivibrator 12 is, for example,
It is a 96L02 type IC, and can be used as a time constant circuit, for example.
It has a 32.4 kilohm resistor 14 and a 200 picofarad capacitor 16. Therefore, each time the monostable multivibrator 12 is triggered, it generates an output pulse M with a width of 2.3 μs from the terminal, and the clock terminal of the D flip-flop 18 generates an output pulse M having a width of 2.3 μs.
Supply to CK. Composite synchronization signal C is also supplied to the D terminal and reset terminal R of D flip-flop 18 via inverter 20. By the way, D
Flip-flop 18 receives a composite sync signal C by the trailing edge of output pulse M of monostable multivibrator 12, and is reset by the trailing edge of composite sync signal C to produce an output pulse D at its terminal.

The conventional horizontal pulse generator 22 is connected to the synchronous separation circuit 1
It receives the composite synchronization signal C from 0 and generates a horizontal pulse (horizontal synchronization signal) H. This horizontal pulse H is applied to the clock terminal of the D flip-flop 24.
It is supplied directly to CK and also to a NAND gate 28 via an inverter 26. The D terminal of the D flip-flop 24 is grounded, the set terminal S receives the output pulse D of the flip-flop 18, and the output pulse from the terminal is connected to the NAND gate 2.
Supply to 8. 6 D flip flops 30
Shift register 30 with A to 30F connected in cascade
is, for example, a 74LS174 type IC, and the number of bits changes to 4 bits or 6 bits by switching the switch 32. Clock terminal of shift register 30
The output pulse D of the D flip-flop and the output pulse R of the NAND gate 28 are applied to the CK and reset terminals R, respectively. D flip flop 3
4 receives the output pulse D of the flip-flop 18 at the set terminal S, and receives the signal from the movable contact of the switch 32 at the clock terminal CK. Further, the D terminal of the D flip-flop 34 is grounded and the Q output is supplied to the D terminal of the flip-flop 30A. Thus, the D flip-flop 34 receives the output pulse D of the D flip-flop 18 and the shift signal.
A pulse I whose leading and trailing edges are each controlled by the output pulse of the resistor 30 is generated to trigger the monostable multivibrator 36. The monostable multivibrator 36 generates a vertical synchronizing signal V, and the NAND gate 38 receives the vertical synchronizing signal V and the horizontal pulse H and generates a field judgment signal F.

Next, the operation of the circuit shown in FIG. 1 will be specifically explained with reference to the waveform diagrams shown in FIGS. 2 to 4. In FIG. 2, signal C is a composite sync signal of the vertical sync signal of the first field of a high definition TV signal. In addition, the first
In the figure, switch 32 is connected to terminal 32B (high quality
TV mode) is selected. Pulse M is generated on every falling edge of signal C, but as mentioned above, the width of pulse M is wider than the pulse width of the horizontal synchronization signal of signal C. Therefore, until the time T0 of the 1125th line, pulse D maintains the "high" level, so D
Flip-flops 24 and 34 are not set. On the other hand, since the output of the flip-flop 24 is always at a "high" level, the pulse R is the horizontal pulse H.
Occurs every time. This pulse R resets shift register 30 and D flip-flop 34 so that pulse I also remains at a "high" level. No.
The pulse M falls at time T1 on the 1125th line, but rises at time T2 after a predetermined time. At time T2, since signal C was previously at a "low" level, pulse D changes to a "low" level. This change in pulse D changes pulse I to a "low" level and flip-flop 24 is set.
This set operation causes the pulse R to go high, and the shift register 30 and flip
Flop 34 is not reset. Time T
At 3, flip-flop 18 is reset and pulse D changes to a "high" level. This change causes shift register 30 to shift the Q output of flip-flop 34, a "high" level, for the first time. (Waveform S in FIG. 2 shows the shift state of the shift register 30.) Hereafter,
Similarly, at times T4, T5, and T6, shift register 30 performs a shifting operation. During this time, pulse I remains at a "low" level and pulse R
remains at a "high" level. At time T6,
When shift register 30 performs its fourth shift, it clocks flip-flop 34 via switch 32 since it is set to 4 bits. This clocking causes pulse I to change to a "high" level. Note that since the vertical synchronization period ends at time T6 when the fourth line starts, the same operation as before time T0 is performed from time T7. That is, time T6
From then on, pulse D maintains the "high" level, so
From time T7 onwards, a pulse R is generated on every horizontal sync signal to reset shift register 30 and flip-flop 34. Therefore, flip-flop 24, inverter 26, and NAND gate 28 are used to control shift register 30 during periods other than vertical synchronization.
It also serves as a malfunction prevention circuit that resets the flip-flop 34 to prevent malfunction. This circuit is particularly effective in preventing malfunctions when the power is turned on.

As mentioned above, pulse I is between time points T2 and T6;
That is, the level is "low" only during the vertical synchronization period. The rising edge of pulse I at time T6 triggers monostable multivibrator 36 to generate a vertical pulse V of a predetermined pulse width. In the first field, the "low" level periods of pulses V and H coincide, so the NAND gate 38 causes pulse F to be at a "high" level. This pulse F makes it possible to identify whether the first field is the second field.

FIG. 3 is a waveform diagram illustrating the operation during the vertical synchronization period in the second field of the high-definition TV signal. In this waveform diagram, the width of the pulse M can be changed by changing the values of the resistor 14 and capacitor 16.
Although it is set to 7μs, as in Figure 2,
2.3μs may be sufficient. Since the operation in the case of FIG. 3 is similar to that in the case of FIG. 2, its explanation will be omitted.
Note, however, that since vertical pulse V does not coincide with horizontal pulse H, pulse F is always at a "low" level.

FIG. 4 is a waveform diagram illustrating the operation of FIG. 1 when an NTSC signal is used as the TV signal. However, the width of the pulse M is set to 7 μs as in the case of FIG. 3, and the switch 32 selects the terminal 32A. The operation in this case is also shift register 3.
This case is similar to the case shown in FIG. 2, with the only difference being the number of shifts of 0, so the explanation will be omitted.

[Changes to Examples]

Although only one preferred embodiment of the present invention has been described above, those skilled in the art will understand that various modifications can be made without departing from the spirit of the present invention. For example, instead of D flip-flop 34
Using RS flip-flop and or gate,
A pulse D is applied to the set terminal of this flip-flop.
and the output pulse of the OR gate to which pulse R and the pulse from switch 32 are supplied is RS.
It may also be supplied to the reset terminal of a flip-flop. Alternatively, pulse I may be fed into a conventional integrating circuit to obtain a vertical pulse.

[Effect of idea]

As described above, according to the present invention, a vertical synchronization signal can be reliably detected from a composite synchronization signal of a high-definition TV.
In addition, by setting the output pulse width of the monostable multivibrator 12 to an appropriate value, for example 7 μs, by selecting the number of bits in the shift register 30, it is possible to obtain a vertical synchronization signal from both high-definition TV and NTSC/TV signals. can be detected. Also, since a shift register is used, the number of shifts of pulse D,
That is, it is easy to change the count value.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a preferred embodiment of the present invention, and FIGS. 2, 3, and 4 are waveform diagrams illustrating the operation of FIG. 1. 12: Monostable multivibrator, 18: D flip-flop, 30: Shift register, 3
4: Flip Flop.

Claims (1)

[Scope of utility model registration request] a monostable multivibrator that is triggered by the leading edge of a composite sync signal of a high-definition television signal and generates a pulse with a width wider than a horizontal sync signal width of the high-definition television signal; a D flip-flop which is clocked by the trailing edge of the output pulse of the monostable pultivibrator and reset by the trailing edge of the composite sync signal; a shift register; a flip-flop generating pulses whose leading and trailing edges are respectively controlled by the output pulses of the D flip-flop and the output pulses of the shift register, the output pulses of the flip-flop; A vertical synchronization signal detection circuit for high-definition television signals, which is characterized by obtaining a vertical synchronization signal.