JPH07298092A - Vertical synchronizing signal separator circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction due to an undesired pulse or the like in the circuit separating digitally a vertical synchronizing signal for a television receiver or a VTR or the like. CONSTITUTION:The circuit is made up of a counter 1 outputting a 1st detection pulse C1 with a prescribed pulse width at a prescribed phase and a 2nd detection pulse C2 widening a pulse width than that of the 1st detection pulse by a prescribed time based on a composite synchronizing signal S1 comprising a horizontal synchronizing signal, a vertical synchronizing signal and an equivalent pulse, a lst flip-flop 2 using the 1st detection pulse as a clock signal to detect a pulse from the composite synchronizing signal, a 2nd flip-flop 3 using the 2nd detection pulse as a clock signal to detect a pulse from the composite synchronizing signal S1, and an AND gate 4 ANDing an output of the 1st flip-flop 2 and an output of the 2nd flip-flop 3 to provide an output of a vertical synchronizing signal, and the synchronization is detected twice to prevent malfunction of separation of vertical synchronizing signal due to irregular pulses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical synchronizing signal separation circuit, and more particularly, to a circuit for digitally separating a vertical synchronizing signal in a television receiver, a VTR or the like, in which unnecessary pulses, noise components, etc. Preventing malfunction due to

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 3 (A), a vertical synchronizing signal is digitally separated from a composite synchronizing signal (FIG. 1A) composed of a horizontal synchronizing signal 11, a vertical synchronizing signal 12 and an equivalent pulse 13. In this case, the synchronizing signals 11 and 12 or the equivalent pulse 13 fall in synchronization with the falling timing (T11), and about 1 / 4H (1H is one horizontal period) from that point (T
Generate a detection pulse 14 (Fig.
The vertical sync signal 15 was separated by the pulse 14 (Fig. 5C). By the way, in the home VTR, the heads (L head and R head) are switched for each field, but the horizontal sync signal may be disturbed at the time of switching. In FIG. 3B, when (a) is the synchronous state of the L head and (b) is the synchronous state of the R head, switching is performed when the two do not match (T13),
As shown in (c), the irregular horizontal sync signal 17 is generated immediately after the regular horizontal sync signal 16 due to the synchronization mismatch, and this pulse may be erroneously detected as a vertical sync signal.
The conventional method may cause such a malfunction.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in order to prevent the above-mentioned malfunction, and it is so arranged that even if an unnecessary pulse or the like is mixed in the composite synchronizing signal, these effects are not affected. An object is to provide a vertical sync signal separation circuit.

[0004]

According to the present invention, there is provided a first detection pulse having a predetermined phase and a predetermined pulse width based on a composite sync signal composed of a horizontal sync signal, a vertical sync signal and an equivalent pulse, and the first detection pulse. A counter for outputting a second detection pulse having a pulse width wider than the detection pulse for a predetermined time;
A first flip-flop for detecting a pulse from the composite synchronizing signal using the detection pulse as a clock signal, a second flip-flop for detecting a pulse from the composite synchronizing signal using the second detection pulse as a clock signal, The present invention provides a vertical synchronization signal separation circuit including an AND gate that performs a logical product operation of an output from a first flip-flop and an output from a second flip-flop and outputs a vertical synchronization signal.

[0005]

The counter generates the first detection pulse and the second detection pulse at a predetermined timing based on the composite synchronizing signal. Both the first flip-flop and the second flip-flop, which use these detection pulses as clock signals, detect the sync signal twice each from the composite sync signal in time sequence. When detected by both flip-flops, it is a normal vertical synchronizing signal.
Therefore, if the AND gate takes the logical product of the outputs of both flip-flops, the output is made only when both are detected, and a normal vertical synchronizing signal is obtained.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A vertical sync signal separation circuit according to the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of an essential part showing an embodiment of a vertical sync signal separation circuit according to the present invention, in which sync detection is performed twice, and FIG. 2 is a composite diagram for explaining FIG. It is a timing chart of a synchronization signal and a detection pulse. In FIG. 1, S1 is a composite sync signal composed of a horizontal sync signal, a vertical sync signal and an equivalent pulse, and 1 is a first of a predetermined timing based on the composite sync signal S1.
A counter for generating the detection pulse C1 and the second detection pulse C2, and the first detection pulse C1 is used as a clock signal, and the input composite synchronizing signal S1 is latched at a predetermined timing. The first flip-flop 3 and the second detection pulse C2 are used as a clock signal, and the composite synchronizing signal S1 to be input is latched at a predetermined timing. Is an AND gate for performing a logical product operation on the outputs of both the first and second flip-flops, and So is a vertical synchronization signal output.

Next, the operation of the present invention will be described. The counter 1 receives the first detection pulse C1 from the decoding synchronization signal S1,
The second detection pulse C2 is generated. 2A shows the horizontal sync signal Hs in the decoded sync signal S1, FIG. 2B shows the first detection pulse C1, and FIG. 2C shows the second detection pulse C2. As shown in the drawing, each detection pulse is reset at the falling timing T1 of the horizontal synchronizing signal Hs, the first detection pulse C1 rises at T2, and the second detection pulse C2 rises at T3. Although the horizontal synchronization signal Hs is used as a reference in FIG. 7A, each detection pulse also falls at the same timing for the vertical synchronization signal and the equivalent pulse. This rising timing T2 or T3 is used for vertical synchronization detection described later. Therefore, this rising timing T2 or T3 is
Set the pulse width of the horizontal sync signal Hs to t1 (4.7 μm for NTSC method)
s), both should be set within 1 / 2H after t1 (1H is one horizontal period, 63.5 μs in the NTSC system).
This range is the pulse width of each detection pulse. Where t1
The following is to prevent detection operation in normal horizontal synchronization, and it is 1 / 2H (31.7μ
The reason for setting it within s) is to prevent detection of an equivalent pulse (1 / 2H cycle). Further, the time difference (phase difference) t2 between the timings T2 and T3 is set to be not less than the pulse width t1 of the horizontal synchronizing signal. This is to avoid detection of the same horizontal sync signal.

The above-mentioned first detection pulse C1 and second detection pulse C2 are sent to the first flip-flop 2 and the second flip-flop 3. Each detection pulse serves as a clock signal for each flip-flop. The decoding synchronization signal S1 is input to each flip-flop as shown in FIG. With this configuration, one of the first flip-flops 2 is at the rising timing T2 of the first detection pulse C1 and the other of the second flip-flops 3 is at the rising timing T3 of the second detection pulse C2. The level of the decoding synchronization signal at that timing is detected and the detection level is latched. The output of each of these flip-flops is ANDed by the AND gate 4. As a result, when the outputs of both flip-flops are high "1", that is, when both flip-flops detect the synchronization signal, the output So is output from the AND gate 4. For example, in FIG. 2A, when there is an unnecessary pulse hs as described in the VTR of FIG. 3B as an example with respect to the normal horizontal synchronizing signal Hs, the level is detected by the first flip-flop 2. However, the level is not detected in the second flip-flop 3. Therefore, AND gate 4
Is 0, and the output So is not affected by the unnecessary pulse hs.

On the other hand, as shown in FIG. 2D, when the pulse to be detected is the vertical synchronizing signal Vs (Ve is a serration pulse), its pulse width (t4) is wider than horizontal (NTSC
About 30μs). Therefore, the flip-flops are latched by both detection pulses C1 and C2 having the relationship of (b) and (c) of FIG. 2, and as a result, the AND gate 4 outputs a normal vertical synchronizing signal So. In this way, erroneous detection due to irregular pulses is prevented. Although FIG. 1 described above is an embodiment in which the synchronization detection is performed twice, this detection may be performed three times or more. In this case, a pulse generating circuit that generates a detection pulse corresponding to the number of times of detection (for example, a counter), a detection circuit for the number of times that the synchronous detection is performed in synchronization with each of the detection pulses (for example, a flip-flop), and An output circuit (for example, an AND gate) that outputs a vertical synchronization signal when all the detection circuits detect synchronization is provided. Further, each of the detection pulses is generated in synchronization with the start point of each sync signal or equivalent pulse as described with reference to FIG. 1, and the pulse width is equal to or more than the horizontal sync signal width and within 1/2 of the horizontal period. Different within the range of.

[0010]

As described above, according to the present invention, the vertical synchronizing signal is detected twice by two detection pulses,
Only when both are detected, the output is made as a normal signal. Therefore, for example, it is possible to solve the conventional problem that the vertical sync signal separation operation malfunctions due to an unnecessary pulse that may occur at the time of synchronization switching during reproduction of the VTR, and improve the accuracy of the vertical sync separation circuit. be able to.

[Brief description of drawings]

FIG. 1 is a circuit diagram of essential parts showing an embodiment of a vertical synchronizing signal separation circuit according to the present invention.

FIG. 2 is a timing chart for explaining FIG.

FIG. 3 is a timing chart for explaining conventional problems.

[Explanation of symbols]

 S1 Decoding sync signal 1 Counter 2 First flip-flop 3 Second flip-flop 4 AND gate C1 First detection pulse C2 Second detection pulse So Vertical sync signal output

Claims (3)

[Claims] 1. A horizontal synchronizing signal, which is generated in synchronism with a rising edge or a falling edge of a horizontal synchronizing signal, a vertical synchronizing signal, or an equivalent pulse of a composite synchronizing signal composed of a horizontal synchronizing signal, a vertical synchronizing signal, and an equivalent pulse, respectively. Of the detection pulse generating means for generating a plurality of detection pulses each having a required pulse width different from each other at a pulse width equal to or larger than the pulse width of 1 and within 1/2 of the horizontal period, and synchronized with each detection pulse from the detection pulse generating means. Sync signal level detection means provided for each detection pulse for detecting the sync signal level from the decoded sync signal, and vertical sync output as a vertical sync signal when the sync signal level is detected by all of the sync signal level detection means. A vertical synchronizing signal separation circuit comprising a signal output means. 2. A first detection pulse having a predetermined pulse width at a predetermined phase based on a composite synchronization signal composed of a horizontal synchronization signal, a vertical synchronization signal, and an equivalent pulse, and a pulse width for a predetermined time from the first detection pulse. A counter that outputs a widened second detection pulse, a first flip-flop that detects a pulse from the composite synchronization signal by using the first detection pulse as a clock signal, and a second detection pulse by using the second detection pulse as a clock signal. A second for detecting a pulse from the composite synchronizing signal
Vertical flip-flop, and an AND gate that outputs a vertical sync signal by performing a logical product operation of the output from the first flip-flop and the output from the second flip-flop. Signal separation circuit. 3. The first detection pulse and the second detection pulse are started in synchronization with respective start points of a horizontal synchronization signal, a vertical synchronization signal or an equivalent pulse, and the pulse widths of both detection pulses are horizontally synchronized. 3. The pulse width of the signal or more and within 1/2 horizontal cycle, and the time difference between the end points of the first detection pulse and the second detection pulse is equal to or more than the horizontal synchronization signal width. Vertical sync signal separation circuit.