JP3319189B2 - Scan line number counting circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanning line number counting circuit for counting the number of horizontal scanning lines from a synchronization signal of a video signal.

[0002]

2. Description of the Related Art In a video signal, data may be superimposed, for example, in a vertical blanking interval, and a scanning line number counting circuit is used to detect the position of the data. This scanning line number counting circuit counts the number of horizontal scanning lines from a synchronization signal of a video signal.
When the synchronization signal is separated from the video signal, an incorrect synchronization signal is generated due to the noise of the video signal as shown in FIG.
The synchronization signal may be lost due to a change in the amplitude of the video signal.

Therefore, conventionally, a synchronization signal separated from a video signal is input to a PLL loop circuit, and an oscillation circuit in the PLL loop circuit is oscillated at an integral multiple (including 1) of the horizontal synchronization signal and input. Control is performed so that the phase matches the synchronization signal. Then, a "correct synchronization signal" is obtained as shown in FIG. 6, which is in phase with the synchronization signal input as the output of the PLL loop circuit and compensates for the missing synchronization signal and has no incorrect synchronization signal. It was configured to count this correct synchronization signal.

[0004]

However, in a reproduced video signal of a home VTR or the like, discontinuity may occur at the switching point of the rotary head as shown in FIG. Then, when the above-described conventional PLL loop circuit is used, the synchronization signal at the discontinuous portion is not reproduced, and the number of the horizontal scanning line is erroneous.

[0005] When a discontinuity occurs as shown in FIG. 7 at a rotary head switching point before the vertical synchronizing signal, an equivalent pulse having a frequency twice that of the horizontal synchronizing signal appears before and after the vertical synchronizing signal. Therefore, as shown in FIG. 7, the PLL loop circuit outputs a synchronization signal shifted by a half cycle until the end of the equivalent pulse. Since the response time of the PLL loop is 10 to 100 times the oscillation cycle, it can not immediately follow the discontinuous synchronization signal as shown in FIG.
PLL loop correction from the end of the equivalent pulse
Begins. Therefore, when the number of scanning lines from the vertical synchronizing signal is counted using such a synchronizing signal, the horizontal scanning line number will be incorrect.

Accordingly, the present invention provides a correct synchronizing signal even when there is a missing synchronizing signal or an improper synchronizing signal due to noise, and even when the video signal is discontinuous due to switching of the head of a home VTR. An object of the present invention is to provide a scanning line number counting circuit that can accurately count horizontal scanning line numbers.

[0007]

A scanning line number counting circuit according to the present invention for achieving the above object has a horizontal synchronizing signal.
, A vertical synchronization signal, and inserted before and after the vertical synchronization signal, respectively.
And the equivalent pulse of twice the frequency of the horizontal sync signal
The sync signal obtained by sync separation from the video signal
The input counter, which is the cycle time of the horizontal sync signal
Is counted as one round, and reset by the input synchronization signal.
A predetermined count that is set and exceeds the one-round count value
A counter that is set to a constant value each time the value is reached,
Counter is reset and set to a constant value
Sometimes, a mask signal having a predetermined width is generated, and the
Signal input to inhibit the input of the synchronization signal to the counter
After the prohibition circuit and the counter are set to a constant value,
Every time when a predetermined count value exceeding the one-round count value is reached
An interpolation pulse generating circuit for outputting an interpolation pulse to the
Interpolated pulses output from the
Then, the next synchronization signal is input to the counter
Until the signal input prohibition circuit disables the prohibition operation.
And the interpolation together with the synchronization-separated synchronization signal.
A line counter for counting pulses.
Total output section of the pulse when the number of inter-pulses reaches a predetermined number
Is set to be about the same as the equivalent pulse insertion section.
It is characterized by that.

Further, the scanning line number counting circuit of the present invention comprises a horizontal synchronizing signal, a vertical synchronizing signal, and the vertical synchronizing signal.
Twice the frequency of the horizontal sync signal inserted before and after
From the video signal with the equivalent pulse of
Counter to which a synchronization pulse based on the synchronization signal
The cycle time of the horizontal synchronization signal as one cycle.
Reset by the input sync pulse,
Each time the specified count value is exceeded,
A counter set to a constant value and the counter reset
When a fixed width is set and
A mask signal generation circuit for outputting a mask signal;
Input of the synchronization pulse to the counter during the
A pulse input prohibition circuit for prohibiting the force and the counter
After the value is set to a fixed value,
An interpolation pulse that outputs an interpolation pulse every time the fixed count value is reached.
A pulse generating circuit and an output from the interpolation pulse generating circuit.
After the number of interpolation pulses reaches a predetermined number, the next synchronization pulse
Until the input to the counter, the mask signal
A mask inhibiting circuit for inhibiting output;
Line that counts the interpolation pulse as well as the period pulse
A counter, and when the number of interpolation pulses reaches a predetermined number.
The total output section of the pulse is the insertion section of the equivalent pulse.
It is characterized in that it is set to the same level as the interval.

[0009]

When a mask signal is output, the input of a synchronization signal or a synchronization pulse to the counter is inhibited by the mask signal, so that the counter does not malfunction due to an incorrect synchronization signal due to noise. Is missing, the counter counts over a certain value and the interpolation pulse is output, and the interpolation pulse is counted by the line counter together with the synchronization signal or the synchronization pulse, so that the scanning line number is not mistaken. Further, when a discontinuous video signal is input due to head switching or the like, the input of the synchronization signal or the synchronization pulse at the discontinuous point to the counter is prohibited by the mask signal, so that the counter counts beyond a certain value. interpolation pulse is outputted to the over, the <br/> mask signal output interpolation pulses reaches a predetermined number Since the power is inhibited, the next synchronization signal or pulse is input to the counter, the counter returns to normal operation, and the interpolation pulse and the next synchronization signal or synchronization pulse are also counted by the line counter. There is no mistake.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 show a first embodiment of the present invention. FIG. 1 shows a circuit block diagram of the scanning line number counting circuit. In FIG. 1, a synchronization separation circuit 1 separates a synchronization signal from an input video signal, and outputs the separated synchronization signal to an edge detection circuit 2 and a vertical synchronization separation circuit 3. When detecting the falling edge of the synchronization signal, the edge detection circuit 2 generates a synchronization pulse at the detection timing. This synchronization pulse is output to the reset terminal of the counter 5 via the first AND circuit 4.

When a synchronization pulse is input, the counter 5 sets (resets) the count value to an all-zero value and counts up based on a clock. N from all zero values
The count time up to the value is set to be the same as the cycle time of the horizontal synchronization signal, and the time (T + t) exceeding the cycle time (T) of the horizontal synchronization signal after the input of the synchronization pulse, that is, the count value is (N + r) value When the next synchronizing pulse is input before reaching, it is set (reset) again to the all-zero value. After the synchronization pulse is input, the count value becomes (N
If the next synchronization pulse has not been input before the value reaches (+ r), the count value is set to the r value (constant value) instead of the all-zero value. Then, from the r value to the (N + r) value (the predetermined count exceeding the one-cycle count value ) until the next synchronization pulse is input.
(Count value) is repeated. That is,
The circuit makes one round with the cycle time of the horizontal synchronization signal. The r value is appropriately determined in consideration of the periodic fluctuation of the horizontal synchronization signal. The count value of the counter 5 is constantly output to the mask signal generation circuit 6 and the interpolation pulse generation circuit 7. In this embodiment, the counter 5 is configured to be reset by a synchronization pulse. However, the counter 5 may be configured to be set to an arbitrary value by inputting a synchronization pulse to a set terminal.

The mask signal generation circuit 6 outputs a mask signal only during a period where the input count value is from the r value to the N value. The output section of the mask signal is a noise removal section for canceling an incorrect synchronization signal due to noise as described below. However, since the pulse width W of the mask signal is equal to one half of the horizontal synchronization signal, the pulse width W of the mask signal is horizontal. 1/2 of the synchronization signal
It is preferable to set the period between one cycle and one cycle. An inverted signal of the mask signal is supplied to the first AND circuit 4 via the second AND circuit 8. The first AND circuit 4 inhibits the input of the synchronization pulse to the counter 5 during the output section of the mask signal, and the first AND circuit 4 is configured as a pulse input inhibiting circuit.

The interpolation pulse generation circuit 7 outputs an interpolation pulse when the input count value reaches the value (N + r). This interpolation pulse is output to the clock terminal of the interpolation pulse counter 9 and the input terminal of the OR circuit 10, respectively. The interpolation pulse counter 9 counts the number of interpolation pulses, and switches the output level to the L level when the count value reaches three values.
The interpolation pulse counter 9 is reset by the synchronization pulse output from the first AND circuit 4. That is, the interpolation pulse counter 9 normally outputs the H level, but switches the output to the L level when the interpolation pulse is continuously output three times. The second AND circuit 8 inhibits the output of the mask signal during the L-level output section of the interpolation pulse counter 9, and the second AND circuit 8 is configured as a mask inhibition circuit.

On the other hand, a synchronization pulse output from the first AND circuit 4 is supplied to a pulse delay circuit 11 which is a delay circuit, and the pulse delay circuit 11 delays the synchronization pulse by a time t and outputs the same to the OR circuit 10. That is, the synchronization pulse is synchronized with the synchronization timing of the interpolation pulse by delaying the synchronization pulse by the time t. The OR circuit 10 outputs the synchronization pulse and the interpolation pulse as one signal path system output, and the output is supplied to the clock terminal of the line counter 12.

The line counter 12 counts both the synchronization pulse and the interpolation pulse, and outputs the total count value to a data reproducing circuit (not shown). This line counter 1
2 is reset by the vertical synchronization signal of the vertical synchronization separation circuit 3. The OR circuit 1 is provided in the data reproducing circuit.
An output of 0 is also derived, and the horizontal scanning line number is recognized based on the count value of the line counter 12, and the data superimposition position in the scanning line is recognized based on the synchronization pulse and the interpolation pulse of the OR circuit 10.

Next, the operation of the above configuration will be described. When the video signal (waveform (a) in FIG. 2) is input to the synchronization separation circuit 1, a synchronization signal (waveform (b) in FIG. 2) is output to the edge detection circuit 2. The edge detection circuit 2 outputs a synchronization pulse (waveform (b) in FIG. 2 ) based on the synchronization signal to the counter 5 via the first AND circuit 4. The counter 5 is set (reset) to an all-zero value by the synchronization pulse, and the count value of the counter 5 is output to the mask signal generation circuit 6 and the interpolation pulse generation circuit 7. The mask signal generation circuit 6 generates a mask signal (in FIG. 2) in a section where the count value is from the r value to the N value.
(C) waveform, but the output timing of the next synchronizing pulse is the non-output section of the mask signal, so that the next synchronizing pulse is output to the counter 5 via the first AND circuit 4. The input timing of the synchronization pulse is such that the count value is near the N value, and the counter 5
Is set (reset) again to the all-zero value, so that the interpolation pulse generation circuit 7 does not output the interpolation pulse.

Here, when noise is superimposed on the video signal as shown in the waveform (a) of FIG. 2, an incorrect synchronization pulse is output from the edge detection circuit 2 as shown in the waveform (b) of FIG. . However, since this incorrect synchronization pulse is cut by the first AND circuit 4 by the mask signal, it is not input to the counter 5. Therefore, the counter 5 does not malfunction due to an incorrect synchronization pulse.

When the amplitude of the horizontal synchronizing signal of the video signal is small and the synchronizing pulse is lost from the output of the edge detecting circuit 2 as shown in the waveforms (a) and (b) of FIG.
Count value exceeds the N value and reaches the (N + r) value. Then, the counter 5 is set to the r value, the count-up is restarted, and the interpolation pulse generation circuit 7 outputs the interpolation pulse ((f) waveform in FIG. 2). If the next horizontal synchronizing signal is normal, a synchronizing pulse is output from the edge detecting circuit 2, the counter 5 is set (reset) to an all-zero value by this synchronizing pulse, and the counter 5 returns to the normal operation again. The interpolation pulse counter 9 counts up to one value by the output of the interpolation pulse, but is reset by the synchronization pulse, so that the output of the interpolation pulse counter 9 keeps the H level . In addition, since the interpolation pulse is output to the line counter 12 via the OR circuit 10 instead of the missing sync pulse, the line counter 12 also accurately counts the horizontal scanning line number.

Further, when a discontinuous video signal is input before the vertical synchronizing signal as shown in the waveform (a) of FIG. 3, a synchronizing pulse based on the synchronizing signal immediately after the discontinuity is supplied to the counter 5 by the mask signal. Input is prohibited. Then, the counter 5 reaches the value (N + r) and is set to the value r. On the other hand, since the subsequent synchronization signals are not synchronized, the input of the synchronization pulse to the counter 5 is inhibited by the mask signal. Therefore, the counter 5 repeats counting up from the r value to the (N + r) value, and every time the counter value reaches the (N + r) value, the interpolation pulse generation circuit 7 sets the interpolation pulse ((c) in FIG. 3).
Waveform). When three interpolation pulses are successively output, the output of the interpolation pulse counter 9 becomes L level ((b) waveform in FIG. 3) and the output of the second AND circuit 8 (FIG. 3) regardless of the output of the mask signal. ((D) waveform) becomes L level, and the subsequent input of the synchronization pulse to the counter 5 is permitted. Then, the counter 5 is generated by the synchronization pulse.
Is set to the all-zero value, and the counter 5 returns to the normal operation again. Further, the interpolation pulse counter 9 is reset by the synchronization pulse and its output (FIG. 3)
((B) waveform) returns to the H level.

In the above operation, while the first AND circuit 4 does not output the synchronization pulse, the interpolation pulse generation circuit 7 outputs the interpolation pulse, and the first AND circuit 4 outputs the synchronization pulse immediately after the interpolation pulse. Therefore, the OR circuit 10 outputs an accurate pulse number as shown in the waveform (e) of FIG. 3, and the line counter 12 accurately counts the horizontal scanning line number.

When the amplitude of the video signal is reduced, the synchronization separating circuit 1 outputs an erroneous signal. In such a case, an erroneous signal is likely to be output from an equivalent pulse portion. Assuming that the output count value of the interpolation pulse counter 9 is 3, the output section of the interpolation pulse is set to be substantially equal to the length of the equivalent pulse. Therefore, even if the synchronizing signal is disturbed in the section of the equivalent pulse, the synchronizing pulse and the interpolation pulse from the OR circuit 10 are correctly held, and the line counter 12 accurately counts the horizontal scanning line number.

In order to make the TV screen inconspicuous at the time of variable-speed reproduction or pause of the VTR, a noise bar is often present in the vertical blanking interval. , The scanning line number is reliably counted.

The output count value of the interpolation pulse counter 9 is preferably changed as appropriate depending on the quality of the input video signal, and may be set to 1 or 2, or may be set to 4 or more.

In the above-described embodiment, since all parts other than part of the synchronization separation circuit 1 are processed by digital circuits, the LSI
Therefore, there is an effect that it can be easily manufactured and can be manufactured at low cost with few external parts.

FIGS. 4 and 5 show a second embodiment of the present invention. In the first embodiment, the present invention is realized by hardware, whereas in the second embodiment, the present invention is realized by software. This is the case when it is realized. FIG. 4 is a circuit block diagram of the scanning line number counting circuit. In FIG. 4, a video signal is input to the sync separation circuit 1, and the sync separation circuit 1 separates the sync signal from the video signal and outputs the sync signal to the CPU 20 by interruption. The output synchronization signal of the synchronization separation circuit 1 may be configured to be output to the CPU 20 through the parallel I / O circuit 21 as shown by a broken line in FIG.

The CPU 20 controls the parallel I
/ O circuit 21, timer circuit 23, ROM 24 and RA
M25. Each output of the parallel I / O circuit 21 is led to a data reproducing circuit (not shown). RO
A program for executing the flowchart of FIG. 5 is stored in the M24 or the RAM 25.

Next, the operation will be described with reference to the flowchart of FIG. When a synchronization signal pulse is input (step S ₁ ), the process waits for a mask time (step S ₂ ). Step S ₂ corresponds to the mask signal of the mask signal generating circuit 6 in FIG. 1. When the mask time ends, it is checked whether or not a synchronization signal pulse is input within the waiting time of the input signal. If the synchronization signal pulse is not input (step S ₃ ), the pulse (first signal) is passed through the parallel I / O circuit 21. outputs the corresponding) to the interpolation pulse example (step S _4). Steps S ₃ and S ₄ correspond to the interpolation pulse generation circuit 7 in FIG. And outputs a pulse, increments the interpolation number (step S _5), increments the scan line number (step <br/> flop S _6, S _12). This scanning line number is output through the parallel I / O circuit 21. Then, if the complement times exceeds 3 (step S _6), the scanning line number Increment
After was Ntoshi (step S _7), waits for input of a sync pulse without waiting for mask time. This corresponds to the mask inhibition operation of the interpolation pulse counter 9 and the second AND circuit 8 in FIG.

When a synchronizing signal pulse is input within the waiting time of the input signal (step S ₈ ), a pulse (corresponding to the synchronizing pulse of the first embodiment) is output through the parallel I / O circuit 21 after a certain time has elapsed. (Step S ₉ ,
S _10). And outputs the pulse to reset the interpolation count to zero (step S _11). Then, by incrementing the scanning line number (step S _12), the scanning line number is outputted through the parallel I / O circuit 21. Step S
₈ indicates that the synchronization pulse of the first AND circuit 4 in FIG.
Steps S ₉ and S ₁₀ correspond to the operations input to
Is equivalent to outputting a synchronization pulse through the pulse delay circuit 11 and the OR circuit 10. Step 11 corresponds to the operation of resetting the interpolation pulse counter 9 in FIG.

The steps for measuring the time, such as steps S ₂ , S ₃ and S ₉ , can be realized by a software loop circuit, but a timer circuit 23 may be used. In this case, an interrupt may be used to notify that the predetermined time has come.

[0030]

As described above, according to the present invention, the horizontal
A synchronization signal, a vertical synchronization signal, and before and after the vertical synchronization signal.
Equivalent parameters of twice the frequency of the horizontal synchronizing signal
From the video signal with
Counter to which the horizontal synchronization signal is input.
Counts the cycle time as one round, and inputs the synchronization signal
Reset, and exceeds the one-round count value.
A counter that is set to a constant value each time the count value is reached
When the counter is reset and to a constant value
When set, a mask signal of a predetermined width is generated and the mask
Input of the synchronization signal to the counter by the clock signal
Signal input inhibit circuit and the counter is set to a constant value.
A predetermined count value that exceeds the one-round count value
Interpolation pulse generation circuit that outputs an interpolation pulse each time it reaches
And an interpolation pulse output from the interpolation pulse generation circuit.
After the counter reaches a predetermined number, the next synchronization signal is sent to the counter.
Until input, inhibit operation of the signal input inhibit circuit
Together with a circuit for disabling
And a line counter for counting the interpolation pulse.
When the number of the interpolation pulses reaches a predetermined number,
The total output section is set to the same extent as the equivalent pulse insertion section.
As a result, a correct synchronization signal can be obtained even when there is a missing synchronization signal or an incorrect synchronization signal due to noise, and even when the video signal is discontinuous due to switching of the head of a home VTR, etc. Has the effect that the horizontal scanning line number can be counted.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a scanning line number counting circuit (first embodiment).

FIG. 2 is a waveform diagram of each part (first embodiment).

FIG. 3 is a waveform diagram of each part (first embodiment).

FIG. 4 is a circuit block diagram of a scanning line number counting circuit (second embodiment).

FIG. 5 is a flowchart (second embodiment).

FIG. 6 is a waveform diagram when a PLL loop circuit is used (conventional example).

FIG. 7 is a waveform diagram in the case of a reproduced video signal of a home VTR (conventional example).

[Description of Signs] 4: First AND circuit (pulse input prohibition circuit) 5: Counter 6: Mask signal generation circuit 7: Interpolation pulse generation circuit 8: Second AND circuit (mask prohibition circuit) 11: Pulse delay circuit (delay Circuit) 12 ... Line counter

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-252415 (JP, A) JP-A-5-56302 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/04-5/12

Claims (3)

(57) [Claims] A horizontal synchronizing signal, a vertical synchronizing signal, and the vertical synchronizing signal;
Two horizontal sync signals inserted before and after the direct sync signal, respectively.
Synchronization from video signal with double frequency equivalent pulse
A counter to which the synchronization signal obtained by separation is input.
Counting the cycle time of the horizontal sync signal as one round,
Reset by the input synchronization signal
Each time the specified count value that exceeds the
Counter set, and when the counter is reset and set to a constant value
A mask signal of a predetermined width is generated when the
Signal that inhibits input of the synchronization signal to the counter
Signal input prohibition circuit and the counter for one round after the counter is set to a constant value.
Interpolation pulse each time the specified count value is exceeded.
An interpolation pulse generating circuit for outputting the interpolated pulse output from the interpolation pulse generating circuit Tokoro
After reaching a constant, the next synchronization signal is input to the counter
Until the signal input prohibition circuit is disabled,
And the interpolation pulse together with the synchronization signal separated by synchronization.
A line counter that counts the number of interpolation pulses when the number of the interpolation pulses reaches a predetermined number.
The force section is set to the same extent as the equivalent pulse insertion section.
Scanning line number count circuit, characterized by being. 2. A horizontal synchronizing signal, a vertical synchronizing signal, and the vertical synchronizing signal.
Two horizontal sync signals inserted before and after the direct sync signal, respectively.
Synchronization from video signal with double frequency equivalent pulse
A sync pulse based on the sync signal obtained by separation is input.
Counter that cycle the horizontal synchronization signal cycle time
And reset by the input sync pulse.
To a predetermined count value exceeding the one-round count value.
A counter that is set to a constant value each time it reaches, and a counter that is set when the counter is reset and to a constant value
Mask signal that outputs a mask signal of a predetermined width when
A generating circuit and, in the signal section of the mask, the synchronization signal to the counter.
A pulse input prohibition circuit for prohibiting the input of pulses and the counter for one round after the counter is set to a constant value.
Interpolation pulse each time the specified count value is exceeded.
An interpolation pulse generating circuit for outputting the interpolated pulse output from the interpolation pulse generating circuit Tokoro
After reaching a constant, the next synchronization pulse enters the counter.
Until output of the mask signal
And the interpolation pulse together with the synchronization pulse separated by the synchronization.
A line counter for counting , and a total output of the interpolation pulses when the number of the interpolation pulses reaches a predetermined number.
The force section is set to the same extent as the equivalent pulse insertion section.
Scanning line number count circuit, characterized by being. 3. The method according to claim 2, wherein the synchronizing signal or the synchronizing pulse is
Delay times for delaying to the interpolation pulse cycle timing
3. The scanning line number counting circuit according to claim 1, wherein the scanning line number counting circuit has a path .