JP3402954B2 - Noise removal circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for removing noise mixed in a synchronizing signal of a video signal, and more particularly to a noise removing circuit used for a character display device (on-screen display, etc.). is there.

[0002]

2. Description of the Related Art Conventionally, an on-screen display device for displaying characters such as characters and figures on a television monitor is generally used by inserting an arbitrary character signal into a part of a broadcasting signal such as television broadcasting. It has a superimpose function that allows the viewer to be notified of information such as channels being broadcast.

FIG. 3 is a diagram showing the structure of the on-screen display device. This on-screen display device needs to be created by synchronizing the character signal to be inserted with the video synchronizing signal of the inserted signal in the superimposing function. Therefore, in this on-screen display device, the sync separation circuit 110 separates the video signal 101 of the inserted signal into a vertical sync signal 102 and a horizontal sync signal 103, and the character generator 120 generates a character signal based on these sync signals. Create. Thereafter, the on-screen display device causes the signal switching circuit 130 to switch the video signal 101.
The created character signal 104 is switched based on the video switching timing signal 105, and the video signal 106 is output.

Therefore, if noise is mixed in the sync signal or there is jitter, the character generator 120 may cause an obstacle such as a vertically or horizontally shaken character created and inserted. Especially, since the video has high sensitivity to the horizontal synchronizing signal, this trouble is likely to occur. Therefore, a phase control circuit using a voltage controlled oscillator as shown in FIG. 4 is often provided on the line of the horizontal synchronizing signal 103. This phase control circuit includes a phase comparator 2
The character generator 12 includes a loop filter 220, a voltage controlled oscillator 230, and a stable signal that is synchronized with the horizontal synchronizing signal 103 on average.
Supply to 0.

[0005]

However, since the phase control circuit provided in the above-mentioned on-screen display device requires a voltage-controlled oscillator of an analog circuit, it is difficult to incorporate it in a digital IC (integrated circuit). Further, even when incorporated in a digital IC, a filter or the like for stabilizing the operation of the phase control loop is required outside the IC, which causes an increase in the number of pins of the IC.

Therefore, the present invention has been made in view of the above problems, does not require an analog voltage control oscillator and a filter which are difficult to be built in a digital IC, and further does not increase the number of pins of the IC. An object of the present invention is to provide a noise removing circuit that can remove noise mixed in an input signal without being affected by a reference clock of a circuit for removing noise.

[0007]

In order to achieve the above object, the noise removing circuit of the present invention performs an up-counting operation when the input signal is at the first logic level according to the logic level of the input signal. Up-down counting means for performing a down-counting operation when the logic level is 2;
During the up-counting operation of the up-down counting means, first count-value detecting means for detecting that the count value matches a predetermined value and outputting a detection signal; and during the down-counting operation of the up-down counting means. The second count value detecting means for detecting that the count value matches a predetermined value and outputting a detection signal, and the detection signal from the first count value detecting means are set to "H" level, A flip-flop which is reset to "L" level by a detection signal from the second count value detecting means,
AN which takes the logical product of the output signal of the flip-flop, the input signal and the output signal of the noise mask circuit described later.
An "H" level signal is output until the output signals of the D gate circuit and the AND gate circuit fall, an "L" level signal is output at the falling timing of this output signal, and a "L" level signal is output after a predetermined period. Noise mask means for outputting an H "level signal, and the input signal is allowed to pass only when both the output signal of the flip-flop and the output signal of the noise mask means are at the" H "level. .

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a noise removal circuit according to an embodiment of the present invention. The noise removing circuit is provided between the sync separation circuit and the character generator in the on-screen display device shown in FIG. 3, and removes noise contained in the input signal such as the horizontal sync signal separated by the sync separation circuit. Used to remove.

The input terminal IN to which an input signal is input is connected to the up / down terminal U / D of the up / down counter 10 and the input terminals of the count value detection circuits 12 and 14, respectively. The output terminal of the up / down counter 10 has the count value detection circuits 12, 14
The reference clock pulse CP is input to the input terminal φ of the up / down counter 10.

Further, the output terminal of the count value detection circuit 12 is connected to the set terminal S of the RS flip-flop 16, and the output terminal of the count value detection circuit 14 is RS.
It is connected to the reset terminal R of the flip-flop 16.
The output terminal Q of the RS flip-flop 16 is connected to the first input terminal of the AND gate circuit 18, and the input terminal IN is connected to the second input terminal of the AND gate circuit 18.

Further, the noise removing circuit includes the AN
A noise mask circuit 20 is provided for inhibiting the input signal for a predetermined period from the falling timing of the output signal of the D gate circuit 18. AND gate circuit 1
The output terminal of 8 is connected to the output terminal OUT of the noise removing circuit, and NO in the noise mask circuit 20 is connected.
D flip-flop circuit 24 via T gate circuit 22
Is connected to the clock terminal CK. The data input terminal D of the D flip-flop circuit 24 has a power supply voltage Vcc.
Is input, the output terminal Q of the D flip-flop circuit 24 is connected to the clear terminal CL bar of the up counter 26, and the above-mentioned A is supplied via the NOT gate circuit 28.
It is connected to the third input terminal of the ND gate circuit 18.

Further, the reference clock pulse CP is input to the input terminal φ of the up counter 26, and the output terminal of the up counter 26 is connected to the count value detection circuit 30. The output terminal of the count value detection circuit 30 is connected to the reset terminal R of the D flip-flop 24.

Here, the up / down counter 10
Uses the clock pulse input to the input terminal φ as a reference clock, and performs an up-count operation when the input signal is at the “H (High)” level according to the logic level of the input signal input to the input terminal IN. , "L (Low)
When the level is ", the down count operation is performed. When the counter reaches the maximum value in the up count operation, the up / down counter 10 keeps the maximum count value until the down count operation is performed. Overflow processing to stop the counting operation, and when the counter reaches the minimum value (0) in the down counting operation, the minimum value (0) is set until the counting operation is started.
It has a function of underflow processing that stops the count operation while holding the count value of.

The count value detection circuit 12 is a detection circuit that outputs a pulse when the count value coincides with a predetermined value while the up / down counter 10 is counting up. At this time, the predetermined value may be set to an arbitrary value that can reliably detect the rising edge of the input signal. The count value detection circuit 14 is a detection circuit that outputs a pulse when the count value coincides with a predetermined value during the down-counting operation of the up-down counter 10. At this time, the predetermined value may be set to any value smaller than the maximum value and larger than the minimum value.

The RS flip-flop 16 is set by a pulse output from the count value detection circuit 12 and reset by a pulse output from the count value detection circuit 14. AND gate circuit 18
Is a three-terminal input AND gate circuit that logically ANDs the output signal from the RS flip-flop 16, the input signal from the input terminal IN, and the output signal from the NOT gate circuit 28, which is the output of the noise mask circuit 20. is there.

The NOT gate circuit 22 includes the AND gate.
It is a circuit that inverts the logical polarity of the output signal from the gate circuit 18. The D flip-flop 24 includes the NOT
It is set to "H" level at the rising timing of the output signal of the gate circuit 22 (falling timing of the output signal of the AND gate circuit 18) and becomes "L" level at the timing of the output pulse from the count value detecting circuit 30. Will be reset.

The up-counter 26 is an up-counter for up-counting the reference clock signal input to the input terminal φ, and the content of the counter is reset when the output of the D flip-flop 24 is at "L" level. It The NOT gate circuit 28 is a circuit that inverts the logical polarity of the output signal from the D flip-flop 24. The count value detection circuit 30 is a detection circuit that outputs a pulse when the count value of the up counter 26 coincides with a predetermined value, and its output serves as a reset signal of the D flip-flop 24. The predetermined value at this time is a count value corresponding to a predetermined period that does not hinder the detection of the next input signal from the falling timing of the input signal, for example, about one cycle of the input signal (horizontal synchronization signal). The count value may be set to a period corresponding to 90%.

Next, the operation of the noise removal circuit of this embodiment will be described. FIG. 2 is a timing chart for explaining the operation of this noise removal circuit.

First, the timing chart will be described. In FIG. 2, (a) is a signal showing an example of an input signal, and shows a state in which noise is superimposed in order to explain a noise removing operation. (B) shows the content of the count value of the up / down counter 10 corresponding to the input signal of (a). (C) is a signal indicating the output of the count value detection circuit 12, and (d) is a signal indicating the output of the count value detection circuit 14. In FIG. 2, the predetermined value of the count value when the count value detection circuit 12 and the count value detection circuit 14 output pulses is shown as the same value, but this predetermined value is arbitrary within the range satisfying the above-mentioned conditions. You can set it to. (E) is a signal indicating the output of the RS flip-flop 16. When this signal is at "H" level, that is, when the count value of the up-down counter 10 exceeds a predetermined value during the up-counting operation, and after the shift to the down-count operation until the count value exceeds the predetermined value. During that time, the AND gate circuit 18 is in a state of passing the input signal. Even when noise is mixed in the input signal while the output signal of the RS flip-flop 16 is at the “H” level,
The third input terminal of the AND gate circuit 18 is kept at the “L” level for a predetermined period from the falling timing of the output signal of the ND gate circuit 18, for example, a period corresponding to about 90% of one cycle of the horizontal synchronizing signal of the input signal. By performing the noise mask operation of inputting a signal, only the first received signal is passed, and the influence of noise can be minimized. (F) is a signal indicating the output of the AND gate circuit 18.

Further, in FIG. 2, (g) is a signal indicating the output of the NOT gate circuit 22, and (h) is a signal indicating the output of the D flip-flop 24. (I) shows the content of the count value of the up counter 26 which is reset when the output of the D flip-flop is at "L" level and starts counting when the output is at "H" level. (J) is a signal indicating the output of the count value detection circuit 30, and outputs a pulse when the count value of the up counter 26 reaches a predetermined value. (K)
Is a signal indicating the output of the NOT gate circuit 28 which inverts the logical polarity of the output signal from the D flip-flop 24.

Next, the operation will be described with reference to the block diagram of the noise removing circuit shown in FIG. When an input signal as shown in FIG. 2A is input to the input terminal IN of the noise removing circuit shown in FIG. 1, the up / down counter 10 causes the up-counting operation and the down-counting operation corresponding to the input signal. And outputs the count values as shown in FIG. 2B to the count value detection circuits 12 and 14, respectively.

The count value detection circuit 12 outputs a pulse as shown in FIG. 2C to the RS flip-flop when the input signal is at the "H" level and the count value matches the above-mentioned predetermined value. It outputs to 16 set terminals S. On the other hand, the count value detection circuit 14 outputs a pulse as shown in FIG. 2D to the RS flip-flop 16 when the count value matches the above-mentioned predetermined value when the input signal is at the “L” level. Output to the reset terminal R of. The RS flip-flop 16 outputs an "H" level signal as shown in FIG. 2 (e) between the input of the pulse to the set terminal S and the input of the pulse to the reset terminal R. To the first input terminal of the AND gate circuit 18.

The input terminal is directly input to the second input terminal of the AND gate circuit 18, and the AND gate circuit 18 outputs the output signal from the RS flip-flop 16 and the input signal from the input terminal IN. NO to be described later
The logical product of the output signals from the T gate circuit 28 is calculated, and the result is output to the output terminal OUT and is output to the NOT gate circuit 22.

Here, the output signal from the NOT gate circuit 28 becomes the "L" level only for a predetermined period from the time when the output signal of the AND gate circuit 18 falls from the "H" level to the "L" level. During the periods other than the above, the level becomes "H". The output of the AND gate circuit 18 is determined only by the signals input to the first input terminal and the second input terminal when the output signal of the NOT gate circuit 28 input to the third input terminal is at "H" level. . Therefore, the output of the AND gate circuit 18 is determined by the input signal from the input terminal IN and the output signal from the RS flip-flop 16 except for a predetermined period from the time when the input signal falls. The predetermined period may be set to, for example, a period corresponding to about 90% of one cycle of the input signal (horizontal synchronization signal).

Further, the NOT gate circuit 22 outputs an "H" level signal to the clock terminal CK of the D flip-flop 24 when the output signal of the AND gate circuit 18 is "L" level, and the AND gate circuit 22. When the output signal of the circuit 18 is at the "H" level, it outputs the "L" level signal. The D flip-flop 24 receives the rising signal from the “L” level to the “H” level at the clock terminal CK (when the falling signal is output from the AND gate circuit 18) at the rising timing. The signal is set to the "H" level, and an "H" level signal is output from the output terminal Q thereof to the clear terminal CL bar of the up counter 26 and the NOT gate circuit 28, respectively.

The NOT gate circuit 28 inverts the inputted "H" level signal into an "L" level signal,
It outputs to the third input terminal of the AND gate circuit 18.
When the "H" level signal is input to the clear terminal CL bar, the up counter 26 counts up the reference clock signal input to the input terminal φ and outputs the count value to the count value detection circuit 30. .

The count value detection circuit 30 outputs a pulse to the reset terminal R of the D flip-flop 24 when the count value of the up counter 26 matches a predetermined value. The predetermined value at this time is a count value corresponding to a predetermined period that does not hinder the detection of the next input signal from the falling timing of the input signal, for example, about one cycle of the input signal (horizontal synchronization signal). 9
The count value may be set to a period corresponding to 0%.

The D flip-flop 24 is reset when a pulse is input to the reset terminal R, and outputs an "L" level signal from the output terminal Q of the up counter 26.
To the clear terminal CL bar and the NOT gate circuit 28. This up counter 26 has a clear terminal C
When an "L" level signal is input to the L bar, the count value of the counter is reset, and the process waits until the "H" level signal is input again to start up counting.
The NOT gate circuit 28 inverts the inputted “L” level signal into an “H” level signal and outputs the inverted signal to the third input terminal of the AND gate circuit 18. And AN
The D gate circuit 18 receives the output signal from the RS flip-flop 16 input to the first input terminal, the input signal from the input terminal IN input to the second input terminal, and the NOT input to the third input terminal. The logical product of the output signals from the gate circuit 28 is calculated, and the result is output to the output terminal OUT.

Here, as described above, the inverter circuit 2
The output signal from 8 becomes "L" level for a predetermined period from the time when the output signal of the AND gate circuit 18 falls from "H" level to "L" level, and becomes "H" level in other periods. Become. The output of the AND gate circuit 18 is determined only by the signals input to the first input terminal and the second input terminal when the output signal of the NOT gate circuit 28 input to the third input terminal is at "H" level. . On the other hand, the inverter circuit 2 input to the third input terminal
When the output signal of 8 is "L" level, the signal of "L" level is always output regardless of the signals input to the first input terminal and the second input terminal. Therefore, AND
The output of the gate circuit 18 is from the RS flip-flop 16 and the input signal from the input terminal IN for a predetermined period from the time when the output signal of the AND gate circuit 18 falls from the “H” level to the “L” level. Irrespective of the output signal of, the signal is always at "L" level.

From the above, the RS flip-flop 1
Even if noise is mixed in the input signal during the period when the output signal of 6 is at the "H" level, the AND gate circuit 18 outputs the AND signal for a predetermined period from the falling timing of the output signal.
By performing a noise mask operation of inputting an “L” level signal to the third input terminal of the gate circuit 18, only the first received signal is allowed to pass, and the influence of noise can be minimized. it can.

The rising timing of the output signal of the AND gate circuit 18 is the up / down counter 1
Since it is synchronized with the detection timing of 0 and is synchronized with the timing of the reference clock input to the input terminal φ of the up / down counter 10, it has a time variation of one clock when viewed from the input signal. Become. On the other hand, since the fall timing is the same as the fall timing of the input signal, there is no time variation with respect to the input signal.

Therefore, when the output signal from the AND gate circuit 18 shown in (f) is used as the horizontal reference signal of the on-screen display device, for example, the falling timing of this output signal becomes the reference. By adopting such a circuit configuration, it is possible to obtain a noise removal effect and also to avoid the influence of time variation due to the reference clock.

As described above, according to the present embodiment, it is possible to remove the noise of the input signal without being affected by the reference clock of the circuit for removing the noise. It is not necessary to add pins even when it is built into the circuit).

[0034]

As described above, according to the present invention, it is possible to eliminate noise without increasing the number of IC pins without requiring an analog voltage controlled oscillator and a filter which are difficult to be built in a digital IC. It is possible to provide a noise removing circuit capable of removing the noise mixed in the input signal without being affected by the reference clock of the circuit for doing so.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a noise removal circuit according to an embodiment.

FIG. 2 is a timing chart for explaining the operation of the noise removal circuit according to the embodiment.

FIG. 3 is a diagram showing a configuration of a conventional on-screen display device.

FIG. 4 is a diagram showing a configuration of a phase control circuit provided in the on-screen display.

[Explanation of symbols]

10 up-down counter 12, 14 Count value detection circuit 16 RS-flip-flop 18 AND gate circuit 20 noise mask circuit 22, 28 NOT gate circuit 24 D-flip flop 26 up counter 30 count value detection circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 5/14-5/217 H04N 5/04-5/12 H04N 5/44-5/445

Claims (6)

(57) [Claims] 1. Up-down count means for performing an up-count operation when the input signal is at a first logic level and a down-count operation when the input signal is at a second logic level, and the up-down count means. First count value detecting means for detecting that the count value matches a predetermined value during the up-counting operation of the down-counting means and outputting a detection signal, and the count during the down-counting operation of the up-down counting means “H” is detected by the second count value detecting means for detecting that the value matches the predetermined value and outputting the detection signal, and the detection signal from the first count value detecting means.
A flip-flop that is set to a level and reset to an "L" level by a detection signal from the second count value detecting means; an output signal of the flip-flop, the input signal, and an output signal of a noise mask circuit described later. AN that takes the logical product of
Until the output signals of the D gate circuit and this AND gate circuit fall, an "H" level signal is output, an "L" level signal is output at the falling timing of this output signal, and a "L" level signal is output after a predetermined period. Noise mask means for outputting a signal of H "level, wherein the output signal of the flip-flop and the output signal of the noise mask means both pass the input signal only during a period of" H "level. Noise removal circuit. 2. Up-down counting means for performing an up-counting operation when the input signal is at a first logical level and a down-counting operation when the input signal is at a second logical level according to the logical level of the input signal, and the up-down counting means. First count value detecting means for detecting that the count value matches a predetermined value during the up-counting operation of the down-counting means and outputting a detection signal, and the count during the down-counting operation of the up-down counting means “H” is detected by the second count value detecting means for detecting that the value matches the predetermined value and outputting the detection signal, and the detection signal from the first count value detecting means.
A flip-flop which is set to a level and reset to an "L" level by a detection signal from the second count value detecting means, an output signal of the flip-flop, the input signal, and an output signal of a noise masking means described later. AN that takes the logical product of
Until the output signals of the D gate circuit and this AND gate circuit fall, an "H" level signal is output, an "L" level signal is output at the falling timing of this output signal, and a "L" level signal is output after a predetermined period. A noise removal circuit comprising: a noise mask means for outputting an H "level signal. 3. Up-down counting means for performing an up-counting operation when the input signal is at a first logic level and a down-counting operation when the input signal is at a second logic level, and the up-down counting means. First count value detecting means for detecting that the count value matches a predetermined value during the up-counting operation of the down-counting means and outputting a detection signal, and the count during the down-counting operation of the up-down counting means “H” is detected by the second count value detecting means for detecting that the value matches the predetermined value and outputting the detection signal, and the detection signal from the first count value detecting means.
A flip-flop that is set to a level and reset to an "L" level by a detection signal from the second count value detecting means; and an AND gate circuit that performs a logical product of the output signal of the flip-flop and the input signal. A noise removal circuit comprising: 4. Up-down counting means for performing an up-counting operation when the input signal is at a first logical level and a down-counting operation when the input signal is at a second logical level according to the logical level of the input signal, and the up-down counting means. First count value detecting means for detecting that the count value matches a predetermined value during the up-counting operation of the down-counting means and outputting a detection signal, and the count during the down-counting operation of the up-down counting means “H” is detected by the second count value detecting means for detecting that the value matches the predetermined value and outputting the detection signal, and the detection signal from the first count value detecting means.
RS-flip-flop set to level and reset to "L" level by the detection signal from the second count value detecting means, output signal of the RS-flip-flop, the input signal, and noise masking means described later. AND gate circuit that takes the logical product of the output signal of the AND gate circuit, a NOT gate circuit that inverts the output signal of the AND gate circuit, and is set to "H" level at the rising timing of the output signal of the NOT gate circuit, which will be described later. The D-flip-flop that is reset to the "L" level by the output signal of the third count value detecting means, and the up-count operation when the output signal of the D-flip-flop is the "H" level, and the "L" level Up-counting means for resetting the contents of the counter when the level is Wherein A but inverted third count value detecting means for outputting a pulse to D- flip-flop when they match a predetermined value determined in advance, the output signal of the D- flip-flop
And a NOT gate circuit for outputting to an ND gate circuit. 5. Up / down counting means for up / down counting by switching up / down counting directions according to the logic level of the input signal, and detection for detecting arrival of the input signal from the contents of the counter of the up / down counting means. Means and a logical product calculating means for calculating a logical product of the output signal of the detecting means and the input signal, wherein the information of the falling edge of the input signal is the falling edge of the output signal of the logical product calculating means. A noise removal circuit characterized by being stored in. 6. Up-down counting means for performing an up-counting operation when the input signal is at a first logical level and a down-counting operation when the input signal is at a second logical level according to the logical level of the input signal, and the up-down counting means. First count value detecting means for detecting that the count value matches a predetermined value during the up-counting operation of the down-counting means and outputting a detection signal, and the count during the down-counting operation of the up-down counting means “H” is detected by the second count value detecting means for detecting that the value matches the predetermined value and outputting the detection signal, and the detection signal from the first count value detecting means.
A flip-flop which is set to a level and reset to an "L" level by a detection signal from the second count value detecting means, an output signal of the flip-flop, the input signal, and an output signal of a noise masking means described later. AN that takes the logical product of
Until the output signals of the D gate circuit and this AND gate circuit fall, an "H" level signal is output, an "L" level signal is output at the falling timing of this output signal, and a "L" level signal is output after a predetermined period. A display device comprising: a noise masking circuit for outputting an H "level signal;