JPH07307727A - Method and circuit for sampling data signal - Google Patents

Abstract

PURPOSE:To perform a sampling for a data signal having high data speed, using a clock signal whose frequency accuracy is not so high and to make a sampling circuit common to data signals which are different in data speed. CONSTITUTION:When one data bit length of a data signal or a minimum pulse width is defined as a TD, a clock signal for synchronization having a cycle of 1/M (M is an integer >=2 or a value approximate to the integer) of TD is used. Namely, the frequency of a clock signal for synchronization is M times as fast as data speed. When the clock signal for synchronization is synchronized with the data signal and the clock signal for synchronization is counted by a counter and four (in the case of M = 4) counts are performed or the changed point of the data signal is detected, the counter is reset. When two of the clock signal for synchronization is counted, a sampling clock signal is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling method and a circuit for sampling vertical blanking information of a television screen, for example.

[0002]

2. Description of the Related Art Recently, various kinds of information, such as information such as characters, have been put on the vertical blanking period of a television. FIGS. 5A and 5B are diagrams showing the structure of vertical blanking information data (hereinafter referred to as “VBI data”) of two different systems, respectively. As can be seen from FIG. 5, VBI data is a clock. It comprises a run-in (CRI), a framing code or start bit, and a data part. Conventionally, in order to sample this VBI data, the output of the oscillator is adjusted to the data rate of the VBI data to obtain a sampling clock. The arrow indicates the sampling timing. That is, the CRI is "1""0""1""0"
, Which indicates the cycle and phase of the data that follows it. This CRI is input to a phase-locked loop circuit (PLL circuit) to synchronize the phase and frequency of the PLL circuit with the CRI. A sampling clock signal is generated from this PLL circuit and data is sampled by this sampling clock signal.

[0003]

Since the data rate of VBI data of one system is fixed, P
High Q for oscillator of LL circuit (narrow frequency range)
The system can be realized relatively easily by using a resonator such as a crystal resonator or a ceramic resonator. However, a teletext (T
T), closed caption, character multiplex (MT), and the like, and the data rates of VBI data in each method are various. Therefore, even if the sampling circuit can support one system, Since the frequency range of the resonator is narrow, the sampling clock becomes unstable, so that a system dedicated to each system must be configured after all. Further, since the above-mentioned resonator is expensive, there is a problem that the system cost becomes high.

The present invention has been made under such circumstances, and an object thereof is to provide a data sampling method and a circuit therefor capable of sampling data having different data rates by a common system. Especially.

[0005]

The present invention uses a clock signal that is separate from the data signal. However, instead of synchronizing the clock signal with the data signal, the data signal is synchronized with the clock signal to obtain the sampling clock. Generating a signal. If the clock signal for synchronizing the data signal is called a synchronizing clock signal, the period T _C of the synchronizing clock signal is, as shown in FIG. 1, one data bit length, that is, the minimum pulse width ( It is necessary that it is 1 / M (M is an integer) of the minimum width T _D. That is, the data rate f _D of the data signal is represented by 1 / T _D , and the frequency f _C of the synchronizing clock signal is represented by 1 / T _C , but the relationship between f _C and f _D is f _C = Mf _D It is necessary to be However, M does not have to be an integer and may be a value close to an integer.

In generating the sampling clock signal, the data signal is first synchronized with the synchronizing clock signal. FIG. 1 shows a state after the data signal is synchronized with the synchronizing clock signal. Then, the change point of the data signal after synchronization, that is, the rising and / or falling of the pulse is detected. When M is 4, that is, f _C = 4 f _D, and the case of detecting the rising edge of the pulse is explained as an example, in the present invention, the second pulse of the synchronizing clock signal is detected after the rising edge of the data signal is detected. Outputs sampling clock signal. In such a method, the counter is reset when the rising edge of the pulse is detected, and then the counter counts as "0, 1, 2, 3" (in this example, the count value of the first pulse is "0"). Can be executed by outputting the sampling clock signal when the counter value becomes "1" (when the synchronizing clock signal has counted two pulses), and when the count value becomes "1", the output circuit For example, if the sampling clock signal is output from the comparator, it is possible to sample a time point that is approximately half the minimum pulse width of the data signal.

Then, tentatively, in the data signal, "L" (L
ow level) data continues, the count value is repeated as “0, 1, 2, 3, 0, 1, 2, 3, ...”, and each time the count value becomes “1”, the sampling clock signal Is output, the count value is reset to "0" by the rising detection signal when "H" data is sent in the data signal.

The present invention provides such a method and a circuit for executing the method. The sampling method of a data signal according to the present invention is a method of sampling a digital data signal by a sampling clock signal. At M for the data rate of the data signal
(M is an integer or a value close to an integer) times the frequency of the synchronizing clock signal, the data signal is synchronized with the synchronizing clock signal, and the synchronizing clock signal is n
(N is an integer) M or an integer close to nM is counted by the counter, and the counter is reset under the OR condition of detecting the change point of the data signal synchronized with the synchronization clock signal, and the counter is set to a predetermined value. A sampling clock signal is generated when a number of synchronization clock signals are counted.

Further, the data signal sampling circuit according to the present invention is a circuit for sampling a digital data signal by a sampling clock signal, which is M (M is an integer or a value close to an integer) times the data rate of the data signal. A synchronizing circuit for synchronizing the data signal with the frequency synchronizing clock signal, a detecting circuit for detecting a change point of the data signal output from the synchronizing circuit and outputting a detection output signal, and the synchronizing clock signal A counter that counts, a reset circuit that outputs a reset signal when the count value of the counter reaches a number corresponding to nM synchronization clock signals or an integer number close to nM, and the counter has a predetermined number. A sampling clock that generates a sampling clock signal when counting the synchronization clock signal And a signal output unit, the counter, characterized in that it is reset when at least one of the detection output signal or a reset signal is input.

[0010]

According to the present invention, the data signal is synchronized with the synchronizing clock signal as described above, the synchronizing clock signal is counted, sampling is performed based on the count value, and the data is used as the reset timing of the counter. The sampling clock signal is self-adjusted by the data signal because the time when the signal change point is detected is incorporated. If such self-adjustment is not performed, if the frequency stability of the synchronizing clock signal is not so high or if f _{C of the} synchronizing clock signal is not a perfect integer multiple of the data rate f _D. In such cases, the timing of the sampling clock signal deviates from the center of the minimum pulse width of the data signal, and this causes integration and sampling of bits that deviate from the bits that should be sampled due to the integration error. If the timing of the clock signal is self-adjusted based on the data signal as described above, the integration error disappears at the time of the adjustment, and accurate sampling can be performed. For systems with different data rates, it is sufficient to generate a synchronization clock signal having a frequency corresponding to the data, that is, a synchronization clock signal with f _C = Mf _D , so that data signals with different data rates are sampled. A common sampling circuit can be used for this.

Further, in the present invention, it is desirable to sample a point corresponding to a position of half the minimum width of the data signal as in the example shown in FIG. For the reason,
When sampling is performed only for the longest period of "L" data in a certain data, that is, for the longest period in which no pulse change point exists, the integration error needs to be less than 1/2 of the minimum pulse width of the data signal. Therefore, the synchronization clock signal must have frequency accuracy that satisfies this condition (however, the required frequency accuracy depends on the value of M). On the other hand, other than the point of 1/2 of the minimum pulse width, for example, 1/3, 2
If points such as / 3 are sampled, the allowable integration error becomes a value smaller than 1/2 of the minimum pulse width, for example, less than 1/3, and the allowable frequency accuracy becomes strict. This is because it is a design disadvantage.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the sampling method of the present invention is applied to a sampling circuit of an image receiving device will be described below. FIG. 2 is a diagram showing a part of a video signal of a television,
A data signal (vertical blanking information data (VBI data)) carrying predetermined information is included between the horizontal synchronization signals HP in the vertical blanking period. VD is a video signal, and VS is a vertical synchronizing signal. Figure 3
FIG. 3 is a circuit diagram showing a part of an image receiving device including a sampling circuit for sampling the data signal (VBI data).

In the figure, reference numeral 1 is a synchronizer (synchronization circuit) for synchronizing the VBI data from the receiving section 10 with the synchronization clock signal SC. The synchronizing clock signal SC is the horizontal synchronizing signal (pulse) HP multiplied by N (N is an integer) in this embodiment, and the receiving unit 1
A horizontal synchronizing signal HP from 0 is generated through a PLL (phase lock loop) circuit 2. In the PLL circuit 2, 21 is a phase comparator, 22 is a low-pass filter, and 23.
Is a voltage controlled oscillator, and 24 is a divider for making 1 / N (N is variable). That is, in this embodiment, VP
Using a PLL circuit 2 in order to obtain a synchronization clock signal of M times the data rate f _D of the I data, such that the frequency of the synchronizing clock signal is Mf _D, i.e. Mf _D = Nf _H
The value of N is set so that

In the subsequent stage of the synchronizer 1, a change point of VBI data synchronized with the synchronizing clock signal sc by the synchronizer 1, for example, a rising edge of a pulse is detected, and a detection output signal eg pulse is output at the time of detection. The differentiating circuit 3 as a circuit is connected.

A counter 4 is connected to the subsequent stage of the differentiating circuit 3 via an OR circuit 31. The counter 4 counts the synchronization clock signal sc, and its output (count value) is input to one input terminal of the first binary comparator 5 and the second binary comparator 6 that form a reset circuit. It The first binary comparator 5 outputs a reset signal rc to the counter 4 through the OR circuit 31 when the numerical value set by the numerical value setting unit 7 and the count value of the counter 4 match. The numerical value setting unit 7 sets a numerical value for determining the timing of a sampling clock signal, which will be described later. In this embodiment, since the count value of the counter 4 starts from "0", the counter 4 synchronizes with the clock for synchronization. In order to reset each time the signal SC is counted M times, the value of "M-1" is set.

The numerical value signal set by the numerical value setting unit 7 is input to the first binary comparator 5 as described above, while it is halved by the divider 71 (M-1). / 2, and in this case, the part after the decimal point is truncated and becomes "1", which is input to the second binary comparator 6. The second binary comparator 6 corresponds to the sampling clock signal output unit of the present invention, takes in the count value of the counter 4, and the value becomes "1" which is the output of the divider 71. Then, the sampling clock signal smpl is output to one input terminal of the buffer circuit 8 including, for example, a D flip-flop.

The buffer circuit 8 has the other input terminal,
A data signal (VBI data) synchronized with the synchronizing clock signal SC in the synchronizer 1 is input through a delay circuit 11, and the sampling clock signal smpl is input.
Then, the data signal is sampled and sent to the data processing unit 80 in the subsequent stage. Since the delay circuit 11 delays by one cycle of the synchronizing clock signal sc before the counter 4 is reset after the differentiating circuit 3 detects the rise from the synchronizer 1 in this embodiment, the data from the synchronizer 1 to be sampled is delayed. It is provided in order to delay the signal by a similar time so as not to cause a deviation in sampling timing.

Next, the operation of the above embodiment will be described. For example, the frequency f _c of the synchronizing clock signal is set to four times f _D (M = 4) with respect to the data rate f _{D of the} data signal. The value of M is set by determining N based on the frequency f _H of the horizontal synchronizing signal HP so that f _D = (N / M) · f _H = (1 / M) · f _c. . Since N in the PLL circuit 2 is variable, the value of N is adjusted so that M = 4. However, if M cannot be completely set to an integer because of the values of f _D , N, and f _H, a value close to an integer, for example, a value close to 4 is set.

When the data signals are synchronized by using such a synchronizing clock signal sc, both of them are respectively shown in FIG.
It is represented as shown in (b). If one pulse, which is the minimum unit of data, arrives at some point in the data signal from the synchronizer 1, the rising edge is detected by the differentiating circuit 3 and the detection output signal of the differentiating circuit 3 (see FIG.
The counter 4 is reset to "0" by the reference. Then, the counter 4 counts the synchronization clock signal sc, and the counter value increases as “0, 1, 2, 3” as shown in FIG. 4D, but it is half of M (4 in this case). When the number of synchronization clock signals sc is counted, that is, the count value of the first pulse is “0”, the second binary number is output when the counter value matches “1” which is the output of the divider 71. The comparator 6 outputs the sampling signal smpl as shown in FIG.

However, in this example, since one cycle of the synchronizing clock signal is spent from the output of the rising edge detection output signal from the differentiating circuit 3 to the resetting of the counter 4, the timing deviation is corrected. In order to do so, the data signal from the synchronizer 1 is delayed by the delay circuit 11, and the data signal (see FIG. 4 (f)) is sampled by the sampling signal smpl. After that, if the pulse of the data signal falls and the data of "L" continues, the counter 4 counts "4" each time it counts four synchronization clock signals.
Is reset each time, and the count value is "1"
The sampling signal is output from the second binary comparator 6 every time. When "H" data comes in the data signal and the pulse rises, the detection output signal resets the counter 4 in the same manner as described above.

As described above, according to the above-described embodiment, since the change point of the data signal is detected and the sampling timing is self-adjusted, even if the frequency accuracy of the synchronizing clock signal is not so high, the "problem" Means To Solve "
As described in the above section, if the accumulated error is less than ½ of the minimum pulse width of the data signal when sampling is performed for the longest period in which the “L” data continues, erroneous bits are not sampled, Accurate sampling can be performed even for a data signal having a high data rate such as teletext.

For a predetermined value of M, f _D = (N
If the N of the PLL circuit 2 is adjusted so as to satisfy / M) · f _H , not only a data signal having one data rate but also a data signal having another data rate can be sampled. Further, there is an advantage that the system can be made common to various data signals having different data rates, and the cost can be kept low because it is not necessary to use a crystal resonator or a ceramic resonator having a high Q.

In the above description, in the present invention, M is not limited to 4 and may be an integer other than 4, but 1 in the synchronizer.
It is necessary to set within a range that does not deviate by the pulse synchronization skew, 4 or more is preferable, and further n (n is an integer)
The counter may be reset when the counter counts an integer close to M or nM. In this case, it is reset when counting n pulses of the minimum width pulse. For example, if M = 4, it is reset when counting 8 synchronization clock signals, and for example, 2 and 6 synchronization clock signals are reset. The sampling clock signal may be output when the clock signals are counted. Further, the synchronizing clock signal is not limited to being generated based on the horizontal synchronizing clock signal, and other signals may be used. The present invention is not limited to VBI data of video signals and may be applied to the case of sampling data signals in other fields.

[0024]

As described above, according to the present invention, since the output timing of the sampling clock signal is self-adjusted based on the data signal, a high data rate can be achieved while using a clock signal whose frequency accuracy is not so high. The data signal that it has can be sampled. Further, the sampling circuit can be made common for data signals having different data rates.

[Brief description of drawings]

FIG. 1 is a time chart showing a data signal, a synchronizing clock signal, and a sampling clock signal for explaining the method of the present invention.

FIG. 2 is an explanatory diagram showing an example of a video signal including vertical blanking information data.

FIG. 3 is a circuit diagram showing a sampling circuit according to an embodiment of the present invention.

FIG. 4 is a time chart diagram showing the operation of the embodiment of the present invention.

FIG. 5 is an explanatory diagram showing an example of a data signal.

[Explanation of symbols]

 1 synchronizer (synchronization circuit) 2 phase lock loop circuit 3 differentiating circuit 4 counter 5 first binary comparator 6 second binary comparator 8 sampling clock signal output section

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Claims (2)

[Claims] 1. A method of sampling a digital data signal with a sampling clock signal, wherein a synchronization clock signal having a frequency M times M (M is an integer or a value close to an integer) times the data rate of the data signal is used.
The data signal is synchronized with the synchronizing clock signal, and the synchronizing clock signal is counted by a counter by n (n is an integer) M or an integer close to nM, and the data signal synchronized with the synchronizing clock signal is counted. Reset the counter under the OR condition of detecting the change point,
A sampling method of a data signal, wherein a sampling clock signal is generated when the counter counts a predetermined number of synchronization clock signals. 2. A circuit for sampling a digital data signal by a sampling clock signal, wherein the data signal is a synchronization clock signal having a frequency M times (M is an integer or a value close to an integer) times the data rate of the data signal. A synchronization circuit for synchronizing, a detection circuit for detecting a change point of the data signal output from the synchronization circuit and outputting a detection output signal, a counter for counting the synchronization clock signal, and a count value of this counter Is the synchronization clock signal nM
A reset circuit that outputs a reset signal when the number reaches a number corresponding to an integer number or nM, and a sampling clock that generates a sampling clock signal when the counter counts a predetermined number of synchronization clock signals A signal output unit, wherein the counter is reset when at least one of the detection output signal and the reset signal is input, the sampling circuit of the data signal.